JPH0534472A - Time measurement circuit - Google Patents

Abstract

PURPOSE:To improve accuracy in measured value by providing a timing detection circuit, and by detecting plus or minus error based on the electric potential levels of a clock for rising as well as lowering timings of a time signal to be measured. CONSTITUTION:An output signal and a clock signal of a detection circuit 12 for time to be measured are received by a timing circuit 10, and an electric potential level of the clock signal when the electric potential level of the time signal to be measured is output to monitor terminals 17, 18. An error is judged to be plus level when the clock is in a high level regardless of rising or lowering state of the time signal to be measured, while it is judged to be minus level when the clock is in low level regardless of rising or lowering state of the time signal to be measured. An actual value and a measured value are close to each other when one of either rising or lowering state of the time signal to be measured is at clock high level, while the other is at low level. Since an estimated value is determined according to the electric potential level of the clock signal at the times of starting and finishing times of the time to be measured, a maximum value of the error is reduced to a semi-clock period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time measuring circuit, and more particularly to a time measuring circuit having high measurement accuracy.

[0002]

2. Description of the Related Art FIG. 5 shows an example of a conventional time measuring circuit, and FIG. 6 shows a timing chart showing an operation example of the conventional circuit of FIG.

In FIG. 5, the conventional circuit is the input terminals 13 and 14 of the signals 1 and 2 to be measured and the measured time detection circuit 1.
2, clock signal input terminal 15, AND gate (AN
D1) 21, an edge counter circuit 11, and an output terminal group 16. The measured time detection circuit 12 is
Inverter (G1) 19 and NOR gate (NOR1)
Have and.

In the conventional circuit, the measured time detection circuit 1
2 normally outputs a low level, and the target measurement time is set high by the input terminal group.
It is a circuit that detects a level and outputs the measured time signal 30.

For example, the time from the rising time of the signal under test 1 shown in FIG. 5 to the rising time of the signal under test 2 is detected by the inverter 19 and the NOR gate 20, and the time under measurement signal 30 shown in FIG. Is output as.

The high level output time in the measured time signal 30 is the measured time, and therefore the number of rising edges or the number of rising edges in the logical product of the measured time signal 30 and the clock signal of a known proper period. According to the count by the edge counter circuit 11, the High level output time of the measured time signal 30, that is, the measured time depends on the count result and the clock cycle.
Can be estimated.

[0007]

In the conventional time measuring circuit, the comparison between the measured time signal 30 and the logic of the clock signal is performed at random timing. Therefore,
The number of rising or falling edges in the logical product of the measured time signal 30 and the clock signal depends on the timing between the measured time signal and the clock signal. However, since there is no function of monitoring the timing between the measured time signal and the clock signal, the count result n of the number of rising or falling edges of the logical product is
It looks like this:

(1) When the rising time of the measured time signal is immediately before the falling time of the clock signal and the falling time of the measured time signal is immediately after the rising time of the clock signal, the actual The measurement time is the minimum value (n-1.5) × clock period.

(2) When the rising time of the measured time signal is immediately after the falling time of the clock signal and the falling time of the measured time signal is immediately before the rising time of the clock signal, the actual measurement is performed. The time is the maximum value (n + 0.5) × clock period.

That is, with respect to the count result n, the value that can be taken as the measurement time is (n-1.5) × clock cycle <the value that can be taken as the measurement time <(n + 0.5) × clock cycle, which is an intermediate value. When the value (n−0.5) × clock cycle is adopted as the estimated value of the measurement time, the error between the estimated value of the measured time and the true value is ± 1 × clock cycle at the maximum, and the reliability of the estimated value with respect to the true value. There is a problem that the property is low.

An object of the present invention is to solve the above problems and provide a time measuring circuit in which the reliability of the estimated value with respect to the true value is not lowered.

[0012]

SUMMARY OF THE INVENTION The structure of the present invention is a time period including an input terminal group for a signal under measurement, a measured time detection circuit, an input terminal for a clock signal, an AND gate, and an edge counter circuit. In the measurement circuit, the output signal of the measured time detection circuit and the clock signal are received, and the potential level of the clock signal at the time when the potential level of the measured time signal changes is output to a monitor output terminal, respectively. And a timing detection circuit for

[0013]

1 is a block diagram showing a time measuring circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram specifically showing the timing detecting circuit of FIG.

FIG. 3 is a timing chart showing an operation example of the circuit of FIG. 1, when the clock signal potential level at the start time and end time of the measured time is low level.

FIG. 4 is a timing chart showing an operation example of the circuit of FIG. 1, when the clock signal potential level at the start time and end time of the measured time is high level.

In FIG. 1, this embodiment has a reset signal input terminal 50, a timing detection circuit 10, and monitor output terminals (1) (2) 17, 18 in addition to the circuit of FIG.

The timing detection circuit 10 includes a D-type flip-flop (DFF) 47, 48 and an R / S-type latch 4.
5, 46, inverters 40, 44, 49, NOR2 gate 41, AND2, 3 gates 42, 43.

In FIG. 2, the measured time detection circuit 12,
The measurement function of the AND gate 21 and the edge counter circuit 11 has the same conventional function.

In the timing detection circuit of FIG. 2, the flip-flops 47 and 48 read the potential level of the input D at the Low level of the clock signal (CK), and set it to High.
It is a D-type flip-flop that outputs the potential level of the output Q at the level.

Therefore, the flip-flop 47 is normally Low.
This is a level output, and outputs a high level only for the time from the rising time of the clock signal for the first time after the start time of the measured time to the rising time of the clock signal for the first time after the end time of the measured time.

The flip-flop normally outputs a Low level signal, and is the time from the falling time of the clock signal for the first time after the start time of the measured time to the falling time of the clock signal for the first time after the end time of the measured time, Hi.
Output gh level.

Therefore, the next-stage NOR gate (NOR2) 41
Is normally Low level, and the potential level of the clock signal at the measured time start time 12 is Lo.
When w, the time Hi from the rising time of the clock signal immediately after the measured time start time to the next falling time Hi
GH level is output, and when the potential level of the clock signal at the end time of the measured time is High, the High level is output for the time from the falling time of the clock signal immediately after the end time of the measured time to the next rising time. To do.

Further, the output signal of the NOR gate 41 is
AND gates 42 and 43 divide the signal into a clock signal potential level monitor signal at the start time of the measured time and a clock signal potential level monitor signal at the end time of the measured time.
Depending on the presence or absence of the high level output state, the potential level of the clock signal at the start time of the measured time is further
The potential level of the clock signal at the end time of the measured time can be determined by the presence / absence of the high level output state in the output signal of the ND gate 43.

Therefore, by setting the output signals of the AND gates 42 and 43 as the set input signals of the R / S latch 45 and the R / S latch 46, the clock signal potential level at the start time and the end time of the measured time is set. , Output Q of the R / S latch 45 and output Q (negative value) of the R / S latch 46, respectively.

When the count result n of the rising or falling edge of the clock signal in the measured time signal is a value that can be taken as the measurement time, the value that can be obtained is as follows depending on the potential level of the clock signal at the start time and the end time of the measured time. The intermediate value is adopted as the estimated value of the measured time under each condition.

(A) When both the potential level of the clock signal at the start time of the measured time and the potential level of the clock signal at the end time of the measured time are High level, (n-1.5) × clock period <measured Possible value of time <(n-0.5) x clock period.

(B) When the potential level of the clock signal at the start time of the measured time is different from the potential level of the clock signal at the end time of the measured time, (n-1)
× clock cycle <value that can be taken as measurement time <n × clock cycle.

(C) When the potential level of the clock signal at the start time of the measured time and the potential level of the clock signal at the end time of the measured time are both low, (n-0.5) <clock cycle <measured Possible value of time <(n + 0.5) × clock period.

As described above, according to the present embodiment, only the input terminal group of the signal under measurement and the target measured time of the signal under measurement input to the input terminal group of the signal under measurement are detected at the High level, Is a low-time output measured time detection circuit and a clock signal input terminal, a 2-input AND gate having the clock signal and the output signal of the measured time detection circuit as input signals, and an output signal of the AND gate. As an input signal, having an edge counter circuit having a function of counting and outputting the number of rising or falling edges in this input signal, further, the output signal of the measured time detection circuit, and the clock signal as an input signal respectively, Changes in the potential level of the output signal of the measured time detection circuit (Low → High and High → Lo
It is characterized by comprising a timing detection circuit having a function of detecting the potential level of the clock signal at the time of w) and outputting it to the monitor output terminals 1 and 2, respectively.

[0030]

As described above, according to the present invention, the estimation of the measurement time based on the counting result n of the rising or falling edge of the clock signal in the measured time signal is always (n-0.5) × in the past. The estimated value is determined in the clock cycle, whereas the estimated value is determined according to the potential level of the clock signal at the start time and end time of the measured time.

Therefore, according to the present invention, the maximum value of the error between the estimated value of the measured time and the true value can be reduced to ± 0.5 × clock cycle in contrast to the conventional ± 1 × clock cycle. is there.

[Brief description of drawings]

FIG. 1 is a block diagram showing a time measuring circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram specifically showing the timing detection circuit of FIG.

3 is a timing diagram showing an example of the operation of the circuit of FIG.

4 is a timing diagram showing another example of the operation of the circuit of FIG.

FIG. 5 is a circuit diagram showing a conventional time measurement circuit.

FIG. 6 is a timing chart showing an operation example of FIG.

[Explanation of symbols]

D D-type flip-flop data input terminal CK D-type flip-flop clock input terminal S R / S latch set terminal R R / S latch reset terminal Q, Q (negative value) D-type flip-flop, R / S latch output terminal 10 Timing Detection circuit 11 Edge counter circuit 12 Measured time detection circuit 13 Measured signal 1 input terminal 14 Measured signal 2 input terminal 15 Clock signal input terminal 16 Output terminal group 17 Monitor output terminal 1 18 Monitor output terminal 2 19, 40, 44 , 49 Inverter 20,41 NOR gate 21, 42,43 AND gate 47,48 D-type flip-flop 45,46 R / S latch

Claims (1)

Claim: What is claimed is: 1. A time measuring circuit comprising a group of input terminals for a signal under measurement, a measured time detection circuit, an input terminal for a clock signal, an AND gate, and an edge counter circuit, Timing detection circuit that receives the output signal of the measured time detection circuit and the clock signal, and converts the potential level of the clock signal at the time when the potential level of the measured time signal changes to an output signal to a monitor output terminal, respectively. A time measuring circuit characterized by comprising.