JPH05344426A - Automatic defect correction circuit for solid-state image pickup element - Google Patents

Abstract

PURPOSE:To detect accurately a defect picture element even in a video camera in which an image is picked up by selecting the field read mode or the frame read mode. CONSTITUTION:This circuit is provided with a read mode changeover switch 23 to read an image pickup signal from a CCD 2 in the field read mode or the frame read mode, a system controller 4 to detect a defect picture element, a timing generator 5, a switch 20, a processing circuit 21 before detection, a detection circuit 22, a detection mode switch 24, a system controller 4 generating a control signal in the detection mode to control the mode to be the frame read mode forcibly, a timing generator 5, a read/write circuit 12 to store the detected defect picture element information, a memory 13, a system controller 4 to correct the output by the defect picture element based on the defect picture element information obtained therefrom, a timing generator 5, a correction control circuit 15 and a correction circuit 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic defect correction circuit for a solid-state image pickup device, which is suitable for application to, for example, a video camera capable of selectively switching between a field read mode and a frame read mode.

[0002]

2. Description of the Related Art A CCD (Charge couple)
In a video camera using a solid-state image sensor such as a device, an image obtained by picking up a so-called defective pixel that outputs a signal of a specific level even when no light is incident on each pixel of the CCD There was a problem that the image quality of was deteriorated.

Therefore, conventionally, a correction circuit for correcting a signal output from a defective pixel is mounted on a video camera, and before shipping the video camera to a user, it is checked which pixel of the CCD is the defective pixel. The information indicating the defective pixel obtained as a result of the inspection is stored in the storage area of the correction circuit of the video camera, etc., and the defective pixel is output by this correction circuit after it actually reaches the user's hand. The signal was corrected by the correction circuit.

As a method of this correction, interpolation such as 0th-order interpolation or 1st-order interpolation is considered.

Of these, the 0th-order interpolation is a method in which the signal output from the defective pixel is held in the sampling circuit and the signal output from the defective pixel is replaced with the signal of the immediately preceding pixel.

In the primary interpolation, the average value of the signal output from the pixel immediately before the defective pixel and the signal output from the pixel next to the defective pixel is obtained, and the signal output from the defective pixel is averaged. This is a method of replacing with a signal.

In the present specification, the above-mentioned zero-order interpolation and 1
The correction method by the interpolation such as the next interpolation will be referred to as the first correction method. As a method without interpolation, a signal corresponding to the signal output from the defective pixel is generated inside the video camera, and the generated signal is subtracted from the signal output from the defective pixel to output the signal from the defective pixel. It is also known how to offset the. This correction method is referred to as a second correction method in this specification.

By the way, the constituent pixels of the CCD may not only be defective at the manufacturing stage, but also may be suddenly defective even after actually reaching the user's hand. There is a case where a signal with a peculiar level is generated in the state where is not incident.

Therefore, the CC used in the video camera
When the defective pixel of D is inspected to obtain information such as address data of the defective pixel and the information is stored in the memory of the video camera and then passed to the user's hand, the above-mentioned sudden defective pixel It is not possible to deal with the occurrence of defective pixels due to the occurrence of defects and aging.

Therefore, recently, a circuit for detecting a defective pixel is further installed inside the video camera, the defective pixel is detected by the circuit for detecting the defective pixel, and the information on the defective pixel obtained by the detection is detected by the video camera. Has been proposed, and a method of correcting a newly generated defective pixel based on this information is proposed.

Detection of defective pixels is performed as follows, for example. In other words, when no light is incident on the CCD, C
The level of the signal output from each pixel of the CD is compared with the level of the signal output from the pixel immediately before this pixel, or the level of the signal output from each pixel of the CCD is compared with a predetermined threshold level. However, when the level of the signal output by the previous pixel or the level of the signal output by the current pixel is higher than the threshold level, it is detected as a pixel (defective pixel) that outputs a signal of a peculiar level, This is performed by obtaining address data of this pixel and scratch (defective pixel) data based on the signal level output from the pixel and storing these in a memory or the like.

On the other hand, after the defective pixel is detected as described above, based on the address data of the defective pixel stored in the memory, the signal corresponding to the defective pixel of the video signal supplied from the CCD is described above. By the first correction method and the second correction method, a signal having a unique level due to the defective pixel is corrected.

[0013]

By the way, there are conventionally a field read mode and a frame read mode as a method of reading a signal from a CCD. In recent video cameras, both the field read mode and the frame read mode are used. Since many of these video cameras are capable of doing so, it is necessary to accurately detect defective pixels even in such a video camera. The two read modes will be described with reference to FIGS. 25 and 26.

In the field read mode, as shown in FIG. 25, charges are read from pixels in two columns adjacent to each other to a transfer section (vertical transfer register). Then, in the vertical transfer register, charges from pixels in two adjacent columns are added, and then the sequentially added charges are transferred to the horizontal transfer register.

That is, as shown in FIG. 25A, in the odd field, the charge read from the photosensitive section I41 (or I42) and the charge read from the photosensitive section I31 (or I32) are added in the transfer section, and the photosensitive section is added. The charge read from I21 (or I22) and the photosensitive section I11 (or I
The charge read from 12) is added by the transfer unit, and then added to a horizontal transfer register (not shown). And FIG.
As shown in B, in the even field, the photosensitive portion I
The charge read from 41 (or I42) is transferred to the transfer unit, and the charge read from the photosensitive unit I31 (or I32) and the charge read from the photosensitive unit I21 (or I22) are added by the transfer unit to obtain the photosensitive unit I11. The charges read from (or I12) are transferred to the transfer unit, and then transferred to a horizontal transfer register (not shown). In this field read mode, the charge is read out from the missing pixels in one field cycle, so the dynamic resolution is poor, but the vertical resolution is poor because the charges of pixels in vertically adjacent columns are added.

On the other hand, in the frame read mode, as shown in FIG.
As shown in FIG. 6, among the vertically adjacent columns, the charge of the pixel in one column is read in the odd field and the charge in the other column is read in the even field. That is, as shown in FIG. 26A, in the odd-numbered field, the charges read from the photosensitive parts I31, I11, I32, and I12 are transferred to the transfer part. Then, as shown in FIG. 26B, in the even field, the photosensitive portion I4
The charges read from 1, I21, I42, and I22 are transferred to the transfer unit.

As is apparent from the above description, in the field read mode, the charge is read out in each pixel in one field cycle, so the dynamic resolution is good, but the charges in the pixels in the vertically adjacent columns are added. Therefore, the vertical resolution is poor. On the other hand, in the frame read mode, since the charges of pixels in vertically adjacent columns are not added, the vertical resolution is good, but the charge read in each pixel is 1
Since the frame period is used, the dynamic resolution is poor. Therefore, in general use, one of the two modes is switched by a change-over switch or the like depending on the shooting conditions.

Therefore, the present invention has been made in consideration of such a point, and a defective pixel can be accurately detected in a video camera capable of selectively switching between the field read mode and the frame read mode. An attempt is made to propose an automatic defect correction circuit for a solid-state image sensor.

[0019]

The present invention provides a solid-state image pickup device 2
From the read control means 23, 4 and 5 for reading the image pickup signal in the first and second read modes, and the information of the defective pixel that outputs a signal of a unique level among the pixels of the solid-state image pickup device 2. Defect detecting means 4, 20, 21, 22
And a selection means for selecting a detection mode or a normal imaging mode in which the defect detection means 4, 20, 21, 22 detects information on a defective pixel that outputs a signal of a unique level among the pixels of the solid-state imaging device 2. 24 and the read control means 2 when the detection mode is selected by the selection means 24.
A control signal is supplied to 3, 4, and 5 to control the read mode from the solid-state image pickup device 2 to be forced to the second read mode, and at the same time, the defect detection means 4, 20, 21, and 2.
Defect detection control means 4 and 5 for causing the defective pixel information detection section 2 to detect defective pixel information, and storage means 12 and 1 for storing information on defective pixels detected by the defect detection means 4, 20, 21, and 22.
3 and correction means 4, 5, 15, 16 for correcting a signal of a specific level due to the defective pixel based on the information of the defective pixel stored in the storage means 12, 13.

[0020]

According to the present invention described above, the solid-state image pickup device 2 by the defect detection means 4, 20, 21, 22 for detecting the information of the defective pixel which outputs a signal of a unique level among the pixels of the solid-state image pickup device 2. When the detection mode is selected by the selection means 24 for selecting the detection mode for detecting the information of the defective pixel that outputs a signal of a peculiar level of each of the pixels or the normal imaging mode, the defect detection control means 4, 5 Supplies a control signal to the read control means 23, 4, 5 to forcibly control the read mode from the solid-state imaging device 2 to the second read mode, and at the same time, the defect detection means 4,
The information of defective pixels is detected by 20, 21, and 22.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the automatic defect correction circuit for a solid-state image pickup device of the present invention will be described in detail below with reference to FIGS.

FIG. 1 is a block diagram showing an example in which the automatic defect correction circuit of the solid-state image pickup device of this embodiment is applied to a video camera. Hereinafter, with reference to FIG. 1, the solid-state image pickup device of this embodiment is applied to a video camera. The case will be described.

In FIG. 1, reference numeral 1 denotes an optical system such as a lens or an iris, and light from a subject is supplied to the CCD 2 via the optical system 1. In this example, for example, this CC
Let D2 be composed of three CCDs for green, red and blue components. In this case, the above-described optical system 1 includes a prism, which supplies the green component light of the light from the subject to the CCD 2 (for the green component light) and the red component light. It is supplied to this CCD2 (for red component light),
The light of the blue component is supplied to this CCD 2 (for the blue component light). The CCD 2 may be of a single plate type or a two plate type.

The light of the green, red and blue components supplied to the CCD 2 is photoelectrically converted in the CCD 2 (three CCDs), and the charge storage time is controlled by the charge storage control signal from the timing generator 5. The charges accumulated by the read signal from the timing generator 5 are read out.

As described above, the read mode of the CCD 2 includes the field read mode and the frame read mode, and the system controller 4 is operated by operating the read mode changeover switch 23.
Judges this and sends a signal to the timing generator 5 so that the reading mode of the CCD 2 can be switched.

Further, a detection mode switch 24 is provided, and by operating this detection mode switch 24, a defect detection mode for detecting a defective pixel, data detected in the defect detection mode, or data detected in advance before shipment. RO
The defect correction is performed based on the data stored in M or the like, and the operation mode is switched to obtain an image signal.

The CCD read mode includes a field read mode and a frame read mode.
In the field read mode, charges accumulated in vertically adjacent pixels are added and output, and the combination of addition is switched for each field. Therefore, the output from the defective pixel is odd (ODD) or even (EVEN). It will be output in both fields. In addition, since the upper and lower pixels are added, when only one of the vertically adjacent pixels is defective, the defect detection is performed after the output from the non-defective pixel is added, and the detection accuracy deteriorates.

On the other hand, in the frame read mode, since the outputs of vertically adjacent pixels are not added, the problem of the field read mode does not occur.

Therefore, in this example, when the detection mode is set, the read mode is forcibly switched to the frame read mode. That is, the detection mode switch 2
When the operation mode 4 is operated and the operation mode is changed to the defect detection mode, the system controller 4 determines which mode the read mode is.

When the read mode is the field read mode, a control signal is sent to the timing generator 5 to forcibly switch the read mode of the CCD 2 to the frame read mode.

Then, in the frame read mode, the output read from the CCD 2 is supplied to the sampling circuit 3, and in the sampling circuit 3, signals from the timing generator 5 and the pulse generator 8 are supplied as shown in FIG. Based on the output signal from the CCD2, sampling is performed at the precharge level shown by SHP and the data level shown by SHD in the figure to remove reset noise, and the sampled signals, that is, green, red and blue are supported. The generated signals are supplied to the adder circuits 9, 10 and 11, respectively.

These adder circuits 9, 10 and 11 add the correction signals corresponding to green, red and blue from the correction circuit 16 which will be described later to the signals corresponding to green, red and blue from the sampling circuit 3, respectively. The addition signals corresponding to green, red, and blue are supplied to other video signal processing circuits of a video camera (not shown) via output terminals 17, 18 and 19, respectively, and the fixed contacts 20a, 20b of the switch 20 and Two
Supply to 0c respectively.

Now, the switch 20 is provided for each adder circuit 9,
In addition to the fixed contacts 20a, 20b and 20c to which signals corresponding to green, red and blue from 10 and 11 are supplied, the CCD 2
Has a fixed contact 20d which is attached to the package of FIG. 2 and to which temperature information is supplied from a temperature sensor 7 for detecting the temperature of the CCD 2, and the switch includes a movable contact 20e and a fixed contact 20a, 20b, 20c and 20d. The signal and temperature information corresponding to green, red, and blue are supplied to the pre-detection processing circuit 21 by connecting to.

The pre-detection processing circuit 21 detects the discontinuous minute level of the carrier component of the signal corresponding to green, red and blue among the signals or temperature information corresponding to green, red and blue supplied from the switch 20. After removing the signal, the signals corresponding to green, red and blue from which the discontinuous minute level of the carrier component is removed, and the temperature information are converted into digital signals, and green,
Digital signals corresponding to red and blue are supplied to the detection circuit 22 and digital temperature data is supplied to the system controller 4.

The detection circuit 22 is a pre-detection processing circuit 21.
The low-pass filtering process was performed on the digital signals corresponding to green, red, and blue supplied from, and the comparison was made with the so-called threshold level for white defects that appear white on the screen and for black defects that appear black on the screen. Then, the result is supplied to the system controller 4.

The system controller 4 compares the result from the detection circuit 22 with the threshold level based on the digital temperature data, and the comparison result shows that the video signal corresponding to the result from the detection circuit 22 is the output signal of the defective pixel. When it is determined that the address signal from the horizontal / vertical counter 6 is stored in the register 14, various information related to the defective pixel is stored.

After the defect detection is completed, the address data of the defective pixel and various information stored in the register 14 are stored in the memory (for example, EEPROM or RA with battery backup) via the read / write circuit 12.
M, etc.) 13. Further, at the time of shipment to the user, data of defective pixels is stored in this memory 13, for example. The writing of the defective pixels to the memory 13 at the time of shipping is performed, for example, when the defective pixel data obtained as a result of detecting the defective pixels at the manufacturing stage of the CCD 2 is once recorded on a recording medium such as a floppy disk and is shipped as a product. Alternatively, a data writing device may be used to copy the defective pixel data recorded on the floppy disk by, for example, LANC communication. Imaging is performed while correcting the defective pixel detected in the defect detection mode and the defective pixel detected in the manufacturing stage. Then, the defective pixel detected in the defect detection mode is corrected by the above-described first correction method. In addition, the memory 13 is, for example, 2
It may be divided into two areas, one area being a non-volatile memory and the other area being a RAM or the like.

On the other hand, in the operation mode in which normal photographing is performed, the address signal of the defective pixel stored in the memory 13 is read, and this address signal and the horizontal / vertical counter 6 are read.
The address signals from the above are compared, and if they match each other, the pulse generator 8 and the timing generator 5 are controlled, and the signal portion corresponding to the defective pixel is sampled by the sampling circuit 3.
Hold at. Further, the defective pixel detected at the manufacturing stage is corrected by the above-described second correction method.

The system controller 4 also has a switch sw2 for supplying a shutter enable signal as a detection enable signal based on the setting information from the switch sw1.
Is turned on and off, and a detection enable signal is supplied to the detection circuit 22 to control the detection of defective pixels by the detection circuit 22. Therefore, for example, the switch sw1
When the user operates, the detection enable signal is supplied to the detection circuit 22 to enter the defect detection mode, and the switch sw2 is turned off by this detection enable signal, so that the shutter enable signal is not supplied to the timing generator 5. .. Therefore, the so-called shutter operation, which shortens the charge storage time in the CCD 2 shorter than the normal storage time, is not performed, the S / N deterioration of the detection of the defective pixel is reduced, and the defective pixel can be detected satisfactorily.

The defective pixel described above will now be described. As shown in FIG. 3, the defective pixel is a white point (white flaw) W1 that does not depend on the light amount but depends on the temperature, and a white point that depends on both the light amount and the temperature. There are points (white scratches) W2 and black dots (black scratches) B1, and black dots (black scratches) B2 that do not depend on the light amount but depend on the temperature. Therefore, in this example, in order to satisfy these conditions, the defective pixel is detected or corrected based on the temperature information from the temperature sensor 7.

Such a minute white spot (white fl)
aw defect and black flag
In the case of “defect”, a constant bias voltage is added or subtracted to the signal output of the defective pixel. The image signal component normally responds to the amount of incident light. Therefore, the position of the defective pixel and the amplitude of the defective component at a certain temperature are measured and stored in advance, and a correction signal having the same amplitude and the opposite polarity as the defective component is generated at the same timing as the signal output of the defective pixel. By adding it to the signal output of, the defect component of the video signal can be canceled. This corresponds to the second correction method described above. This state is shown in FIG.

FIG. 4 shows each waveform with the vertical axis representing the amplitude level (V) of the video signal and the horizontal axis representing the time (T).
Is the output signal out1 when the amount of light is large and the output signal ou when the amount of light is small.
It shows t2. The range indicated by the broken line corresponds to the output pulse for one pixel.

As shown in FIG. 4A, the minute white-spot pulse W and the minute black-spot pulse B output from the defective pixel are generated in both the large light quantity output signal out1 and the small light quantity output signal out2. ..

Output signal out at high light quantity shown in FIG. 4A
The minute white spot pulse W and the minute black spot pulse B of 1 are shown in FIG. 4B.
Minute white point correction pulse Wp and minute black point pulse Bp shown in
By adding a correction signal consisting of (compensated by the correction circuit 16 in FIG. 1), the minute white-spot corresponding pulse W and the minute black-spot corresponding pulse B are corrected as shown in FIG. 4C as the high light amount output signal out1. ing.

The minute white point pulse W and the minute black point pulse B of the output signal out2 at the small light quantity shown in FIG. 4A are
By adding the correction signal composed of the minute white spot correction pulse Wp and the minute black spot pulse Bp (outputted by the correction circuit 16 in FIG. 1) shown in FIG. 4B, as shown as a small light quantity output signal out2 in FIG. 4C, The minute white-spot corresponding pulse W and the minute black-spot corresponding pulse B are corrected.

Now, each part of the circuit of this embodiment shown in FIG. 1 will be described in more detail below with reference to FIGS.

First, the sampling circuit 3 shown in FIG. 1 will be described with reference to FIGS.

In FIG. 5, reference numeral 30 is a correlation double sampling circuit, and this correlation double sampling circuit 30 is supplied with a signal (video signal) corresponding to green from the CCD (green CCD) 2 shown in FIG. The input terminal 31 of the operational amplifier circuit 32 is connected to the input terminal of the amplifier circuit 32, and the output terminal of the amplifier circuit 32 is connected to the non-inverting input terminal (+) of the operational amplifier circuit 38 via the switch 33. Of the non-inverting input terminal (+) of the amplifier 37 is grounded via the capacitor 37, the output terminal of the operational amplifier circuit 38 is connected to the output terminal 45, and the output terminal of the amplifier circuit 32 is connected to the amplifier circuit 42 via the switch 40. This amplifier circuit 4 is connected to the input terminal
The second input terminal is grounded via the capacitor 41, the output terminal of the amplification circuit 42 is connected to the inverting input terminal (-) of the operational amplification circuit 38 via the switch 43, and the inverting input of the operational amplification circuit 38 is connected. Connect the terminal (-) to capacitor 4
4 through grounding.

The correlation double sampling circuit 3
The sample hold signal SHP from the timing generator 5 is supplied to the 0 switch 40 via the input terminal 39, and the switch 3 of the correlated double sampling circuit 30 is supplied.
The sample hold signal SHD from the AND circuit 36 is supplied to 3 and 43.

In the AND circuit 36, the sample-hold signal SHD supplied to the switches 33 and 43 is the signal supplied to the input terminal 34 of the sampling circuit 3 and the frame signal from the timing generator 5 for the signal corresponding to green. It is a signal obtained by taking a logical product.

Reference numeral 49 is a correlated double sampling circuit for a signal corresponding to red, and this correlated double sampling circuit 4
The configuration of 9 is similar to that of the correlated double sampling circuit 30. The input terminal 46 is connected to the correlated double sampling circuit 49.
A signal corresponding to red from the CCD (red CCD) 2 shown in FIG. 1 is supplied via the, and the output of the correlated double sampling circuit 49 is supplied to the output terminal 50. Although not shown, the switch 40 of the correlated double sampling circuit 49 is supplied with the sample hold signal SHP from the timing generator 5 via the input terminal 39, and the switches 33 and 43 of the correlated double sampling circuit 49 are supplied.
To the sample and hold signal SHD from the AND circuit 48.

Switches 33 and 43 not shown in the drawing
The sample-and-hold signal SHD supplied to the AND circuit 48 is obtained by ANDing the signal supplied to the input terminal 34 of the sampling circuit 3 and the frame signal from the timing generator 5 for the signal corresponding to red in the AND circuit 48. Signal.

Reference numeral 54 is a correlated double sampling circuit for the signal corresponding to blue.
The configuration of 4 is similar to that of the correlated double sampling circuit 30. The input terminal 51 is connected to the correlated double sampling circuit 54.
A signal corresponding to blue is supplied from the CCD (blue CCD) 2 shown in FIG. 1 via the, and the output of the correlated double sampling circuit 54 is supplied to the output terminal 55. Although not shown, the switch 40 of the correlated double sampling circuit 54 is supplied with the sample hold signal SHP from the timing generator 5 via the input terminal 39, and the switch 33 of the correlated double sampling circuit 54 and Four
Sample hold signal SHD from AND circuit 53
To supply.

Switches 33 and 43 (not shown)
The sample-and-hold signal SHD supplied to the AND circuit 53 is obtained by ANDing the signal supplied to the input terminal 34 of the sampling circuit 3 and the frame signal from the timing generator 5 for the signal corresponding to blue in the AND circuit 53. Signal.

The AND circuit 36, 48, and 53 is supplied with the signal shown in FIG. 6A, and the AND circuit 36 is provided with a signal (G) corresponding to green as shown in FIG. 6B in addition to this signal.
A frame signal from the timing generator 5 that is active for one frame for every three frames (ch) is supplied, and the logical product of these two signals is calculated to generate the sample hold signal SHD as shown in FIG. 6E.

Similarly, in addition to the signal shown in FIG. 6A, the AND circuit 48 receives a signal from the timing generator 5 which becomes active for every three frames which are for signals (Rch) corresponding to red as shown in FIG. 6C. A frame signal is provided, and the logical AND of these two signals is performed.
A sample hold signal SHD as shown by F is generated.

Similarly, the AND circuit 53 has a configuration shown in FIG.
In addition to the signal shown in FIG. 6D, a frame signal from the timing generator 5 that is active for one frame for every three frames for signals corresponding to blue (Bch) as shown in FIG. 6D is supplied, and the logical product of these two signals is supplied. Is taken,
A sample hold signal SHD as shown in FIG. 6G is generated.

Next, the operation of the sampling circuit 3 shown in FIG. 5 will be described with reference to FIG.

As shown in FIG. 7A, signals (G, G supplied from the CCD 2 to the sampling circuit 3 shown in FIG. 5).
R and Bch signals) have a precharge level shown in FIG.
B is sample-held by the sample-hold signal SHP (signal from the timing generator 5 supplied to the input terminal 39 in FIG. 5), and the data level of the signal shown in FIG. 7A is the sample-hold signal SHD shown in FIG. 5 is a signal corresponding to the outputs of the AND circuits 36, 48 and 53, and in FIG.
Corresponding to F and G respectively).

If the data level is the abnormal level pa as shown in FIG. 7A, the abnormal level pa is also output as shown in FIG. 7D in the normal operation. Therefore, as shown in FIG. 7E, a signal indicating the position of the abnormal level pa is used so as not to output a signal corresponding to this abnormal level pa among the sampling signals SHD shown in FIG. 7C (FIG. 7F). .. Thus, as shown in FIG. 7G, an abnormal level p of the output signal
The signal corresponding to a remains the output signal of the previous pixel, that is, the held state. Therefore, as shown in FIG. 7G, the abnormal levels pa are removed from the outputs from the respective output terminals 45, 50 and 55 of the correlated double sampling circuits 30, 49 and 54 connected to the operational amplifier circuit 38 shown in FIG. Output.

Further, as shown in FIG. 5, the operational amplifier circuit 3
A signal obtained by sampling the data level of each pixel is supplied to the non-inverting input terminal (+) of 8 and a signal obtained by sampling the data level of each pixel is supplied to the inverting input terminal (-) of the operational amplifier circuit 38. Therefore, the data potential of each pixel and the reset potential of each pixel are sampled and held, and the difference between these is obtained in the operational amplifier circuit 38, and this is output.

Therefore, the reset noise and the like, which are in-phase components between the reset potential and the data potential, can be removed.

As described above, in the sampling circuit 3, as shown in FIG. 6, the signal from the CCD 2 corresponding to green, the signal corresponding to red and the signal corresponding to blue, that is, Gch (channel), When sampling the outputs of Rch (channel) and Bch (channel) respectively, during sampling of Gch, Rch and Bc
Since sampling of h is stopped, sampling of Gch and Bch is stopped during sampling of Rch, and sampling of Gch and Rch is stopped during sampling of Bch, channels other than the channel that is sampling It is possible to prevent the deterioration of the defective pixel detection accuracy due to the so-called data jump from the.

FIG. 8 is a block diagram showing another example for preventing the jumping of data from a channel other than the above-described sampling channel. As shown in FIG. 8, in this example, CCD (R) 2R, CCD
The outputs from the (G) 2G and the CCD (B) 2B are supplied to the sampling circuit 133 via the switches 130, 131, and 132, respectively, and the output is output from the output terminal 135, and a control circuit separately provided. The control signal from 134 causes the switches 130, 131, and 132 to be sequentially turned on, for example, every frame period.

When the control signal output from the control circuit 134 is a signal as shown in FIGS. 6B, C and D, for example, the frame signal that becomes active for one frame period in the three frame periods shown in FIG. 6B is the switch 131. Is supplied to the sampling circuit 1 through the switch 131, and the switch 131 is turned on while the frame signal is active.
33 and is sampled. Next, a frame signal that is active for one frame period in the three frame periods shown in FIG.
30 is turned on while this frame signal is active, whereby the output from the CCD 2R is supplied to the sampling circuit 133 via the switch 130 and is sampled. Next, a frame signal that is active for one frame period in the three frame periods shown in FIG. 6D is supplied to the switch 132, and the switch 132 is turned on for the period when this frame signal is active,
As a result, the output from the CCD 2B is supplied to the sampling circuit 133 via the switch 132 and is sampled.

Therefore, also in this case, similarly to the sampling circuit 3 described in FIG. 5, a signal corresponding to green from the CCD 2G, a signal corresponding to red from the CCD 2R and a signal corresponding to blue from the CCD 2B, that is, Gc
h (channel), Rch (channel) and Bch
When sampling each of the (channel) outputs, since the Rch and Bch signals are not supplied to the sampling circuit 133 during Gch sampling, sampling is not performed and the Gch is not sampled during Rch sampling.
Since the signals of Bch and Bch are not supplied to the sampling circuit 133, sampling is not performed, and the signals of Gch and Rch are sampled by the sampling circuit 1 during sampling of Bch.
Since the signal is not supplied to the channel 33, sampling is not performed, so that it is possible to prevent deterioration of image quality due to so-called data jump from a channel other than the channel being sampled.

Next, the system controller 4 shown in FIG. 1 will be described with reference to FIG.

As shown in FIG. 9, in the system controller 4 shown in FIG.
The comparison circuit 60 is arranged in addition to the original circuit (not shown). That is, the output signal (comparison result signal) from the detection circuit 22 shown in FIG. 1 is supplied to the comparator 62 via the input terminal 61, and the digital temperature data from the detection preprocessing circuit 21 shown in FIG. The signal is supplied to the multiplication circuit 65 via the input terminal 63, and the threshold circuit 64 is supplied.
To the multiplying circuit 65. Then, in the multiplication circuit 65, the temperature sensor thermally coupled to the CCD 2 (see FIG. 1) is used for the threshold data from the threshold circuit 64.
Is detected, and this is modulated by the pre-detection processing circuit 21 by the digital temperature data converted to digital. Further, the modulated threshold data and the signal supplied from the detection circuit 22 are respectively supplied to a comparator 62, and the comparator 62 compares them, and the comparison result is output via an output terminal 66 to a system controller (not shown). 4 to the other circuits.

In this way, the threshold data for determining that this output is the output from the defective pixel, even if the output is from the defective pixel having the positive temperature characteristic, has the positive temperature characteristic. Therefore, the detection performance for the signal output by the defective pixel can be kept constant. Therefore, the dependency of the detection performance of the automatic defective pixel detection system on temperature is significantly reduced, and for example, it is possible to prevent erroneous detection of even an output of a minute defective pixel which is unnecessary in the application. It is possible to detect various defective pixels.

Next, the internal structure and operation of the register 14 shown in FIG. 1 will be described with reference to FIGS.

In FIG. 10, 70r, 70r +
70r + n are main registers, and these main registers 70r, 70r + 1, ..., 70r + n are field flags indicating an area for storing a horizontal address, an area for storing a vertical address, and the number of the field. Area where channel is stored, channel information (Rch, Gch
And Bch information) and an area in which time history data is stored. The information stored in each of these areas is information corresponding to the defective pixel.

The time history here is the number of times that a certain pixel is not detected as a defect, and in the present example, when a certain pixel is not detected as a defect 10 times, for example, this pixel is not regarded as a defective pixel. .. This is done because a certain pixel may or may not output a signal of a specific level (level as a defect) field by field, frame by frame, or irregularly. is there.

That is, as described above, when a pixel which outputs a signal of a peculiar level irregularly outputs a signal of a normal level at the time of defect detection, it is determined that the pixel is a normal pixel. Will be done. In addition, if the defective pixel is detected only once, when the pixel that outputs a signal of a normal level is erroneously detected as the defective pixel due to noise or the like, the data remains forever.

In this example, the pixel which outputs a signal of a peculiar level irregularly can be corrected as a defective pixel. Further, in this way, noise that is suddenly mixed into the video signal will not be erroneously detected as a defective pixel.

The main registers 70r, 70r + 1, ...
The information stored in 70r + n is the information of the pixel determined to be defective before the detection of the defective pixel is started this time, that is, at the present time.

72r, 72r + 1, ... 72r + n
Are auxiliary registers, and these auxiliary registers 72r and 7r
72r + n is an area in which a horizontal address is stored, an area in which a vertical address is stored, an area in which a field flag indicating the number of the field is stored, and channel information (Rch, Gch and Bch information).
Is stored, and an area in which time history data is stored. The information stored in each of these areas is information corresponding to the defective pixel, and the main registers 70r, 70r + 1, ...
The information of the defective pixel determined to be defective at the present time stored in 0r + n is stored in the auxiliary registers 72r, 72r + 1,
72r + 2, ..., 72r + n, respectively.

71c, 71c + 1, ... 71c + n
Are respective comparators, and auxiliary registers 72r, 72r + 1, ... Which are sequentially read from the data selector 73.
Defective pixel information from 72r + n and main registers 70r, 7
0r + 1, ... 70r + n is detected as a match of the position information, and, for example, the detection result is detected by the system controller 4
Transfer to.

Next, referring to FIG. 11 to FIG.
The operation of the register 14 shown in FIG.

In FIG. 11, the pixel information judged to be defective at the present time is stored in the main registers 70r, 70r + 1, 70r +.
2, ..., 70r + n. In the address area of the main register 70r, the address data of the defective pixel at address (x, x) is stored, and in the time history area, the time history data “8” is stored. Also, the main register 7
Address data of a defective pixel at address (y, y) is stored in the address area of 0r + 1, and time history data “3” is stored in the time history area. The address area of the main register 70r + 2 stores the address data of the defective pixel, which is the address (z, z), and the time history area "0" is stored.

For convenience of explanation, explanation of other information shown in FIG. 10 will be omitted.

First, before the detection, the main registers 70r and 70r are controlled by the control signal from the system controller 4.
, 70r + 2, 70r + 3, ... 70r + n, respectively, as shown in FIG.
2r + 1, 72r + 2, 72r + 3, ... 72r +
n, and then main registers 70r, 70r + 1, 7
The contents of 0r + 2, 70r + 3, ..., 70r + n are respectively cleared.

In each of FIGS. 11 to 18, a blank address column indicates a cleared state in which pixel information is not stored.

Now, the main registers 70r, 70r + 1, 7
After clearing the contents of 0r + 2, 70r + 3, ... 70r + n, the defective pixel is detected by the control of the system controller 4, and the information of the pixel judged to be defective is stored in the main registers 70r, 70r + 1, 70r + 2, 70r +.
3, ..., 70r + n, respectively. An example of this case is shown in FIG. As shown in FIG. 13, the address data of the defective pixel at address (x, x) is stored in the address area of the main register 70r, and the time history data "10" is stored in the time history area. In addition, the address data of the defective pixel at the address (v, v) is stored in the address area of the main register 70r + 1,
For example, the time history data “10” is stored in the time history area. Although not shown, information other than the address data and time history data of these defective pixels is also stored in the same manner.

Next, as shown by the hatched signal lines in FIG. 14, the contents of the auxiliary register 72r are changed to the data selector 73.
Information of the defective pixels read by the comparators 71c, 71c + 1, 71c + 2, 71.
c + 3, ..., 71c + n, respectively, and these comparators 71c, 71c + 1, 71c + 2, 71+
.., 71c + n, main registers 70r,
70r + 1, 70r + 2, 70r + 3, ... 70r
The information of the defective pixel read from + n is sequentially compared.

Then, the auxiliary registers 72r, 72r +
1, 72r + 2, 72r + 3, ... Address of defective pixel read to 72r + n and main registers 70r, 7
0r + 1, 70r + 2, 70r + 3, ... 70r +
It is determined whether the address of the defective pixel stored in n matches or does not match. At this time, it is necessary that both the horizontal address and the vertical address match. It goes without saying that the channel data also need to match.

In the example of FIG. 14, the auxiliary register 72r
Since the address data of the defective pixel information stored in (1) coincides with the address data of the defective pixel information stored in the main register 70r (channel data is the same if not shown), the comparator 71c A signal corresponding to the detection result is supplied to the system controller 4, for example.

Next, as shown by the hatched signal lines in FIG. 15, the contents of the auxiliary register 72r + 1 are read by the data selector 73, and the read information of the defective pixel is read by the comparators 71c, 71c + 1, 71c + 2.
71c + 3, ..., 71c + n, and these comparators 71c, 71c + 1, 71c + 2, 71+
.., 71c + n, main registers 70r,
70r + 1, 70r + 2, 70r + 3, ... 70r
The information of the defective pixel read from + n is sequentially compared.

In the example of FIG. 15, the auxiliary register 72r
The address data of the defective pixel information stored in +1 is the main registers 70r, 70r + 1, 70r + 2, 70r.
Since the address data of the defective pixel information stored in +3, ..., 70r + n respectively does not match, the comparators 71c, 71c + 1, 71c + 2, 7
1c + 3, ... 71c + n do not react. At this time, the time history data stored in the time history area of the auxiliary register 72r + 1 is "3", but "1" is subtracted from the time history data "3" stored in the auxiliary register 72r + 1. This time history data is set to "2", and the defective pixel information (only the time history data is set to "2") stored in the auxiliary register 72r + 1 is used as the unused main registers 70r + 2, 70r + 3, ... 70r + n. Stored in either In this case, the signal is stored in the unused main register 70r + 2 as shown by the hatched signal line in FIG.

Next, as shown by the hatched signal lines in FIG. 17, the contents of the auxiliary register 72r + 2 are read by the data selector 73, and the information of the read defective pixel is read by the comparators 71c, 71c + 1, 71c + 2,
71c + 3, ..., 71c + n, and these comparators 71c, 71c + 1, 71c + 2, 71+
.., 71c + n, main registers 70r,
70r + 1, 70r + 2, 70r + 3, ... 70r
The information of the defective pixel read from + n is sequentially compared.

In the example of FIG. 17, the auxiliary register 72r
The address data of the defective pixel information stored in +2 is the main registers 70r, 70r + 1, 70r + 2, 70r.
Since the address data of the defective pixel information stored in +3, ..., 70r + n respectively does not match, the comparators 71c, 71c + 1, 71c + 2, 7
1c + 3, ... 71c + n do not react. At this time, the time history data stored in the time history area of the auxiliary register 72r + 2 is "0".

This means that the pixel stored in the register as the defective pixel was not detected as the defective pixel ten times in a row. In this case, the data of the defective pixel is transferred to the main registers 70r, 70r + 1, 70r + 2, 7
0r + 3, ... Does not transfer to 70r + n.

Then, at the next defect detection, the main register 70
r, 70r + 1, 70r + 2, 70r + 3, ... 7
The data of 0r + n is the auxiliary registers 72r, 72r + 1,
72r + 2, 72r + 3, ... 72r + n, and auxiliary registers 72r, 72r + 1, 72r + 2, 7
Since the contents of 2r + 3, ..., 72r + n are rewritten, pixels that are not detected as defective pixels 10 times in a row are erased from the register. That is, in this case, the data of the defective pixel represented by the address data (z, z) is erased.

In this way, for example, if a pixel once determined to be defective at the time of detection is not determined to be defective ten times in succession during the detection period or at each detection, the corresponding pixel is determined to be a defective pixel. It wo n’t end up,
There is no possibility of making a mistaken determination as a defective pixel due to the mixing of noise.

In the above example, the case in which the time history data of a pixel once determined to be a defective pixel is sequentially decreased from "10", and when it becomes "0", the pixel is not considered to be a defective pixel will be described. However, for example, the time history data initially set is set to “0”, “1” is added every time it is not judged as a defect, and when the time history data becomes “10”, the pixel having the time history data is defective. It may be determined that the pixel is not a pixel.

Next, a case where the contents of the register 14 of FIG. 1 described with reference to FIGS. 11 to 18 are processed according to the temperature will be described.

The register 14 shown in FIG. 1 stores various pieces of information on defective pixels obtained as a result of the defective pixel detection processing. In this example, in performing the detection, two methods can be selectively adopted for handling various information of the defective pixel obtained by the detection before the current detection.

One is a method of erasing all the information of the previous defective pixel and detecting again, and the other is to correct the defective pixel with the information of the previous defective pixel and detect the defective pixel to newly detect it. This is a method of adding various kinds of information of the pixel detected as the defective pixel to the information of the defective pixel detected last time.

The defective pixel has a positive temperature characteristic, and the absolute value of the level of the signal output from the defective pixel increases as the temperature increases. Therefore, the former method has the advantage that erroneous data obtained by erroneous detection is erased, so that erroneous data does not remain, but on the other hand, if defective pixels are detected when the temperature is low, Since the level of the signal output from the defective pixel is low, there is a possibility of failing to detect a defective pixel that poses a problem at high temperatures.

On the other hand, in the latter method, since the data of the defective pixel is not erased, even if the defective pixel is detected in the low temperature state, if it is detected in the low temperature state last time, , Because that data is retained,
Even if the information of the originally defective pixel is not detected because it is detected at a low temperature, the previous data is maintained and there is no problem. However, if the previous data was data due to an erroneous detection, the data will not be deleted, which is a problem.

Therefore, in this example, the system controller 4 selects which of the above two methods is to be used each time it is detected, based on the temperature information from the temperature sensor 7 shown in FIG. To do. That is, when the temperature is low, the method of adding the information of the defective pixel obtained by the current detection to the above-mentioned previous detection data is adopted, and when the temperature is high, the previous detection data is deleted.

In this way, when the temperature is high,
By erasing the previously detected defective pixel information, accidentally erroneously detected data can be erased, and when the temperature is low, the defective pixel information detected this time is added to the previously detected defective pixel information to detect defects at low temperatures. Accidents in which pixels are not detected can be prevented, and thus a memory having a limited capacity can be effectively used, and reliable and highly accurate defective pixel detection can be performed, and good defective pixel correction can be performed.

It should be noted that the time history management method of the register 14 described with reference to FIGS. 10 to 18 and the method of erasing or adding information of the previously detected defective pixel depending on the temperature are used in combination. Is also good.

Next, the correction control circuit 15 shown in FIG. 1 will be described. In this example, the correction control circuit 15 shown in FIG. 1 supplies a control signal to the timing generator 5 via the system controller 4 based on the temperature data from the temperature sensor 7 to set the charge accumulation time in the CCD 2 to N. Make it variable within the double range.

That is, when the temperature of the CCD is equal to or lower than the predetermined temperature, the sensor gate pulse supplied to the CCD is once every several fields and is thinned out more than usual to extend the charge accumulation time. As a result, the output video signal is once every several fields, but there is no problem because it is in the defective pixel detection mode.

Therefore, in this example, the correction control circuit 1
5 is supplied from the temperature sensor 7 via the system controller 4 (note that the temperature sensor 7 or the detection preprocessing circuit 2
1 may be directly supplied). When temperature data is detected and the temperature is low, a control signal is supplied to the timing generator 5 via the system controller 4 in accordance with the temperature to accumulate charges in the CCD 2. Allow the time to be longer than normal and keep normal if the temperature is high.

Further, the correction control circuit 15 compares the temperature data supplied from the temperature sensor 7 via the system controller 4 with the reference temperature data, and when the supplied temperature data is lower than the reference temperature data, the correction circuit 16 To a low level "0", and when the temperature data supplied is higher than the reference temperature data, the control signal supplied to the correction circuit 16 is set to a high level "1".

As will be described later, when this control signal is low level "0", that is, when the temperature of the CCD 2 is low, the gain of the amplifier circuit of the correction circuit 16 is changed. As a result, the level of the correction signal supplied from the correction circuit 16 to each of the adder circuits 9, 10 and 11 can be varied.

Further, the correction control circuit 15 supplies a mask signal (enable signal of the analog switch 88) to an analog switch 88 (see FIG. 19) of the correction circuit 16 which will be described later, so that the signal output from the defective pixel by the temperature rise is output. When the level reaches a level that the correction circuit 16 cannot completely correct, the defective pixel is not corrected.

Next, the correction circuit 16 will be described with reference to FIG.

In FIG. 19, reference numeral 84 is an input terminal to which the control signal from the correction control circuit 15 shown in FIG. 1 is supplied. The control signal supplied to this input terminal 84 controls the on / off of the switch 85. To do. Reference numeral 80 is an input terminal to which the temperature information from the temperature sensor 7 is supplied, and this input terminal 80 is connected to the input terminal of the temperature characteristic circuit 81.
The temperature characteristic circuit 81 converts the temperature data supplied through the input terminal 80 so as to match the characteristics of the minute white point (the output of the positive electrode of the output of the defective pixel), and outputs the output obtained by this conversion to the temperature. It is supplied to the conversion circuit 82.

The temperature conversion circuit 82 is the temperature characteristic circuit 8
1 is connected to the inverting input terminal (-) of the operational amplifier circuit 83 via the resistor R1, the output terminal of this operational amplifier circuit 83 is connected to the input terminal of the DA converter 87, and this operational amplifier is connected. The output terminal of the circuit 83 is connected to the connection point of the resistor R1 and the temperature characteristic circuit 81, and the resistors R3 and R2 and the switch 85 are provided.
Connected via a series circuit of, the connection point of the resistors R3 and R2 is further connected to the inverting input terminal (-) of the operational amplifier circuit 83, and the non-inverting input terminal (+) of this operational amplifier circuit 83 is grounded. Consists of

As can be seen from FIG. 19, when the control signal supplied from the correction control circuit 15 via the input terminal 84 is low level "0", the switch 85 is opened and the gain of the temperature conversion circuit 82 is changed. When the control signal becomes high level "1", the gain of the temperature conversion circuit 82 becomes small.

Therefore, the output from the temperature characteristic circuit 81 is amplified by the operational amplifier circuit 83 with a gain according to the control signal at that time, and then the reference voltage input to the DA converter 87 is used as the reference voltage for the DA converter 87. Supplied to the terminal. The DA converter 87 converts the level data of the defective pixel read out from the memory (for example, ROM) 89 by the system controller 90 into an analog signal based on the reference voltage from the temperature conversion circuit 82, and the analog signal is converted into an analog signal. Supply to the switch 88.

The memory 89 stores the level data of the defective pixel in addition to the level data of the defective pixel described above. The system controller 90 stores the level data of the defective pixel stored in the memory 89 as D. −
The address signal corresponding to the level data of the defective pixel is supplied to the A converter 87, that is, the analog switch 88 is supplied with a pulse indicating which of the G, R, and B channels is to be corrected.

This analog switch 88 outputs the correction signal supplied from the DA converter 87 to the output terminal 91 for the G channel, the output terminal 92 for the R channel or the B channel according to the address signal from the system controller 90. It is supplied to the adder circuit 9, 10 or 11 shown in FIG. 1 via any of the output terminals 93, and is supplied from the DA converter 87 according to the mask signal supplied from the correction control circuit 15 via the input terminal 86. The supply of the corrected signal to the output terminal 91, 92 or 93 is determined.

Here, the mask signal will be described. Figure 7
As described above, in the sampling circuit 3, when the data level is the abnormal level pa, the abnormal level pa is also output in the normal operation. Therefore, the abnormal level pa Of the sampling signal SHD is not used to output a signal corresponding to this abnormal level pa. That is, the signal corresponding to the abnormal level pa of the output signal is kept as it is, ie, the state in which it is held.

By the way, when the sampling circuit 3 is configured to perform the correction by the first correction method, the above-described correction circuit 16 is configured to perform the correction by the second correction method. The output corrected by this correction method will also be corrected by the second correction method. Therefore, as described above, the supply of the correction signal supplied from the DA converter 87 to the output terminal 91, 92 or 93 is determined according to the mask signal supplied from the correction control circuit 15 via the input terminal 86. Is.

Now, the operation of the correction circuit 16 will be described with reference to FIG.

FIG. 20A shows the output from the sampling circuit 3 shown in FIG. 1. As shown in FIG.
The projecting portion shown by the slanted line is an offset of the charge having temperature dependency, and has a property that the level becomes large in proportion to the storage time for photoelectric conversion. That is, this corresponds to the output of the defective pixel, which becomes an output of a peculiar level on the projected image.

If this defective pixel is detected at the time of manufacture, the defective pixel is corrected by the second correction method of adding the correction signal shown in FIG. 20B to the output signal of the CCD 2 shown in FIG. 20A. You can cancel the output. However, there is a defective pixel whose output level changes with the passage of time, and as shown by the broken line in FIG. 20A, when the level output by the defective pixel increases with time, such as p20. There is.

In such a case, even if the output of the defective pixel is corrected by the second correction method, the level increase p20 indicated by the broken line in FIG. 20A appears as an output of a peculiar level in the output. If the output of the defective pixel is corrected by the first correction method here, as shown in FIG. 20C, the corresponding portion of the level increase p20 shown in FIG. 20A is replaced with the previous output.

When correction is performed by the second correction method using the waveform shown in FIG. 20B in the state shown in FIG. 20C, the level increase shown by the broken line in FIG. 20 is shown as shown by the hatched line in FIG. 20D. An output of the opposite polarity corresponding to the minute p20 will appear.

Therefore, in this example, a mask signal (for example, a pulse for two clocks) as shown in FIG. 20E is generated by the correction control circuit 15, and this mask signal is input through the input terminal 86 shown in FIG. Analog switch 8
Supply to 8. Then, the mask signal shown in FIG. 20E is set to the high level "1" by the analog switch 88.
In the case of
As indicated by a broken line at 0F, a portion p21 having a polarity opposite to that of the level increase amount p20 shown in FIG. 20B does not appear in the output.

Therefore, the output of the defective pixel whose output level changes depending on the temperature can be accurately corrected, and thus the accuracy of the correction of the output of the defective pixel can be improved and the defective pixel can be corrected satisfactorily.

As described above, the correction circuit 16
In accordance with the control signal (switching signal) from the correction control circuit 15, the temperature conversion circuit 82 shown in FIG.
It is designed to change the gain of.

This will be described with reference to FIG.

FIG. 21A shows the output from the sampling circuit 3 shown in FIG. 1. The hatched protruding portion p22 shown in FIG. 21A has a level proportional to the storage time for photoelectric conversion. It represents the output of a defective pixel having the property of becoming large.

Here, the waveform shown in FIG. 21A is changed to that shown in FIG. 21B.
The output due to the defective pixel can be canceled by performing the defective pixel correction by adding the waveform shown in FIG. However, as shown by the broken line in FIG. 21A, when a peculiar level output p23 suddenly appears (a peculiar level at which a normal pixel is determined to be a defective pixel is suddenly output).
If, for example, the above-described charge storage time is set longer than usual when correcting the output of the defective pixel (e.g., doubled), the output of each defective pixel shown in FIG. The levels of p22 and p23 are shown in Fig. 2.
As shown in 1C, the level is doubled.

When the output of the defective pixel is corrected with the waveform shown in FIG. 21B, as shown in FIG. 21D, the normal output of the defective pixel has been canceled by the correction shown in FIG. 21A. Output of defective pixel p22
Up to the output, and these are detected as defective pixels.

Therefore, in this example, the correction control circuit 15
19 is turned off by the control signal from FIG. 19 to increase the gain of the temperature conversion circuit 82, thereby doubling the reference voltage of the DA converter 87, thereby causing a defect from the system controller 90. The output level of the pixel is doubled as shown in FIG. 21E.

By doing this, as shown in FIG. 21F, only the portion corresponding to the output p23 of the new defective pixel remains,
It becomes possible to correct this. Therefore, it is possible to appropriately detect the output of the defective pixel that has suddenly occurred, and to perform an appropriate correction process on the detected defective pixel, which allows good detection of the defective pixel and its correction. it can. Moreover, the output of the defective pixel that is not the detection target is not erroneously detected.

Next, the pre-detection processing circuit 21 shown in FIG. 1 will be described with reference to FIG.

In FIG. 22, reference numeral 100 denotes a signal (adding circuit 9, 1 from the movable contact 20e of the switch 20 of FIG. 1).
0 or 11, or an input terminal to which temperature information from the temperature sensor 7) is supplied, and a signal supplied via the input terminal 100 is supplied to the amplifier circuit 102 and the delay element 101 via the resistor R4. It

The main purpose of this detection preprocessing circuit 21 is to reduce the detection error due to the sampling frequency component. Therefore, the resistor R4 and the delay element 101 described above remove the carrier component in the input signal that is the object of erroneous detection, and the input signal from which this carrier component is removed is amplified by the amplifier circuit 102 having a gain of, for example, several tens of times. Then, the amplified input signal is converted into a digital signal by the A / D converter 103, and the digital signal obtained by this conversion is supplied to the detection circuit 22 shown in FIG. When the detection preprocessing circuit 21 is used, for example, the detection target level of several mV is 100 mVp.
Even if it is added to the carrier component of −p, the detection target level of several mV can be supplied to the detection circuit 15.
A method of amplifying and detecting the discontinuous portion is also conceivable. However, in this case, the carrier component is also amplified, so that the output voltage range of the amplifier circuit is exceeded.

Next, the operation of the pre-detection processing circuit 21 will be described with reference to FIG.

A signal to the detection preprocessing circuit 21 via the input terminal 100 of FIG. 22 is a signal having a protruding portion p30 (for example, due to the output signal of the defective pixel) indicated by hatching in a part of the signal as shown in FIG. 23A. 22 is input, if the delay element 101 shown in FIG. 22 is impedance-matched, the signal passed through the resistor R4 is
As shown in FIG. 23B, the projecting portion p30 in the waveform of FIG. 23A becomes the projecting portion p31 indicated by diagonal lines.

When the signal shown in FIG. 23 is delayed by the delay element 101 shown in FIG. 22, the phase is inverted by 180 degrees at the point indicated by the arrow dl in FIG. 22, and the reflected waveform is as shown in FIG. 23C. 23B, the phase of the protruding portion p31 in the waveform of FIG. 23B is inverted (the other portions are also the same), and is further delayed by the time of one cycle.

Therefore, the signal supplied to the amplifier circuit 102 shown in FIG. 22 is a waveform obtained by adding the waveform shown in FIG. 23B and the waveform shown in FIG. 23C, that is, as shown in FIG.
3A shows a waveform in which only the projecting portion p30 indicated by hatching is taken out. The waveform shown in FIG. 23D is applied to the amplifier circuit 102 shown in FIG. 22 as a voltage having a level exceeding the threshold level Th for determining a defective pixel in the detection circuit 22 as shown in FIG. 23E, This is converted into a digital signal by the A-D converter 103 and then supplied to the detection circuit 22 described later.

Therefore, it is possible to accurately extract only the output from the defective pixel, which allows good defect detection and correction of the good defective pixel output. Note that the temperature information from the temperature sensor 7 is provided separately in A
Alternatively, the signal may be converted into a digital signal by the -D converter and directly supplied to each unit.

Next, the detection circuit 22 shown in FIG. 1 will be described with reference to FIG.

In FIG. 24, reference numeral 110 denotes an input terminal to which the digital signal subjected to the pre-detection processing from the detection pre-processing circuit 21 shown in FIG. 1 is supplied, and the digital signal from the input terminal 110 is added to the addition circuit 112 and the subtraction circuit. Circuit 111
Are supplied to each.

The adder circuit 112 adds the input signal supplied via the input terminal 110 and the signal fed back, and supplies the added output to the flip-flop circuit 114 via the time constant circuit 113. The flip-flop circuit 114 supplies the output signal from the time constant circuit 113 to the subtraction circuit 111 based on the output signal from the comparator 116 described later, and feeds it back to the addition circuit 112 as described above. The addition circuit 112, the time constant circuit 113, and the flip-flop circuit 114 form a low-pass filter. Therefore, the signal output from the flip-flop circuit 114 becomes a signal of the average level of DC neighboring pixels in which so-called whiskers and noise components of the original signal are removed.

The output from the flip-flop circuit 114 is supplied to the subtraction circuit 111, and the subtraction circuit 111 is supplied.
At, the output signal of the flip-flop circuit 114 is subtracted from the input signal supplied through the input terminal 110, that is, the signal which may be the output from the defective pixel. The signal obtained by this subtraction is supplied to the absolute value circuit 115. The absolute value circuit 115 obtains the absolute value of the signal from the subtraction circuit 111. That is, the levels of the white spots (white spots) produced by the output of the defective pixel and the black spots (black spots) produced by the output of the defective pixel are set to the same polarity, and then supplied to the comparator 116 and the signal supplied from the subtraction circuit 111. Determines whether the signal is due to a white defect or a signal due to a black defect, generates a control signal (flag) according to the result of the determination, supplies the control signal to the switch 119, and controls the switching of the switch 119.

One fixed contact 11 of this switch 119
9a is connected to the output terminal of the threshold circuit 117 that outputs the positive threshold signal, the other fixed contact 119b is connected to the output terminal of the threshold circuit 118 that outputs the negative threshold signal, and the movable contact 119c is connected. It is connected to one input terminal of the comparator 116.

The switch 119 generates a threshold level signal from the threshold circuit 117 for generating a threshold level (positive signal) corresponding to a white defect and a threshold level (negative signal) corresponding to a black defect. Threshold circuit 11
8 and the threshold level signal from the comparator 8 selectively according to the control signal from the absolute value circuit 115.
It is a switch for supplying to 16. The threshold circuits 117 and 118 may have a configuration in which the threshold level data stored in the memory is read by the reading circuit and converted into an analog signal by the DA converter, or a circuit configuration that simply generates an analog voltage. It may be a circuit inside the controller 4.

The comparator 116 compares the absolute value signal from the absolute value circuit 115 with the threshold level signal supplied from the threshold circuit 17 or 18 via the switch 119, and the absolute value signal is larger than the threshold level signal. In this case, the output from the corresponding pixel is determined to be the output from the defective pixel, and the control signal is supplied to the flip-flop circuit 114 so that the output from the corresponding defective pixel is not input to the flip-flop circuit 114. This is because if the output of the defective pixel is used to obtain the average level of the neighboring pixels, the average value will be disturbed.

Here, how the low-pass filter (hereinafter, referred to as a filter) composed of the adder circuit 112, the time constant circuit 113 and the flip-flop circuit 114 described above obtains the average value of the neighboring pixels described above. Will be explained.

The output of this filter is the weighted average of the pixels in the front in the horizontal direction. The horizontal address is now k
It is assumed that the pixel is focused on. Assuming that the pixel level at the address k is Pk, the filter output (average level of neighboring pixels) Pkm at time k is (1 / 2Pk-1).
+ (1 / 4Pk-2) + (1 / 8Pk-3) + (1/1
6Pk-4) + ... + ((1/2 nth power) Pk-n
+ ... Therefore, it can be said that it is effectively a weighted average of the front few pixels.

Now, the operation of the above detection circuit 22 will be described.

The digital signal from the pre-detection circuit 21 is added via the input terminal 110 to the addition circuit 112 and the subtraction circuit 11.
1 is supplied. The output from the adder circuit 112 is supplied to the flip-flop circuit 114 via the time constant circuit 113.

On the other hand, when the output of the subtraction circuit 111 is supplied to the absolute value circuit 115, the polarity of the input signal is detected in the absolute value circuit 115, and the signal due to the white defect or the black defect is detected based on the detection result. The control signal based on the determination result is supplied to the switch 119, the input signal is converted into absolute value data, and the conversion data is supplied to the other input terminal of the comparator 120.

On the other hand, the switch 119 has an absolute value circuit 115.
The movable contact 119c is connected to one or the other movable contact 119a or 119b based on the control signal from the. As a result, a positive (for white flaw) or negative (for black flaw) threshold level signal from the threshold circuit 117 or 118 is read, and the read threshold level signal is input to one input terminal of the comparator 116. Is supplied to.

The comparator 116 compares the absolute value data from the absolute value circuit 115 with the threshold level signal supplied from the threshold circuit 117 or 118, and when the absolute value data is larger than the threshold level signal, the defective pixel is detected. 1 is supplied to the system controller 4 shown in FIG. 1 through the output terminal 120 and the control signal is supplied to the flip-flop circuit 114. Do not capture the signal of. This can prevent the disturbance of the average level of neighboring pixels due to the output of the defective pixel.

As described above, the detection circuit 22 determines whether the signal to be detected is due to the black defect due to the negative output of the defective pixel or due to the white defect due to the positive output of the defective pixel, and it is determined as the white defect. If it is, the threshold level signal for white flaws is used to determine whether the output is due to a defective pixel.If it is determined to be black flaw, the threshold level signal for black flaw is used to determine whether the output is due to a defective pixel. Since it is determined whether or not it is possible, erroneous detection due to so-called whiskers, noise, etc. can be prevented, and good detection can be performed.

As described above, in this example, when the selection by the detection mode switch 24 becomes the mode indicating the detection of the defective pixel, the read mode changeover switch 23.
Even if the setting is in the field read mode, it is forcibly switched to the frame read mode. For example, it is installed in a video camera that can select two read modes: field read and frame read. In this case, the frame reading mode with a good vertical resolution is automatically selected when the defective pixel is detected, and thus the accurate defective pixel can be detected.

The above-described embodiment is an example of the present invention, and it goes without saying that various other configurations can be adopted without departing from the gist of the present invention.

[0157]

According to the present invention described above, the peculiarity of each pixel of the solid-state image pickup device by the defect detection means for detecting the information of the defective pixel which outputs the signal of the peculiar level of each pixel of the solid-state image pickup device 2. When the detection mode is selected by the selection unit that selects the detection mode for detecting the information of the defective pixel that outputs a signal of a different level or the normal imaging mode, the defect detection control unit supplies the control signal to the read control unit. Since the read mode from the solid-state image sensor is forcibly set to the second read mode and the defect detection unit is made to detect the information of the defective pixel, for example, the read mode is set to field read and frame read. If it is installed in a video camera that can be selected from two readout modes, a frame with good vertical resolution can be used when defective pixels are detected. Beam reading mode is automatically selected, thereby making it possible to detect the correct defective pixels.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of an automatic defect correction circuit of a solid-state image sensor according to the present invention.

FIG. 2 is a waveform diagram for explaining an embodiment of an automatic defect correction circuit for a solid-state image sensor according to the present invention.

FIG. 3 is an explanatory diagram for explaining an embodiment of an automatic defect correction circuit for a solid-state image sensor according to the present invention.

FIG. 4 is a waveform diagram for explaining an embodiment of an automatic defect correction circuit for a solid-state image sensor according to the present invention.

FIG. 5 is a configuration diagram showing an example of a main part of an embodiment of an automatic defect correction circuit of the solid-state image pickup device of the present invention.

FIG. 6 is a waveform diagram provided for explaining a main part of an embodiment of an automatic defect correction circuit for a solid-state image sensor according to the present invention.

FIG. 7 is a waveform diagram provided for explaining a main part of an embodiment of an automatic defect correction circuit for a solid-state image sensor according to the present invention.

FIG. 8 is a configuration diagram showing another example of a main part of an embodiment of the automatic defect correction circuit of the solid-state image pickup device of the present invention.

FIG. 9 is a configuration diagram showing an example of a main part of an embodiment of an automatic defect correction circuit for a solid-state image sensor according to the present invention.

FIG. 10 is a configuration diagram showing an example of a main part of an embodiment of an automatic defect correction circuit for a solid-state image sensor according to the present invention.

FIG. 11 is an explanatory diagram for explaining an operation of a main part of an embodiment of the automatic defect correction circuit of the solid-state imaging device of the present invention.

FIG. 12 is an explanatory diagram for explaining an operation of a main part of an embodiment of the automatic defect correction circuit of the solid-state image pickup device of the present invention.

FIG. 13 is an explanatory diagram for explaining an operation of a main part of an embodiment of the automatic defect correction circuit of the solid-state image pickup device of the present invention.

FIG. 14 is an explanatory diagram for explaining an operation of a main part of an embodiment of the automatic defect correction circuit of the solid-state imaging device of the present invention.

FIG. 15 is an explanatory diagram for explaining an operation of a main part of an embodiment of the automatic defect correction circuit of the solid-state imaging device of the present invention.

FIG. 16 is an explanatory diagram for explaining an operation of a main part of an embodiment of the automatic defect correction circuit of the solid-state imaging device of the present invention.

FIG. 17 is an explanatory diagram for explaining an operation of a main part of an embodiment of the automatic defect correction circuit of the solid-state imaging device of the present invention.

FIG. 18 is an explanatory diagram for explaining an operation of a main part of an embodiment of the automatic defect correction circuit of the solid-state imaging device of the present invention.

FIG. 19 is a configuration diagram showing an example of a main part of an embodiment of an automatic defect correction circuit for a solid-state image sensor according to the present invention.

FIG. 20 is a waveform diagram provided for explaining a main part of an embodiment of an automatic defect correction circuit for a solid-state image sensor according to the present invention.

FIG. 21 is a waveform diagram provided for explaining a main part of an embodiment of an automatic defect correction circuit for a solid-state image sensor according to the present invention.

FIG. 22 is a configuration diagram showing an example of a main part of an embodiment of an automatic defect correction circuit of the solid-state image pickup device of the present invention.

FIG. 23 is a waveform diagram provided for explaining a main part of an embodiment of an automatic defect correction circuit for a solid-state image sensor according to the present invention.

FIG. 24 is a configuration diagram showing an example of a main part of an embodiment of an automatic defect correction circuit for a solid-state image sensor according to the present invention.

FIG. 25 is an explanatory diagram showing the principle of field reading.

FIG. 26 is an explanatory diagram showing the principle of frame reading.

[Explanation of symbols]

 1 Optical System 2 CCD 3 Sampling Circuit 4 System Controller 5 Timing Generator 6 Horizontal / Vertical Counter 7 Temperature Sensor 8 Pulse Generator 9, 10, 11 Adder Circuit 12 Read / Write Circuit 13 Memory 14 Register 15 Correction Control Circuit 16 Correction Circuit 20 Switch 21 pre-detection processing circuit 22 detection circuit 23 read mode selector switch 24 detection mode switch

Claims (1)

[Claims] 1. A read control means for reading an image pickup signal from a solid-state image pickup device in a field and frame read mode, and information of a defective pixel which outputs a signal of a peculiar level in each pixel of the solid-state image pickup device. Defect detecting means, selecting means for selecting a detection mode or a normal imaging mode for detecting information on a defective pixel that outputs a signal of a unique level among the pixels of the solid-state image sensor by the defect detecting means, When the detection mode is selected by the selection means, a control signal is supplied to the readout control means to control the readout mode from the solid-state image pickup device to be forced into the frame readout mode, and the defect detection means is deficient. Defect detection control means for detecting pixel information, and the defect detected by the defect detection means A solid-state image pickup device comprising: storage means for storing elementary information; and correction means for correcting a signal of a specific level due to the defective pixel based on the information on the defective pixel stored in the storage means. Automatic defect correction circuit.