JP2990927B2 - Defective pixel detection circuit of solid-state image sensor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a defective pixel detecting circuit of a solid-state image sensor which is suitable for a video camera or the like which can detect and correct defective pixels.

[0002]

2. Description of the Related Art For example, in a video camera using a CCD device, an image is obtained by picking up a so-called defective pixel which outputs a signal of a peculiar level in a state where no light is incident, of each pixel of the CCD device. There is a problem that the image quality deteriorates.

Therefore, conventionally, a video camera is equipped with a correction circuit for correcting a signal output from a defective pixel, and before shipping the video camera to a user, which pixel of the CCD element of the video camera is defective. After the pixel is inspected, the information indicating the defective pixel obtained as a result of the inspection is stored in the storage area of the correction circuit of the video camera, or the like. Thus, the signal output from the defective pixel is corrected by the correction circuit.

[0004] As this correction method, a defect correction method such as so-called zero-order interpolation and primary interpolation and a so-called RPN (residual pattern noise) correction method have been put to practical use.

[0005] Of the former correction methods, the zero-order interpolation is a method in which a signal output from a defective pixel is held in a sampling circuit, and a signal output from the defective pixel is replaced with a signal of a previous pixel.

In the former correction method, the primary interpolation obtains an average of a signal output from a pixel immediately before a defective pixel and a signal output from a pixel next to the defective pixel, and obtains an average from a defective pixel. This is a method of replacing the output signal with an average signal.

In the latter method, that is, RPN (residual pattern noise) correction, a signal corresponding to a signal output from a defective pixel is generated inside the video camera, and this signal is generated from a signal output from the defective pixel. This is a method of subtracting a signal to cancel a signal output from a defective pixel.

By the way, not only the pixels constituting the CCD element become defective at the manufacturing stage but also suddenly become defective even after actually reaching the hands of the user. In a state where light is not incident, a signal having a peculiar level, that is, a defect state in which residual pattern noise is generated may occur.

Therefore, the CC used for the video camera is
If the defective pixel of the D element is inspected to obtain information such as the address data of the defective pixel, and this information is stored in the memory or the like of the video camera and then passed to the user's hand, the above-described sudden defect may occur. It is not possible to cope with the generation of pixels or the generation of defective pixels due to aging.

Therefore, recently, a circuit for detecting a defective pixel is further mounted inside the video camera, the defective pixel is detected by the circuit for detecting the defective pixel, and information of the defective pixel obtained by the detection is transferred to the video camera. A method of correcting a defective pixel newly generated by, for example, the above-described RPN correction circuit mounted on the video camera based on this information has been proposed.

The detection of a defective pixel is performed, for example, as follows. That is, when no light is incident on the CCD element, the level of the signal output from each pixel of the CCD element is compared with the level of the signal output from the pixel immediately before this pixel, or The level of the signal output from the pixel is compared with a predetermined threshold level.
When the level of the signal output by the previous pixel or the level of the signal output by the current pixel is higher than the threshold level, the pixel is detected as a pixel (defective pixel) that outputs a signal of a peculiar level, and this pixel is detected. This is performed by obtaining address data and flaw (defective pixel) data based on the signal level output by the pixel, and storing them in a memory or the like.

On the other hand, after the defective pixel is detected as described above, based on the address data of the defective pixel stored in the memory, the signal corresponding to the defective pixel of the video signal supplied from the CCD element is read from the memory. By subtracting the Blemish data corresponding to the read address data of the defective pixel, a signal of a specific level due to the defective pixel is corrected.

[0013]

By the way, the processing of the data of the defective pixel obtained by the above-described detection of the defective pixel includes a case where all the information on the previous defective pixel is deleted and the new defective pixel is detected again, and a case where the previous defective pixel is detected again. It is conceivable that the defective pixel is corrected based on the pixel information, the defective pixel is detected, and various kinds of information of the pixel newly detected as the defective pixel are added to the information of the previously detected defective pixel.

Incidentally, a defective pixel has a positive temperature characteristic, and the higher the temperature, the higher the absolute value of the level of the signal output from the defective pixel. Therefore, the former method has the advantage that erroneous data obtained by erroneous detection is deleted, so that erroneous data does not remain. However, since the level of the signal output from the defective pixel is low, a problem arises in that a defective pixel that is problematic at a high temperature is not detected.

On the other hand, the latter method does not delete the data of the defective pixel. Therefore, even if the detection of the defective pixel may be failed at a low temperature, the data obtained at the previous high temperature may not be deleted. Therefore, the information of the pixel which is originally defective is held in the register 14, and there is an advantage that the defective pixel can be corrected even when it is detected at a low temperature, but it is obtained by an accidental erroneous detection or the like. Unnecessary data is kept in registers forever without being erased,
There is a disadvantage that unnecessary correction processing is performed.

The present invention has been made in view of such a point. When the temperature is high, the information of the defective pixel detected last time can be erased by deleting the information on the accidentally erroneously detected data. By adding the information of the defective pixel to be detected this time to the information of the detected defective pixel, it is possible to prevent an accident that the defective pixel is not detected at a low temperature, thereby effectively using a memory having a limited capacity, reliably, and An object of the present invention is to propose a defective pixel detection circuit of a solid-state imaging device that can detect a defective pixel with high accuracy and correct a defective pixel.

[0017]

According to the present invention, a defective pixel detecting circuit of a solid-state image sensing device is provided, for example, as shown in FIGS. 1 to 24, based on an output signal of the solid-state image sensing device. Defective pixel detecting means 4, 20, 21, 22 for detecting a defective pixel outputting a signal of a peculiar level, and address data representing at least the position of the defective pixel detected by the defective pixel detecting means 4, 20, 21, 22 , A temperature sensor 7 for detecting the temperature of the solid-state imaging device 2, and a detection level of the temperature information obtained by the temperature sensor 7 when a new defective pixel detection operation is performed.
A mode in which the data of the defective pixel stored in the storage unit 14 is invalidated according to the comparison result with the fixed value, and only the data of the newly generated and detected defective pixel is stored in the storage unit 14, and a mode stored in the storage unit 14. And control means 4 for holding selectively the data of the defective pixel and selectively switching between a mode in which the data of the newly generated and detected defective pixel is added to the storage means 14 and stored.

The defective pixel detecting circuit of the solid-state imaging device according to the present invention, based on the output signal of the solid-state imaging device 2 as shown in FIGS. Defective pixel detecting means 4, 20, 21, 22 for detecting a defective pixel for outputting a signal, and a small number of defective pixels detected by the defective pixel detecting means 4, 20, 21, 22;
A storage means 14 for storing at least address data representing a position, and a temperature sensor 7 for detecting the temperature of the solid-state imaging device 2.
When the temperature sensor 7 detects that the temperature is equal to or lower than a predetermined value when performing a new defective pixel detection operation, the data of the defective pixel stored in the storage unit 14 is held, and And control means 4 for controlling the addition and storage of the data of the generated and detected defective pixels in the storage means 14.

The defective pixel detecting circuit of the solid-state image pickup device according to the present invention, based on the output signal of the solid-state image pickup device 2 as shown in FIGS. Defective pixel detecting means 4, 20, 21, 22 for detecting a defective pixel for outputting a signal, and a small number of defective pixels detected by the defective pixel detecting means 4, 20, 21, 22;
A storage means 14 for storing at least address data representing a position, and a temperature sensor 7 for detecting the temperature of the solid-state imaging device 2.
When the temperature sensor 7 detects that the temperature is equal to or higher than a predetermined value when performing a new defective pixel detection operation, the data of the defective pixel stored in the storage unit 14 is invalidated, and a new And a control means 4 for storing only the data of the defective pixel that has occurred and detected in the storage means 14.

[0020]

According to the present invention described above, when a new defective pixel detection operation is performed, the data of the defective pixel stored in the storage means 14 is invalidated according to the temperature information obtained from the temperature sensor 7 and the new defective pixel is detected. A mode in which only the data of the detected defective pixel is stored in the storage means 14; the data of the defective pixel stored in the storage means 14 is held; and the data of the newly detected defective pixel is added to the storage means 14. For example, when the temperature is high, accidentally erroneously detected data can be erased by deleting the information of the defective pixel detected last time. By adding the information of the defective pixel detected this time to the information of the defective pixel detected last time, it is possible to prevent an accident that the defective pixel is not detected at a low temperature, thereby limiting the capacity. Is the memory can be effectively used to have,
Defective and accurate detection of defective pixels can be performed reliably and good defective pixels can be corrected.

According to the present invention described above, when the temperature sensor 7 detects that the temperature is equal to or lower than a predetermined value when a new defective pixel is detected, the storage means 14 stores the temperature. Since the data of the defective pixel is held and the data of the newly detected defective pixel is added and stored in the storage means 14, the data of the defective pixel previously detected when the temperature is high, for example, can be held, As a result, a sufficient correction can be performed on the defective pixel.

According to the present invention described above, when the temperature sensor 7 detects that the temperature is equal to or higher than a predetermined value when a new defective pixel is detected, the storage means 14 stores the temperature. Since the data of the defective pixel is invalidated and only the data of the newly detected defective pixel is stored in the storage means 14, the data due to the accidental erroneous detection is quickly erased, and the appropriate correction of the defective pixel is performed. It can be carried out.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a defective pixel detecting circuit of a solid-state imaging device according to the present invention will be described below in detail with reference to FIGS.

FIG. 1 is a block diagram showing an example in which a defective pixel detection circuit of the solid-state image pickup device of this embodiment is applied to a video camera. Hereinafter, the solid-state image pickup device of this embodiment is applied to a video camera with reference to FIG. The case will be described.

In FIG. 1, reference numeral 1 denotes an optical system such as a lens and an iris. Light from a subject is supplied to the CCD element 2 via the optical system 1. In the present embodiment, for example, it is assumed that this CCD element 2 is composed of three CCD elements for green, red and blue components. In this case, the optical system 1 includes a prism, and the prism supplies green component light to the CCD element 2 (for green component light) out of the light from the subject, thereby forming a red component. Light is supplied to the CCD element 2 (for red component light), and blue component light is supplied to the CCD element 2 (for blue component light). Note that this CCD element 2
May be, for example, a single plate type or a two plate type.

The green, red, and blue component lights supplied to the CCD element 2 are photoelectrically converted by the CCD elements 2 (three CCD elements), and the charge accumulation time is controlled by a charge accumulation control signal from the timing generator 5. Are controlled and read out by the readout signal from the timing generator 5.

Here, there are a field reading method and a frame reading method for reading signals from the CCD element 2. In this example, for example, when a defective pixel is detected, the signal is forcibly issued by a command from a defective pixel correction system described later. In this case, the mode is switched to the frame accumulation mode.

Since it is very rare that a signal having a peculiar level spans two pixels due to a defective pixel, in frame reading, an output from one defective pixel appears in either an even or odd field. .

On the other hand, in the field reading, the output of one defective pixel appears in both the even and odd fields.

Therefore, when detection is performed by field reading, a memory capacity for two pixels is required for the output of one defective pixel. However, in order to specify a pixel having one specific level of output, a memory capacity for these two pixels is necessary.

In reading out a frame, in order to accurately correct the output of a defective pixel and not to correct the output of a non-defective pixel, it is essential to specify a pixel having an unusual level of output. Condition.

However, the process of specifying this takes a lot of trouble. Particularly, when a defective pixel is detected during the field reading, the charge accumulation in the photo sensor of the CCD element 2 is reduced during the field period. , The charge accumulation time in the field readout is 2
Compared with the frame reading in which the charge accumulation time is twice as long, the signal level output by the defective pixel is half of the signal level output by the defective pixel in the case of the frame reading,
The S / N of the detection in the case where the defective pixel is detected by performing the field reading is significantly lower than the S / N of the detection in the case where the defective pixel is detected by performing the frame reading.

Therefore, in this embodiment, in the mode of detecting a defective pixel, the reading mode from the CCD element 2 is forcibly set to the frame reading mode. Therefore, the S / N of detection is improved by 6 dB as compared with the case where the field readout is performed and the defective pixel is detected, and highly accurate and good defective pixel detection can be performed. The required memory capacity can be reduced to half of the case where the field readout is performed and the defective pixel is detected.

The output from the CCD element 2 is supplied to a sampling circuit 3, where the CCD element 2 receives a signal from a timing generator 5 and a pulse generator 8 as shown in FIG.
Are sampled at sampling points indicated by P in the figure to remove reset noise and the like, and the sampled signals, that is, signals corresponding to green, red and blue, are added to adders 9, 10 and 11 Supply each.

The addition circuits 9, 10 and 11 add the correction signals corresponding to green, red and blue from the correction circuit 16 described later to the signals corresponding to green, red and blue from the sampling circuit 3, respectively. The addition signals corresponding to green, red, and blue are supplied to other video signal processing circuits and the like of a video camera (not shown) via output terminals 17, 18, and 19, respectively, and fixed contacts 20a, 20b and 2
0c respectively.

The switch 20 is connected to each of the adder circuits 9,
In addition to fixed contacts 20a, 20b and 20c to which signals corresponding to green, red and blue from 10 and 11 are supplied, a temperature sensor 7 which is attached to the package of the CCD element 2 and detects the temperature of the CCD element 2 Is provided with a fixed contact 20d to which temperature information is supplied.
0e to these fixed contacts 20a, 20b, 20c and 2
By connecting to 0d, signals and temperature information corresponding to green, red and blue are supplied to the detection preprocessing circuit 21.

The detection pre-processing circuit 21 detects a discontinuous minute level of a carrier component of a signal corresponding to green, red and blue from among signals corresponding to green, red and blue or temperature information supplied from the switch 20. After the removal, the signals corresponding to green, red, and blue from which the discontinuous minute level of the carrier component has been removed, and the temperature information are converted into digital signals, and green,
The digital signals corresponding to red and blue are supplied to the detection circuit 22 and the digital temperature data is supplied to the system controller 4.

The detection circuit 22 includes a pre-detection processing circuit 21
The digital signal corresponding to green, red, and blue supplied from is subjected to low-pass filtering and a comparison using threshold levels for so-called white flaws that appear white on the screen and black flaws that appear black on the screen. The result is supplied to the system controller 4.

The system controller 4 compares the result from the detection circuit 22 with a threshold level based on the digital temperature data, and, based on the comparison result, converts a video signal corresponding to the result from the detection circuit 22 into an output signal from a defective pixel. If it is determined, various information related to the defective pixel is stored in the register 14 together with the address signal from the horizontal / vertical counter 6.

After the defect detection is completed (for example, in a defect detection mode), the address data and various information of the defective pixel stored in the register 14 are stored in a memory (for example, an EEPROM or a battery backup) via the read / write circuit 12. Attached RAM 13).

On the other hand, during normal photographing, the memory 1
3 is read, and the address signal is compared with the address signal from the horizontal / vertical counter 6.
And the timing generator 5 is controlled to cause the sampling circuit 3 to hold the signal portion corresponding to the defective pixel.

The system controller 4 performs the correction control circuit 1 when the level of the stored defective pixel is equal to or higher than the stored level during the operation of correcting the defective pixel.
The mask signal is supplied to the correction circuit 16 from step 5, thereby preventing the correction circuit 16 from correcting the output from the defective pixel whose level varies.

Further, the system controller 4 switches the switch sw2 for supplying the shutter enable signal with the detection enable signal based on the setting information from the switch sw1.
, And supplies a detection enable signal to the detection circuit 22 to control the detection of defective pixels by the detection circuit 22. Therefore, for example, the switch sw1
Is operated by the user to set a mode for detecting a defective pixel.
The detection enable signal is supplied to the detection circuit 22 to enter the defective pixel detection mode. At the same time, the switch sw2 is turned off by the detection enable signal, whereby the shutter enable signal is not supplied to the timing generator 5. Therefore, the so-called shutter operation for shortening the charge accumulation time in the CCD element 2 shorter than the normal accumulation time is not performed, so that the deterioration of the S / N of the detection of the defective pixel can be reduced and the defective pixel can be detected satisfactorily. it can.

Here, the above-mentioned defective pixel will be described. As shown in FIG. 3, the defective pixel is a white point (white flaw) W1 which does not depend on the light amount but depends on the temperature, and a white point which depends on both the light amount and the temperature. There are a point (white defect) W2 and a black point (black defect) B1, and a black point (black defect) B2 that does not depend on the light amount but does depend on the temperature. Therefore, in this example, detection and correction of a defective pixel are performed based on the temperature information from the temperature sensor 7 so that these conditions can be satisfied.

Both such minute white points and black points have a form in which a constant bias voltage is added or subtracted from the signal output of the defective pixel. The video signal component normally responds to the amount of incident light. Therefore, the position of the defective pixel and the amplitude of the defective component at a certain temperature are measured and stored in advance, and a correction signal having the same amplitude and the opposite polarity as the defective component is generated at the same timing as the signal output of the defective pixel, thereby obtaining the defective pixel. , The defective component of the video signal can be canceled. This is shown in FIG.

FIG. 4A shows waveforms with the vertical axis representing the amplitude level (V) of the video signal and the horizontal axis representing time (T).
Is a large light output signal out1 and a small light output signal ou
This shows t2. The range shown by the broken line corresponds to the output pulse for one pixel.

As shown in FIG. 4A, in each of the large light quantity output signal out1 and the small light quantity output signal out2, the minute white point pulse W and minute black point pulse B output from the defective pixel are generated. .

A large light output signal out shown in FIG. 4A.
The minute white point pulse W and minute black point pulse B of FIG.
The minute white point correction pulse Wp and the minute black point pulse Bp shown in FIG.
1 (which is output from the correction circuit 16 in FIG. 1), the minute white point corresponding pulse W and the minute black point corresponding pulse B are corrected as shown in FIG. 4C as the large light amount output signal out1. ing.

Further, the minute white point pulse W and minute black point pulse B of the small light amount output signal out2 shown in FIG.
By adding a correction signal (output from the correction circuit 16 in FIG. 1) composed of the minute white point correction pulse Wp and the minute black point pulse Bp shown in FIG. 4B, as shown in FIG. 4C as a small light amount output signal out2, The minute white point corresponding pulse W and the minute black point corresponding pulse B are corrected.

Next, each part of the circuit of this embodiment shown in FIG. 1 will be described in more detail with reference to FIGS.

First, the sampling circuit 3 shown in FIG. 1 will be described with reference to FIGS.

In FIG. 5, reference numeral 30 denotes a correlated double sampling circuit. The correlated double sampling circuit 30 receives a signal (video signal) corresponding to green from the CCD device (green CCD) 2 shown in FIG. The supplied input terminal 31 is connected to the input terminal of the amplifier circuit 32, and the output terminal of the amplifier circuit 32 is connected to the non-inverting input terminal (+) of the operational amplifier circuit 38 via the switch 33. The non-inverting input terminal (+) of the operational amplifier circuit 38 is grounded via a capacitor 37, the output terminal of the operational amplifier circuit 38 is connected to an output terminal 45, and the output terminal of the amplifier circuit 32 is connected to an amplifier circuit 42 via a switch 40. And the input terminal of the amplifier circuit 42 is grounded via the capacitor 41,
The output terminal of the amplifier circuit 42 is connected to the inverting input terminal (-) of the operational amplifier circuit 38 via the switch 43, and the inverting input terminal (-) of the operational amplifier circuit 38 is grounded via the capacitor 44. Composed of

The correlated double sampling circuit 3
The sample / hold signal SHP from the timing generator 5 is supplied to the switch 40 of the "0" through the input terminal 39, and the switch 3 of the correlated double sampling circuit 30
The sample hold signal SHD from the AND circuit 36 is supplied to 3 and 43.

The sample and hold signal SHD supplied to the switches 33 and 43 is obtained by combining the signal supplied to the input terminal 34 of the sampling circuit 3 and the frame signal from the timing generator 5 for the signal corresponding to green in the AND circuit 36. This is a signal obtained by taking a logical product.

Reference numeral 49 denotes a correlated double sampling circuit for a signal corresponding to red.
9 is the same as that of the correlated double sampling circuit 30. An input terminal 46 is connected to the correlated double sampling circuit 49.
A signal corresponding to red is supplied from the CCD element (CCD for red) 2 shown in FIG. 1 through the, and the output of the correlated double sampling circuit 49 is supplied to an output terminal 50. Although not shown, the sample / hold signal SHP from the timing generator 5 is supplied to the switch 40 of the correlated double sampling circuit 49 via the input terminal 39,
The sample and hold signal SH from the AND circuit 48 is supplied to the switches 33 and 43 of the correlated double sampling circuit 49.
Supply D.

Switches 33 and 43 not shown
Is obtained by ANDing the signal supplied to the input terminal 34 of the sampling circuit 3 and the frame signal from the timing generator 5 for the signal corresponding to red in the AND circuit 48. Signal.

Numeral 54 denotes a correlated double sampling circuit for a signal corresponding to blue.
4 is the same as that of the correlated double sampling circuit 30. The input terminal 51 is connected to the correlated double sampling circuit 54.
, A signal corresponding to blue from the CCD element (blue CCD) 2 shown in FIG. 1 is supplied, and the output of the correlated double sampling circuit 54 is supplied to an output terminal 55. Although not shown, the sample / hold signal SHP from the timing generator 5 is supplied to the switch 40 of the correlated double sampling circuit 54 via the input terminal 39, and the switch 33 of the correlated double sampling circuit 54 is supplied.
And 43 are supplied with a sample hold signal SHD from the AND circuit 53.

Switches 33 and 43 not shown
Is obtained by ANDing the signal supplied to the input terminal 34 of the sampling circuit 3 and the frame signal from the timing generator 5 for the signal corresponding to blue in the AND circuit 53. Signal.

A signal shown in FIG. 6A is supplied to each of the AND circuits 36, 48, and 53. In addition to this signal, the AND circuit 36 has a signal (G) corresponding to green as shown in FIG.
The frame signal from the timing generator 5 which becomes active for one frame per three frames (ch) is supplied, the logical product of these two signals is obtained, and the sample hold signal SHD as shown in FIG. 6E is generated.

Similarly, in addition to the signal shown in FIG. 6A, the AND circuit 48 receives a signal from the timing generator 5 which becomes active for one frame per three frames (Rch) for a signal corresponding to red as shown in FIG. 6C. A frame signal is supplied, the logical product of these two signals is taken, and FIG.
A sample hold signal SHD as shown in F is generated.

Similarly, in the AND circuit 53, FIG.
6D, a frame signal from the timing generator 5 which is active for one frame for every three frames (Bch) for a signal corresponding to blue as shown in FIG. 6D is supplied, and the logical product of these two signals is supplied. Is taken,
A sample hold signal SHD as shown in FIG. 2G is generated.

Next, the operation of the sampling circuit 3 shown in FIG. 5 will be described with reference to FIG.

As shown in FIG. 7A, the signals (G, R, Bch signals) supplied from the CCD element 2 to the sampling circuit 3 shown in FIG. 5 have the precharge levels shown in FIG. The signal is sampled and held by the signal SHP (the signal from the timing generator 5 supplied to the input terminal 39 in FIG. 5), and the data level of the signal shown in FIG. 7A is changed to the sample hold signal SHD shown in FIG. , 4
8 and 53, which are sampled and held by FIG. 6E, corresponding to FIGS. 6E, F and G respectively.

If the data level is at an abnormal level pa as shown in FIG. 7A, the abnormal level pa is also output in the normal operation as shown in FIG. 7D. Therefore, as shown in FIG. 7E, a signal corresponding to the abnormal level pa is not output from the sampling signal SHD shown in FIG. 7C using a signal indicating the position of the abnormal level pa (FIG. 7F). . Thus, as shown in FIG. 7G, the abnormal level p of the output signal
The signal corresponding to “a” remains the output signal of the immediately preceding pixel, that is, is held. Therefore, the output from the output terminals 45, 50, and 55 of the correlated double sampling circuits 30, 49, and 54 connected to the operational amplifier circuit 38 shown in FIG. 5 has the abnormal level pa removed as shown in FIG. 7G. Output.

As shown in FIG. 5, the operational amplifier 3
8 is supplied with a signal obtained by sampling the data level of each pixel, and a signal obtained by sampling the data level of each pixel is supplied to the inverted input terminal (-) of the operational amplifier circuit 38. Therefore, the data potential of each pixel and the reset potential of each pixel are sampled and held, and the difference between them is obtained in the operational amplifier circuit 38, and this is output.

Therefore, reset noise and the like which are in-phase components between the reset potential and the data potential can be removed.

As described above, in the sampling circuit 3, as shown in FIG. 6, a signal corresponding to green, a signal corresponding to red, and a signal corresponding to blue from the CCD element 2, that is, Gch (channel) ), Rch (channel) and Bch (channel) when sampling, respectively, during sampling of Gch, Rch
And sampling of Bch are stopped, sampling of Gch and Bch is stopped during sampling of Rch,
Since sampling of Gch and Rch is stopped during sampling of Bch, it is possible to prevent deterioration of image quality due to so-called data jumping from a channel other than the channel being sampled.

FIG. 8 is a block diagram showing another example of the sampling circuit 3 described above. As shown in FIG. 8, in this example, the CCD element (R) 2R, the CCD element (G) 2
G and the output from the CCD element (B) 2B are supplied to the sampling circuit 1 via switches 130, 131 and 132, respectively.
33, and outputs the output from an output terminal 135. The switches 130, 131, and 132 are sequentially turned on, for example, for each frame by a control signal from a control circuit 134 provided separately.

When the control signal output from the control circuit 134 is, for example, a signal as shown in FIGS. 6B, 6C and 6D, a frame signal which is active for one frame in three frames shown in FIG. The switch 131 is turned on while the frame signal is active, so that the output from the CCD element 2G is output via the switch 131 to the sampling circuit 133.
And sampled. Next, a frame signal that is active for one frame in three frames shown in FIG. 6C is supplied to the switch 130, and the switch 130 is turned on while the frame signal is active,
As a result, the output from the CCD element 2R is switched to the switch 13
The signal is supplied to the sampling circuit 133 via 0 and is sampled. Next, a frame signal that is active for one frame in three frames shown in FIG. 6D is supplied to the switch 132, and the switch 132 is turned on while the frame signal is active, thereby the CCD is turned on.
The output from the element 2B is supplied to the sampling circuit 133 via the switch 132 and is sampled.

Therefore, also in this case, like the sampling circuit 3 described with reference to FIG.
, A signal corresponding to red from the CCD element 2R and a signal corresponding to blue from the CCD element 2B, that is, the output of Gch (channel), Rch (channel) and Bch (channel). When sampling each, the Rch during the sampling of Gch
And Bch signals are not supplied to the sampling circuit 133, so that no sampling is performed. During the sampling of Rch, the signals of Gch and Bch are
33, no sampling is performed and Bc
Since the Gch and Rch signals are not supplied to the sampling circuit 133 during the sampling of h, no sampling is performed, thereby preventing the deterioration of the image quality due to the so-called data jump from a channel other than the channel being sampled. it can.

Next, the system controller 4 shown in FIG. 1 will be described with reference to FIG.

As shown in FIG. 9, the system controller 4 shown in FIG.
A comparison circuit 60 is provided in addition to the original circuit (not shown). That is, the output signal (comparison result signal) from the detection circuit 22 shown in FIG. 1 is supplied to the comparator 62 via the input terminal 61, and the digital temperature data from the detection pre-processing circuit 21 shown in FIG. The signal is supplied to a multiplication circuit 65 through an input terminal 63 and a threshold circuit 64
Is supplied to the multiplication circuit 65. In the multiplying circuit 65, the temperature sensor (see FIG. 1) thermally coupled to the CCD element 2 detects the threshold data from the threshold circuit 64, and the detection pre-processing circuit 21 digitally detects this. Modulation is performed using the converted digital temperature data.
Further, the modulated threshold data and the signal supplied from the detection circuit 22 are compared with the comparator 62.
Are compared by the comparator 62, and the comparison result is supplied to another circuit (not shown) of the system controller 4 via the output terminal 66.

With this arrangement, the threshold data for judging that the output is the output of the defective pixel has a positive temperature characteristic with respect to the output of the defective pixel having the positive temperature characteristic. The detection performance for the signal output by the defective pixel can be kept constant;
This greatly reduces the dependence of the detection performance of the automatic defective pixel detection system on temperature, and prevents accidents, such as erroneous detection of minute defective pixels that are unnecessary in the application. Thus, good defective pixels can be detected. In addition, even when noise is applied to a signal having a level lower than the threshold level for various reasons such as jitter, the threshold level is raised as a result and the sensitivity is reduced, so that erroneous detection can be prevented.

Next, the internal configuration and operation of the register 14 shown in FIG. 1 will be described with reference to FIGS.

In FIG. 10, 70r, 70r +
.., 70r + n are main registers, respectively. These main registers 70r, 70r + 1,.
+ N is an area for storing a horizontal address, an area for storing a vertical address, an area for storing a field flag indicating a number field, and channel information (Rc
h, Gch and Bch information), and an area for storing time history data. The information stored in each of these areas is information corresponding to a defective pixel.

The time history here is the number of times a certain pixel is not detected as a defect. In this example, if a certain pixel is not detected as a defect ten times, for example, this pixel is not regarded as a defective pixel. . This is because a certain pixel may or may not output a signal of a peculiar level (level as a defect) for each field, for each frame, or irregularly. In such a case, even if it is desired to correct such a pixel as a defective pixel, a problem arises in that when a signal is detected when a signal having a peculiar level is not output, the pixel is not detected as a defective pixel, and correction processing cannot be performed. It is. In the present embodiment, a pixel that outputs a signal of a peculiar level irregularly can be corrected as a defective pixel. Further, in this way, noise suddenly mixed in the video signal is not erroneously detected as a defective pixel.

The main registers 70r, 70r + 1,
... The information stored in 70r + n is information of a pixel determined to be defective at the present time before starting detection of a defective pixel, that is, at the current time.

72r, 72r + 1,... 72r + n
Are sub-registers, respectively.
2r + 1,..., 72r + n are an area for storing a horizontal address, an area for storing a vertical address, an area for storing a field flag indicating a number field, and channel information (Rch, Gch, and Bch information).
And an area in which time history data is stored. The information stored in each of these areas is information corresponding to the defective pixel.
The above-mentioned main registers 70r, 70r + 1,..., 7
The information of the defective pixel determined to be defective at this time stored in 0r + n is stored in sub-registers 72r, 72r + 1,
72r + 2,... 72r + n.

71c, 71c + 1,... 71c + n
Are the comparators, and the sub-registers 72r, 72r + 1,...
n from defective pixel information and main registers 70r, 70r
+1... 70r + n,
For example, the detection result is notified to the system controller 4.

Next, referring to FIG. 11 to FIG.
The operation of the register 14 shown in FIG.

FIG. 11 shows the main register 70r, 70r + 1, and 70r information of the pixel determined to be defective at the present time.
+2,... 70r + n. The address area of the main register 70r stores the address data of the defective pixel at the address “x” (the horizontal / vertical address in FIG. 10), and the time history data “8” is stored in the time history area. Also, the main register 70r
The address data of the defective pixel having the address “y” (the horizontal / vertical address in FIG. 10) is stored in the +1 address area, and the time history data “3” is stored in the time history area. The address area of the main register 70r + 2 stores the address data of the defective pixel at the address "z" (the horizontal / vertical address in FIG. 10), and the time history area stores the time history data "0".

Note that, for convenience of explanation, the description of the other information shown in FIG. 10 will be omitted.

First, before detection, the main registers 70r and 70r are controlled by a control signal from the system controller 4.
0r + 1, 70r + 2, 70r + 3,... 70r +
n as shown in FIG.
r, 72r + 1, 72r + 2, 72r + 3,..., 7
2r + n, and then the main registers 70r, 7
0r + 1, 70r + 2, 70r + 3,... 70r +
Clear each area of n.

In each of FIGS. 11 to 18, "not yet" indicates a cleared state in which pixel information is not stored.

Now, the main registers 70r, 70r +
After clearing 1, 70r + 2, 70r + 3,..., 70r + n, a defective pixel is detected under the control of the system controller 4, and information of the pixel determined to be defective is stored in the main registers 70r, 70r + 1, 70r + 2, 70.
r + 3,... 70r + n. FIG. 13 shows an example in this case. As shown in FIG. 13, the address area of the main register 70r has the address “x”.
The address data of the defective pixel is stored in the time history area. For example, time history data "10" is stored in the time history area since the first detection operation is performed. The main register 70
The address data of the defective pixel having the address “v” is stored in the address area of r + 1, and the time history area is detected by the first detection operation.
0 "is stored. Although not shown, information other than the address data and the time history data of these defective pixels is also stored.

Next, as indicated by the hatched signal lines in FIG.
The information of the read defective pixels is read by the comparators 71c, 71c + 1, 71c + 2, 71
.., 71c + n, and these comparators 71c, 71c + 1, 71c + 2, 71+
, 71c + n, the main register 70
r, 70r + 1, 70r + 2, 70r + 3,..., 7
It is sequentially compared with the information of the defective pixel read from 0r + n. As a minimum condition for the matching, it is necessary that the channel data and the address data match.

In the example of FIG. 14, the sub register 72r
Of the defective pixel information stored in the main register 70r matches the address data of the defective pixel information stored in the main register 70r. A signal corresponding to the detection result is transmitted to, for example, the system controller 4.
To supply.

Next, as indicated by the hatched signal lines in FIG. 15, the contents of the sub-register 72r + 1 are read by the data selector 73, and the read information of the defective pixels is read by the comparators 71c, 71c + 1, 71c + 2,
., 71c + n, and these comparators 71c, 71c + 1, 71c + 2, 71+
, 71c + n, the main register 70
r, 70r + 1, 70r + 2, 70r + 3,..., 7
It is sequentially compared with the information of the defective pixel read from 0r + n.

In the example of FIG. 15, the sub register 72r
The address data of the information of the defective pixel stored in +1 (the same applies to the channel data, not shown) is stored in the main registers 70r, 70r + 1, 70r + 2, 70r +.
,..., 70r + n, none of the address data of the information of the defective pixel (the same applies to the channel data, not shown), and therefore the comparators 71c, 71c + 1, 71c + 2, 71c + 3,
... None of 71c + n react. At this time, the time history data stored in the time history area of the sub-register 72r + 1 is "3" and has not yet been set to "0". Therefore, for example, the system controller 4 is stored in the sub-register 72r + 1. The information of the defective pixel is not erased, and "1" is subtracted from the historical data "3" stored in the sub register 72r + 1 to make the historical data "2".
Of the defective pixel (only the time history data is set to "2") stored in the unused main register 70r +
2, 70r + 3,... 70r + n. In this case, as shown by the hatched signal line in FIG. 16, the data is stored in the unused main register 70r + 2.

Next, as indicated by the hatched signal lines in FIG. 17, the contents of the sub-register 72r + 2 are read out by the data selector 73, and the read information on the defective pixels is read by the comparators 71c, 71c + 1, 71c + 2,
., 71c + n, and these comparators 71c, 71c + 1, 71c + 2, 71+
, 71c + n, the main register 70
r, 70r + 1, 70r + 2, 70r + 3,..., 7
It is sequentially compared with the information of the defective pixel read from 0r + n.

In the example of FIG. 17, the sub register 72r
The address data of the information of the defective pixel stored in +2 (the same applies to the channel data, not shown) is stored in the main registers 70r, 70r + 1, 70r + 2, 70r +.
,..., 70r + n, none of the address data of the information of the defective pixel (the same applies to the channel data, not shown), and therefore the comparators 71c, 71c + 1, 71c + 2, 71c + 3,
... None of 71c + n react. At this time, since the time history data stored in the time history area of the sub register 72r + 2 is "0", for example, the system controller 4 stores the information of the defective pixel stored in the sub register 72r + 2 in the main register. 70r,
70r + 1, 70r + 2, 70r + 3,... 70r
+ N is not stored. Therefore, in this case, immediately before the start of the detection of the next defective pixel, information on the defective pixel stored in the main register 70r + 2 is stored and corresponds to the address data “z” stored in the sub register 72r + 2. Only the information of the defective pixel to be erased is erased.

After such processing is completed, the process shown in FIG.
As shown in the figure, the time history data is "10" in the main register 70r and the information of the defective pixel corresponding to the address "x" is stored. The time history data is "10" in the main register 70r + 1 and the address " The information of the defective pixel corresponding to the address "y" is stored in the main register 70r + 2, and the information of the defective pixel corresponding to the address "y" is stored in the main register 70r + 2. Is "8", the information of the defective pixel corresponding to the address "x" is stored, the time history data is "3", and the information of the defective pixel corresponding to the address "y" is stored in the subregister 72r + 1. The time history data is “0” in the sub register 72r + 2, and information on the defective pixel corresponding to the address “z” is stored. As will be described later, when the temperature is low at the time of the next detection, only the information of the defective pixel stored in the sub-register 72r + 2 is thus cleared, and the other sub-registers 72r, 72r + 1, 72r + 3,. 72
The information of the defective pixel stored in r + n may be held.

As described above, for example, if a pixel once determined to be defective at the time of detection is not determined to be defective, for example, 10 times consecutively during the detection period or for each detection, the corresponding pixel is not determined as a defective pixel. Therefore, it is possible to determine a pixel that outputs a signal of a peculiar level irregularly due to, for example, the influence of temperature as described above as a defective pixel, perform correction processing on the defective pixel, and mix sudden noise. Is not mistakenly determined to be a defective pixel with respect to a signal having a peculiar level, and therefore, a pixel of a channel and an address corresponding to a portion where the signal is carried is not erroneously corrected, and In addition, highly accurate detection of a defective pixel and correction of the defective pixel can be performed.

In the above example, a case has been described in which, when the time history data of a pixel once determined to be a defective pixel becomes "0", the pixel is not determined to be a defective pixel. The time history data is set to "0", and "1" is added each time the time history data is not determined to be defective. When the time history data becomes "10", the pixel having the time history data is determined to be not a defective pixel. You may do it.

Next, a case will be described in which the contents of the register 14 of FIG. 1 described with reference to FIGS. 11 to 18 are processed in accordance with the temperature.

The register 14 shown in FIG. 1 stores various kinds of information on defective pixels obtained as a result of the defective pixel detection processing. In the present example, in performing the detection, two methods can be selectively used for handling various kinds of information on the defective pixel obtained by the detection before the current detection.

One method is to delete all the information on the previous defective pixel and detect it again. The other is to correct the defective pixel based on the information on the previous defective pixel, detect the defective pixel, and newly detect the defective pixel. In this method, various information of a pixel detected as a defective pixel is added to information of a previously detected defective pixel.

Incidentally, a defective pixel has a positive temperature characteristic, and the higher the temperature is, the higher the absolute value of the level of the signal output from the defective pixel is. Therefore, the former method has the advantage that erroneous data obtained by erroneous detection is deleted, so that erroneous data does not remain. Since the level of the signal output from the defective pixel is low, there is a possibility that a defective pixel which may cause a problem at a high temperature may not be detected.

On the other hand, the latter method does not delete the data of the defective pixel. Therefore, even if the detection of the defective pixel may fail at a low temperature, the data obtained at the previous high temperature is not deleted. Therefore, the information of the pixel which is originally defective is held in the register 14, and there is an advantage that the defective pixel can be corrected even when it is detected at a low temperature, but it is obtained by an accidental erroneous detection or the like. Unnecessary data is kept in registers forever without being erased,
Unnecessary correction processing is performed.

In this embodiment, the system controller 4 selects each of the above two methods based on the temperature information from the temperature sensor 7 shown in FIG. I do. That is, when the temperature is low, a method of adding the information of the defective pixel obtained by the current detection to the previous detection data is adopted, and when the temperature is high, the previous detection data is deleted.

In this way, when the temperature is high,
By deleting the previously detected defective pixel information, accidentally erroneously detected data can be deleted.When the temperature is low, the defective pixel information detected this time is added to the information of the previously detected defective pixel to detect the defective pixel at low temperature. An accident that a pixel is not detected can be prevented, so that a memory having a limited capacity can be used effectively, and a defective pixel can be reliably and accurately detected, and a good defective pixel can be corrected.

It should be noted that the method of managing the time history of the register 14 described with reference to FIGS. 10 to 18 and the method of deleting or adding the information of the previously detected defective pixel according to the temperature are used in combination. Is also good.

Next, the correction control circuit 15 shown in FIG. 1 will be described. In the present example, the correction control circuit 15 shown in FIG. 1 supplies a control signal to the timing generator 5 via the system controller 4 based on the temperature data from the temperature sensor 7 to store the charge accumulation time in the CCD element 2. In the range from the normal accumulation time to the accumulation time longer than the normal accumulation time.

If the charge accumulation time in the CCD element 2 is made longer than the normal accumulation time, the number of frames of the output image decreases, but the amplitude of the output signal increases under the same light amount. This is the S / N of the detection
It is an improvement factor. In particular, since the S / N of the output of the CCD element 2 tends to deteriorate at low temperatures compared to that at high temperatures,
Making the charge storage time longer than usual is very effective.

Therefore, in this example, the correction control circuit 1
5 is supplied from the temperature sensor 7 via the system controller 4 (note that the temperature sensor 7 or the detection preprocessing circuit 2
The temperature data is detected. When the temperature is low, a control signal is supplied to the timing generator 5 via the system controller 4 in accordance with the detected temperature data, and The charge accumulation time is made longer than usual, and if the temperature is high, it is kept as usual.

Thus, the S / N of the output does not deteriorate even if the CCD image pickup device 2 is used at a low temperature and the CCD device 2 is at a low temperature immediately after the power is turned on. Accuracy can be improved and good defective pixel detection can be performed, and detection can be performed under wider temperature conditions (outside air temperature, temperature of the CCD element 2 itself).

The correction control circuit 15 compares the temperature data supplied from the temperature sensor 7 via the system controller 4 with the reference temperature data, and when the supplied temperature data is lower than the reference temperature data, the correction circuit 16 The control signal supplied to the correction circuit 16 is set to a high level "1" when the temperature data supplied is higher than the reference temperature data.

As will be described later, when this control signal is at low level "0", that is, when the temperature of the CCD element 2 is low, the gain of the amplifier circuit of the correction circuit 16 is varied. Thereby, the level of the correction signal supplied from the correction circuit 16 to each of the addition circuits 9, 10 and 11 can be varied.

The correction control circuit 15 supplies a mask signal (enable signal of the analog switch 88) to an analog switch 88 (see FIG. 19) of the correction circuit 16 described later, and outputs a signal output from the defective pixel due to a rise in temperature. When the level becomes a level that the correction circuit 16 cannot completely correct, the correction for the defective pixel is not performed.

Next, the correction circuit 16 will be described with reference to FIG.

In FIG. 19, reference numeral 84 denotes an input terminal to which a control signal from the correction control circuit 15 shown in FIG. 1 is supplied, and on / off of the switch 85 is controlled by the control signal supplied to the input terminal 84. I do. Reference numeral 80 denotes an input terminal to which temperature information from the temperature sensor 7 is supplied. The input terminal 80 is connected to an input terminal of a temperature characteristic circuit 81.
The temperature characteristic circuit 81 converts the temperature data supplied through the input terminal 80 so as to match the minute white point (the output of the positive electrode among the outputs of the defective pixels), and converts the output obtained by this conversion into the temperature. It is supplied to the conversion circuit 82.

This temperature conversion circuit 82 is provided with a temperature characteristic circuit 8
1 is connected to the inverting input terminal (-) of the operational amplifier circuit 83 via the resistor R1, and the output terminal of the operational amplifier circuit 83 is connected to the input terminal of the DA converter 87. The output terminal of the circuit 83 is connected to the connection point of the resistor R1 and the temperature characteristic circuit 81 with the resistors R3 and R2 and the switch 85.
, The connection point of the resistors R3 and R2 is connected to the inverting input terminal (-) of the operational amplifier circuit 83, and the non-inverting input terminal (+) of the operational amplifier circuit 83 is grounded. It is composed.

As can be seen from this figure, the correction control circuit 1
When the control signal supplied from input terminal 5 through input terminal 84 is at a low level "0", the gain of temperature conversion circuit 82 is increased, and when the control signal is at a high level "1", temperature conversion circuit 82 has a high gain. The gain decreases.

Therefore, the output from the temperature characteristic circuit 81 is amplified by the operational amplifier circuit 83 with a gain corresponding to the control signal at that time, and thereafter, the reference voltage of the DA converter 87 is input as the reference voltage of the DA converter 87. It is supplied to the terminal. The DA converter 87 converts the level data of the defective pixel read from the memory (for example, ROM) 89 by the system controller 90 into an analog signal based on the reference voltage from the temperature conversion circuit 82, and converts the analog signal into an analog signal. Supply to switch 88.

Here, in addition to the level data of the defective pixel described above, the address data of the level data and the like are stored in the memory 89, and the system controller 90 stores the level data of the defective pixel stored in the memory 89 in D. −
An analog switch 88 is supplied with an address signal corresponding to the level data of the defective pixel, that is, a pulse indicating which of the G, R, and B channels is to be corrected.

The analog switch 88 converts a correction signal supplied from the DA converter 87 into an output terminal 91 for the G channel, an output terminal 92 for the R channel, or an output terminal 92 for the B channel in accordance with an address signal from the system controller 90. The signal is supplied to the adder circuit 9, 10 or 11 shown in FIG. 1 through one of the output terminals 93, and is supplied from the DA converter 87 according to the mask signal supplied from the correction control circuit 15 via the input terminal 86. The supply of the correction signal to the output terminal 91, 92 or 93 is determined.

Now, the operation of the correction circuit 16 will be described with reference to FIG.

FIG. 20A shows an output from the sampling circuit 3 shown in FIG. 1, and as shown in FIG.
The projecting portion indicated by oblique lines is a temperature-dependent charge offset, and has a property that the level increases in proportion to the accumulation time for photoelectric conversion. That is, this is one of the defective pixels that produces a unique level of output on the projected image.

Here, the waveform shown in FIG.
The output by the defective pixel can be canceled by performing the defective pixel correction by adding the waveform shown in FIG. However, the output level of a defective pixel may change with time, and as shown by a broken line in FIG. 20A, the level output by one defective pixel in the waveform with time increases as shown by p20. May be.

In such a case, even if the output of the defective pixel is corrected, the level increase p2 indicated by the broken line in FIG.
0 becomes an output of a peculiar level and appears in the output.
Here, if the output of the defective pixel is corrected, as shown in FIG. 20C, the portion corresponding to the level increase p20 shown in FIG. 20A is replaced by the immediately preceding output.

When defective pixel correction is performed using the waveform shown in FIG. 20B in the state shown in FIG. 20C,
As indicated by hatching in 0D, an output of the opposite polarity corresponding to the level increase p20 indicated by the broken line in FIG. 20 appears.

Therefore, in this embodiment, a mask signal (for example, a pulse for two clocks) as shown in FIG. 20E is generated by the correction control circuit 15, and this mask signal is supplied via the input terminal 86 shown in FIG. Analog switch 8
8 and the analog switch 88
When the mask signal shown in FIG. 20 is at the high level "1", the output is not performed. As a result, as shown by the broken line in FIG. 20F, the portion p21 having the polarity opposite to that of the level increase p20 shown in FIG. I do.

Therefore, it is possible to accurately correct the output of the defective pixel whose output level changes depending on the temperature, thereby improving the accuracy of the correction of the output of the defective pixel, and performing a good correction of the defective pixel.

As described above, the correction circuit 16
In FIG. 19, the control signal (switching signal) from the correction control circuit 15 causes the temperature conversion circuit 82 shown in FIG.
Try changing the gain of

This will be described with reference to FIG.

FIG. 21A shows an output from the sampling circuit 3 shown in FIG. 1, and as shown in FIG. 21A,
The protruding portion indicated by oblique lines, that is, the output 22 of the defective pixel that has already existed is a temperature-dependent charge offset, and has a property that the level increases in proportion to the accumulation time for photoelectric conversion. That is, this is one of the defective pixels that produces a unique level of output on the projected image.

Here, the waveform shown in FIG.
The output by the defective pixel can be canceled by performing the defective pixel correction by adding the waveform shown in FIG. However, as shown by the broken line in FIG. 21A, when a peculiar level output p23 suddenly appears (a peculiar level at which a normal pixel is suddenly determined to be a defective pixel is output).
If the output of the defective pixel is corrected here, for example, when the above-described charge accumulation time is longer than usual (for example, it is described as twice), the output of each defective pixel shown in FIG. Figure 2 shows the levels of p22 and p23
The level is doubled as shown in FIG. 1C.

Here, when the output of the defective pixel is corrected with the waveform shown in FIG. 21B, as shown in FIG. 21D, the output of the defective pixel already exists as shown in FIG. 21A which has been canceled by the correction for the output of the normal defective pixel. Output p22 of the defective pixel
Up to the output, and these are detected as defective pixels.

Therefore, in this embodiment, the correction control circuit 15
19, the switch 85 shown in FIG. 19 is turned off to increase the gain of the temperature conversion circuit 82, thereby doubling the reference voltage of the DA converter 87, for example. The output level of the pixel is doubled as shown in FIG. 21E.

As a result, as shown in FIG. 21F, only a portion corresponding to the output p23 of the new defective pixel remains.
This makes it possible to make corrections. Therefore, the output of a suddenly generated defective pixel can be appropriately detected, and an appropriate correction process can be performed on the detected defective pixel. As a result, a good defective pixel can be detected and corrected. it can. In addition, the output of a defective pixel not to be detected is not erroneously detected.

Next, the pre-detection processing circuit 21 shown in FIG. 1 will be described with reference to FIG.

In FIG. 22, reference numeral 100 denotes a signal from the movable contact 20e of the switch 20 in FIG.
0 or 11, or an input terminal to which temperature information from the temperature sensor 7 is supplied. A signal supplied through the input terminal 100 is supplied to the amplifier circuit 102 and the delay element 101 via the resistor R4. You.

The main purpose of the detection pre-processing circuit 21 is to reduce detection errors due to sampling frequency components. Therefore, the above-described resistor R4 and the delay element 101 remove the carrier component from the input signal which is the target of the erroneous detection, and the input signal from which the carrier component has been removed is amplified by, for example, the amplifier circuit 102 having a gain of several tens of times. Then, the amplified input signal is converted into a digital signal by the AD converter 103, and the digital signal obtained by this conversion is supplied to the detection circuit 22 shown in FIG. When the detection pre-processing circuit 21 is used, for example, the detection target level of several mV is 100 mVp.
Even if it is added to the −p carrier component, the detection target level of several mV can be supplied to the detection circuit 15.

Next, the operation of the pre-detection processing circuit 21 will be described with reference to FIG.

A signal having a protruding portion p30 (for example, based on an output signal of a defective pixel) indicated by oblique lines in a part of the signal as shown in FIG. 23A is supplied to the detection preprocessing circuit 21 via the input terminal 100 of FIG. Is input, if the delay element 101 shown in FIG. 22 is impedance-matched, the signal passing through the resistor R4 becomes
As shown in FIG. 23B, the protruding portion p30 in the waveform of FIG. 23A becomes a protruding portion p31 indicated by oblique lines.

When the signal shown in FIG. 23 is delayed by delay element 101 shown in FIG. 22, the phase is inverted by 180 degrees at the point indicated by arrow dl in FIG. 22, and the reflected waveform becomes as shown in FIG. 23C. 23B, the phase of the protruding portion p31 in the waveform of FIG. 23B is inverted (the same applies to other portions), and the waveform is further delayed by one period.

Therefore, the signal supplied to the amplifier circuit 102 shown in FIG. 22 is a waveform obtained by adding the waveform shown in FIG. 23B and the waveform shown in FIG. 23C, that is, as shown in FIG.
Only the protruding portion p30 indicated by oblique lines in FIG. 3A has a waveform extracted. Then, the waveform shown in FIG. 23D is made into a voltage having a level exceeding a threshold level Th for judging a defective pixel in the detection circuit 22 as shown in FIG. 23E in the amplifier circuit 102 shown in FIG. After this is converted into a digital signal by the A / D converter 103, it is supplied to a detection circuit 22 described later.

Therefore, only the output of the defective pixel can be accurately taken out, whereby a good defect can be detected, and the output of the good defective pixel can be corrected. The temperature information from the temperature sensor 7 is provided separately from A
A digital signal may be converted by a -D converter and supplied directly to each unit.

Next, the detection circuit 22 shown in FIG. 1 will be described with reference to FIG.

In FIG. 24, reference numeral 110 denotes an input terminal to which a digital signal subjected to pre-detection processing from the pre-detection processing circuit 21 shown in FIG. 1 is supplied. Circuit 111
Respectively.

The addition circuit 112 adds the input signal supplied via the input terminal 110 and the feedback signal, and supplies the added output to the flip-flop circuit 114 via the time constant circuit 113. The flip-flop circuit 114 supplies the output signal from the time constant circuit 113 to the subtraction circuit 111 based on the output signal from the comparator 116, which will be described later, and feeds it back to the addition circuit 112 as described above. The addition circuit 112, the time constant circuit 113 and the flip-flop circuit 114 constitute a low-pass filter. Therefore, the signal output from the flip-flop circuit 114 is a signal of the average level of the DC neighboring pixels from which the so-called whiskers and noise components of the original signal have been removed.

The output from the flip-flop circuit 114 is supplied to a subtraction circuit 111.
In the above, the output signal of the flip-flop circuit 114 is subtracted from the input signal supplied via the input terminal 110, that is, the signal that is likely to be the output of the defective pixel. The signal obtained by this subtraction is supplied to the absolute value circuit 115. This absolute value circuit 115 obtains the absolute value of the signal from the subtraction circuit 111. That is, the level of the white point (white defect) due to the output of the defective pixel and the level of the black point (black defect) due to the output of the defective pixel are set to the same polarity, and then supplied to the comparator 116 and the signal supplied from the subtraction circuit 111. Determines whether the signal is a signal due to a white defect or a signal due to a black defect, generates a control signal (flag) according to the result of the determination, supplies the control signal to the switch 119, and controls the switching of the switch 119.

One fixed contact 11 of this switch 119
9a is connected to the output terminal of a threshold circuit 117 that outputs a positive threshold signal, the other fixed contact 119b is connected to the output terminal of a threshold circuit 118 that outputs a negative threshold signal, and the movable contact 119c is connected. Connected to one input terminal of comparator 116.

This switch 119 generates a threshold level signal from a threshold circuit 117 for generating a threshold level (a positive signal) corresponding to a white defect and a threshold level (a negative signal) for a black defect. Threshold circuit 11
8 in accordance with the control signal from the absolute value circuit 115.
16 is a switch to be supplied to the switch. Note that the threshold circuits 117 and 118 may read the threshold level data stored in the memory by a read circuit and convert the threshold level data into analog signals by a DA converter, or a circuit configuration that simply generates an analog voltage. A circuit inside the controller 4 may be used.

The comparator 116 compares the absolute value signal from the absolute value circuit 115 with the threshold level signal supplied from the threshold circuit 17 or 18 via the switch 119, and the absolute value signal is larger than the threshold level signal. In this case, the output from the corresponding pixel is determined to be an output from the defective pixel, and a control signal is supplied to the flip-flop circuit 114 so that the output of the corresponding defective pixel is not input to the flip-flop circuit 114. This is because if the output of a defective pixel is used to obtain the average level of neighboring pixels, the average value will be disturbed.

Here, a low-pass filter (hereinafter, referred to as a filter) composed of the above-described addition circuit 112, time constant circuit 113, and flip-flop circuit 114 obtains the above-described average value of the neighboring pixels. Will be described.

The output of this filter is the weighted average of the previous pixel in the horizontal direction. Now, the horizontal address is k
Assume that attention is paid to the pixel of. Assuming that the level of the pixel at the address k is Pk, the output (average level of neighboring pixels) Pkm of the filter at the time point k is (1 / 2Pk-1).
+ (1 / 4Pk-2) + (1 / 8Pk-3) + (1/1
6Pk-4) +... + ｛(1/2 to the nth power) Pk-n
+ ... Therefore, it can be said that it is effectively a weighted average of several pixels in front.

Next, the operation of the detection circuit 22 will be described.

The digital signal from the pre-detection circuit 21 is input to the addition circuit 112 and the subtraction circuit 11 via the input terminal 110.
1 is supplied. The output from the adding circuit 112 is supplied to the flip-flop circuit 114 via the time constant circuit 113.

On the other hand, when the output of the subtraction circuit 111 is supplied to the absolute value circuit 115, the absolute value circuit 115 detects the polarity of the input signal and, based on the detection result, detects a signal due to a white defect or a black defect. And a control signal based on the determination result is supplied to the switch 119, the input signal is converted into absolute value data, and the converted data is supplied to the other input terminal of the comparator 120.

On the other hand, the switch 119 is connected to the absolute value circuit 115.
The movable contact 119c is connected to one or the other movable contact 119a or 119b on the basis of a control signal from the control unit. As a result, a positive (for white defect) or negative (for black defect) threshold level signal from the threshold circuit 117 or 118 is read out, and the read threshold level signal is input to one input terminal of the comparator 116. Supplied to

The comparator 116 compares the absolute value data from the absolute value circuit 115 with the threshold level signal supplied from the threshold circuit 117 or 118. If the absolute value data is larger than the threshold level signal, the comparator 116 detects a defective pixel. Is supplied to the system controller 4 shown in FIG. 1 through the output terminal 120, and a control signal is supplied to the flip-flop circuit 114. Do not take in the signal of. As a result, it is possible to prevent disturbance of the average level of the neighboring pixels due to the output of the defective pixel.

As described above, the detection circuit 22 determines whether the signal to be detected is due to a black defect due to the negative output of the defective pixel or a white defect due to the positive output of the defective pixel, and determines that the signal is a white defect. In this case, it is determined whether or not the output is due to a defective pixel by using a threshold level signal for white defects, and if it is determined to be a black defect, the output is to be determined by using the threshold level signal for black defects. Since the determination is made, it is possible to prevent erroneous detection due to so-called whiskers, noise, or the like, and perform good detection.

As described above, in this example, when the temperature is low, the system controller 4 obtains the previous detection data based on the temperature information from the temperature sensor 7 shown in FIG. The method of adding the information of defective pixels is adopted, and the previous detection data is deleted when the temperature is high, so that accidentally erroneously detected data can be deleted and the accident that defective pixels are not detected at low temperatures. This makes it possible to effectively use a memory having a limited capacity, to perform reliable and highly accurate defective pixel detection, and to perform good defective pixel correction.

The above embodiment is an example of the present invention.
It goes without saying that various other configurations can be adopted without departing from the spirit of the present invention.

[0156]

According to the present invention described above, when a new defective pixel detection operation is performed, the data of the defective pixel stored in the storage means is invalidated according to the temperature information obtained from the temperature sensor, and the new defective pixel is detected. A mode in which only the data of the detected defective pixel is stored in the storage unit, the data of the defective pixel stored in the storage unit is held, and the data of the newly detected defective pixel is added to the storage unit and stored. Since the mode is selectively switched, for example, when the temperature is high, the data of the accidentally erroneously detected data can be deleted by deleting the information of the defective pixel detected last time. By adding the information of the defective pixel to be detected this time to the information of the defective pixel, it is possible to prevent an accident that the defective pixel is not detected at a low temperature, thereby reducing the capacity of the memory. It enables the use of the Li, reliable, and,
There is an advantage that highly accurate defective pixel detection can be performed and good defective pixel correction can be performed.

According to the present invention described above, when a temperature of a predetermined temperature or less is detected by the temperature sensor when a new defective pixel is detected, the defective pixel stored in the storage means is stored. And the data of the newly detected defective pixel is added and stored in the storage means, so that the data of the defective pixel previously detected, for example, when the temperature is high, can be stored, and thereby the defective pixel can be stored. There is an advantage that sufficient correction can be performed on the pixel.

According to the present invention described above, when the temperature sensor detects that the temperature is equal to or higher than a predetermined value when a new defective pixel detecting operation is performed, the defective pixel stored in the storage means is stored. Is invalidated, and only the data of the newly detected defective pixel is stored in the storage means, so that the data due to the accidental erroneous detection can be quickly erased and the appropriate correction of the defective pixel can be performed. There are benefits that can be done.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a video camera to which an embodiment of a defective pixel detection circuit of a solid-state imaging device according to the present invention is applied .

FIG. 2 is a waveform diagram for explaining a sampling circuit of a video camera to which an embodiment of a defective pixel detection circuit of a solid-state imaging device according to the present invention is applied ;

FIG. 3 is a waveform diagram for explaining defective pixels detected by a video camera to which an embodiment of a defective pixel detection circuit of a solid-state imaging device according to the present invention is applied ;

FIG. 4 illustrates a defect of a video signal performed by a video camera to which an embodiment of a defective pixel detection circuit of a solid-state imaging device according to the present invention is applied.
FIG. 6 is a waveform diagram for explaining cancellation of components .

FIG. 5 is a configuration diagram showing a sampling circuit of a video camera to which an embodiment of a defective pixel detection circuit of the solid-state imaging device according to the present invention is applied ;

FIG. 6 is a waveform diagram for explaining a sampling circuit of a video camera to which an embodiment of a defective pixel detection circuit of a solid-state imaging device according to the present invention is applied ;

FIG. 7 is a waveform diagram for explaining a sampling circuit of a video camera to which an embodiment of a defective pixel detection circuit of a solid-state imaging device according to the present invention is applied ;

FIG. 8 is a configuration diagram showing another sampling circuit of a video camera to which an embodiment of the defective pixel detection circuit of the solid-state imaging device according to the present invention is applied .

FIG. 9 is a configuration diagram showing a system controller of a video camera to which an embodiment of a defective pixel detection circuit of a solid-state imaging device according to the present invention is applied ;

FIG. 10 is a configuration diagram showing a register of a video camera to which an embodiment of a defective pixel detection circuit of a solid-state imaging device according to the present invention is applied ;

FIG. 11 is an explanatory diagram for explaining an operation of a register of a video camera to which an embodiment of a defective pixel detection circuit of a solid-state imaging device according to the present invention is applied ;

FIG. 12 is an explanatory diagram for explaining an operation of a register of a video camera to which an embodiment of a defective pixel detection circuit of a solid-state imaging device according to the present invention is applied ;

FIG. 13 is an explanatory diagram for explaining an operation of a register of a video camera to which an embodiment of a defective pixel detection circuit of a solid-state imaging device according to the present invention is applied ;

FIG. 14 is an explanatory diagram for explaining an operation of a register of a video camera to which an embodiment of a defective pixel detection circuit of a solid-state imaging device according to the present invention is applied ;

FIG. 15 is an explanatory diagram for explaining an operation of a register of a video camera to which an embodiment of a defective pixel detection circuit of a solid-state imaging device according to the present invention is applied ;

FIG. 16 is an explanatory diagram for explaining an operation of a register of a video camera to which an embodiment of a defective pixel detection circuit of a solid-state imaging device according to the present invention is applied ;

FIG. 17 is an explanatory diagram for explaining an operation of a register of a video camera to which an embodiment of a defective pixel detection circuit of a solid-state imaging device according to the present invention is applied ;

FIG. 18 is an explanatory diagram for explaining an operation of a register of a video camera to which an embodiment of a defective pixel detection circuit of a solid-state imaging device according to the present invention is applied ;

FIG. 19 is a configuration diagram showing a correction circuit of a video camera to which an embodiment of a defective pixel detection circuit of a solid-state imaging device according to the present invention is applied .

FIG. 20 is a waveform diagram for explaining a correction circuit of a video camera to which an embodiment of a defective pixel detection circuit of a solid-state imaging device according to the present invention is applied ;

FIG. 21 is a waveform diagram for explaining a correction circuit of a video camera to which an embodiment of a defective pixel detection circuit of a solid-state imaging device according to the present invention is applied ;

FIG. 22 is a configuration diagram showing a detection pre-processing circuit of a video camera to which an embodiment of a defective pixel detection circuit of a solid-state imaging device according to the present invention is applied .

FIG. 23 is a waveform diagram for explaining a detection pre-processing circuit of a video camera to which an embodiment of a defective pixel detection circuit of a solid-state imaging device according to the present invention is applied ;

FIG. 24 is a configuration diagram showing a detection circuit of a video camera to which an embodiment of a defective pixel detection circuit of a solid-state imaging device according to the present invention is applied ;

Claims (3)

(57) [Claims] 1. A defective pixel detecting means for detecting a defective pixel outputting a signal of a peculiar level from among the pixels of the solid-state image sensor based on an output signal of the solid-state image sensor; Small number of detected defective pixels
Storage means for storing address data representing at least a position; a temperature sensor for detecting the temperature of the solid-state imaging device; and a detection level of temperature information obtained by the temperature sensor when a new defective pixel detection operation is performed. And the specified value
A mode in which the data of the defective pixel stored in the storage unit is invalidated according to the result, and only the data of the newly generated and detected defective pixel is stored in the storage unit. Holds pixel data and newly
A control unit for selectively switching a mode in which data of the detected and detected defective pixel is additionally stored in the storage unit. 2. A defective pixel detecting means for detecting a defective pixel outputting a signal of a peculiar level from each pixel of the solid-state image sensor based on an output signal of the solid-state image sensor, Small number of detected defective pixels
Storage means for storing at least address data representing a position; a temperature sensor for detecting the temperature of the solid-state imaging device; and a temperature lower than a predetermined value by the temperature sensor when a new defective pixel detection operation is performed. Is detected, the control means for holding the data of the defective pixel stored in the storage means, and adding and storing the data of the newly generated and detected defective pixel in the storage means. And a defective pixel detection circuit for a solid-state imaging device. 3. A defective pixel detecting means for detecting a defective pixel outputting a signal of a peculiar level from each pixel of the solid-state image sensor based on an output signal of the solid-state image sensor; Small number of detected defective pixels
Storage means for storing at least address data representing a position; a temperature sensor for detecting a temperature of the solid-state imaging device; and a temperature higher than a predetermined temperature by the temperature sensor when a new defective pixel detection operation is performed. And control means for invalidating the data of the defective pixel stored in the storage means and storing only data of a newly generated and detected defective pixel in the storage means when is detected. A defective pixel detection circuit for a solid-state imaging device, comprising: