JPH05343664A - Static induction thyristor - Google Patents

Abstract

PURPOSE:To obtain a gate breakdown voltage and to switch a static induction thyristor with low driving power in the thyristor having a driving gate region and a ground gate region. CONSTITUTION:A first gate region 13 formed on one surface of a semiconductor substrate is connected to a cathode electrode 16, and short-circuited to a cathode region 14. A second gate region 15 is buried, and connected to a gate electrode 17. An anode region 18 is formed on the other surface of the substrate. A distance between the region 15 of the buried structure and the region 13 formed on the surface is obtained to enhance a gate breakdown voltage, power loss of driving the gate is reduced to simplify a driving circuit. Further, injection of carrier at the time of turning OF is suppressed, and carrier storage time is short, and hence a high speed switching is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic induction thyristor capable of controlling large electric power with low driving electric power.

[0002]

2. Description of the Related Art Conventionally, an electrostatic induction thyristor has been known as one of power control semiconductor elements. In the electrostatic induction thyristor, a large gate current flows because residual carriers are extracted from the gate at the time of turn-off, and therefore, the gate drive circuit needs to be devised. Therefore, for example, an improved element structure near the gate region has been proposed. The present inventors have devised an electrostatic induction thyristor 21 having a surface type split gate structure as shown in FIG. 2 as an example of such an electrostatic induction thyristor (see Japanese Patent Application No. 3-110647).

The electrostatic induction thyristor 21 having the structure shown in FIG.
On one surface of the N-type semiconductor substrate 22, N for the cathode region is formed.
A type impurity diffusion region 24 is formed, and a P type impurity diffusion region 23 for the drive gate region and a P type impurity diffusion region 25 for the ground gate region are independently formed so as to narrow the region, and the surface of the drive gate region 23 is formed. Is provided with a gate electrode 27, the surfaces of the ground gate region 25 and the cathode region 24 are short-circuited by the cathode electrode 26, and an N-type and P-type bonding surface is formed inside the semiconductor substrate 22. A P-type impurity region 28 for an anode region is formed on the other surface, and an anode electrode 29 is provided on the surface.

[0004]

In the conventional example of FIG. 2, the gate region is divided into a driving gate region 23 and a ground gate region 25, and the ground gate region 25 is directly connected to the cathode region 24, whereby excessive carrier injection is performed. Since the current is suppressed, the gate extraction current at turn-off can be reduced, and high-speed switching operation can be realized. However, the drive gate region 23 and the ground gate region 25
Since the punch-through withstand voltage during the period is low, the gate withstand voltage is low, resulting in a large gate drive power and poor gate driveability.

The present invention has been made in view of the above points, and an object thereof is to provide an electrostatic induction thyristor capable of ensuring a gate breakdown voltage and performing a switching operation with low drive power. It is in.

[0006]

In order to solve the above-mentioned problems, an electrostatic induction thyristor of the present invention is provided, as shown in FIG. 1, on one surface of a semiconductor substrate 11 of one conductivity type for a cathode region. One conductivity type impurity diffusion region 14 is formed, another conductivity type impurity diffusion region 13 for the first gate region is formed so as to sandwich the cathode region 14, and the second conductivity type impurity diffusion region 13 is formed inside the semiconductor substrate 11. An impurity diffusion region 15 of another conductivity type for the gate region is formed, a cathode electrode 16 is formed on the surfaces of the cathode region 14 and the first gate region 13, and a gate electrode 17 is formed on the surface of the second gate region 15. Forming,
A junction surface of one conductivity type and another conductivity type is formed inside the semiconductor substrate 11, an impurity region 18 of another conductivity type for an anode region is formed on the other surface of the semiconductor substrate 11, and a surface of the anode region 18 is formed. The anode electrode 19 is formed on the anode.

[0007]

In the structure of the present invention, the drive gate region 15 has the buried structure and the ground gate region 13 has the surface structure, so that the distance between the drive gate region 15 and the ground gate region 13 can be increased. The gate breakdown voltage can be secured, and the normally-on / off characteristics can be determined at the intervals of the drive gate regions 15. As a result, the gate breakdown voltage characteristic and the normally-on / off characteristic can be independently determined. Further, by adopting the gate short-circuit structure in which the ground gate region 13 is short-circuited with the cathode region 14, proper carrier injection from the embedded drive gate region 15 to the semiconductor substrate 11 occurs at the time of gate forward bias, and the forward modulation is performed by the conductivity modulation. The directional voltage drop can be kept low. Furthermore, at the time of turn-off, carriers are quickly ejected through the cathode region 14 and the ground gate region 13. At this time, since the carrier is less accumulated, the accumulation time can be shortened and the high speed switching operation can be performed. Moreover, since the gate resistance of the embedded drive gate region 15 is larger than that of the ground gate region 13 on the surface (-10Ω), the peak value of the gate extraction current can be reduced. Furthermore, since the cathode electrode 16 can have a large area, plate-shaped bonding can be performed, and as compared with the conventional wire bonding, the wiring inductance can be reduced and high-speed switching operation can be performed. Due to the above-described actions, it is possible to provide an element which has low gate drive power, is easily driven, and is capable of high-speed switching operation.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. First, the P-type impurity diffusion region 15 for the drive gate region is formed on one surface of the N-type semiconductor substrate 11. The normally-off / normally-on characteristics can be determined by the distance between the drive gate regions 15. If normally off, the impurity concentration of the semiconductor substrate 11 is 6.5 × 10 5.
^When the driving gate region 15 is ¹³ cm ^-3 and the P-type impurity concentration of the driving gate region 15 is 1 × 10 ¹⁸ cm ^-3 , the distance between the driving gate regions 15 needs to be 3.7 μm or less. Next, the N-type semiconductor substrate 12 is epitaxially grown on one surface of the N-type semiconductor substrate 11. An N-type impurity diffusion region 14 for the cathode region is formed on the surface of the N-type semiconductor substrate 12, and a P-type impurity diffusion region 13 for the ground gate region is formed so as to sandwich the N-type impurity diffusion region 14 for the cathode region. Then, the cathode electrode 16 is formed on the surface of each of the regions 13 and 14 via the oxide film. At this time, the buried gate region 15 is not arranged immediately below the cathode region 14. Further, with respect to the embedded drive gate region 15, a trench groove is formed at one end on the front surface side to form a drive gate electrode 17. A P-type anode region 18 is formed on the other surface of the N-type semiconductor substrate 11, and a PN junction surface is provided inside the semiconductor substrate 11. An anode electrode 19 is formed on the surface of the anode region 18 to complete the electrostatic induction thyristor 10.

[0009]

According to the structure of the electrostatic induction thyristor of the present invention, the first gate region formed on the surface of the semiconductor substrate is short-circuited with the cathode region, so that the injection of carriers at the time of turning on is suppressed. , The current drawn from the gate at the time of turn-off can be reduced, and the second gate region has a buried structure, so that a distance from the first gate region formed on the surface can be secured. This has the effect of increasing the gate breakdown voltage, reducing the power loss in gate drive, and simplifying the drive circuit. Moreover, since the carrier storage time is short, high-speed switching operation is possible. ..

[Brief description of drawings]

FIG. 1 is a sectional view of an electrostatic induction thyristor according to the present invention.

FIG. 2 is a cross-sectional view of a conventional static induction thyristor.

[Explanation of symbols]

 10 Electrostatic Induction Thyristor 11 Semiconductor Substrate 12 Semiconductor Substrate (Epitaxial Region) 13 Ground Gate Region 14 Cathode Region 15 Drive Gate Region 16 Cathode Electrode 17 Drive Gate Electrode 18 Anode Region 19 Anode Electrode

Claims (1)

[Claims] 1. A one-conductivity-type impurity diffusion region for a cathode region is formed on one surface of a one-conductivity-type semiconductor substrate, and the other-conductivity-type impurity region for the first gate region is sandwiched so as to sandwich the cathode region. An impurity diffusion region is formed, another conductivity type impurity diffusion region for the second gate region is formed inside the semiconductor substrate, and a cathode electrode is formed on the surfaces of the cathode region and the first gate region. A gate electrode is formed on the surface of the second gate region, a junction surface of one conductivity type and another conductivity type is formed inside the semiconductor substrate, and an impurity region of another conductivity type for the anode region is formed on the other surface of the semiconductor substrate. And an anode electrode is formed on the surface of the anode region.