JPH05342859A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To set a voltage stress mode without necessitating a private pad, and to operate the screening of a defective mode by fixing one part of the output signals of a refresh address counter in the same level. CONSTITUTION:When a bar in test mode signal BITAC is generated based on a prescribed signal inputted from one part of outside terminals 2 used at the time of the normal operation of a DRAM 10, only the upper bits of the output signals of a refresh address counter 4 are fixed in the same level, so that an AC bar in test mode of a short time system can be obtained. At that time, the lower bits of the output signals of the address counter 4 are changed accompanied with the operation of a counter, so that an AC voltage stress mode in which a high voltage is impressed to the word line ML of the DRAM circuit 10, and a duty rate is higher than the normal operation, can be set. Thus, the screening of the deterioration of the breakdown strength of the insulating film of a memory cell transfer gate can be attained in a short time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a circuit for performing a voltage stress test on a DRAM (dynamic random access memory).

[0002]

2. Description of the Related Art In a DRAM, the highest electric field (voltage stress) is applied to the gate insulating film of a transfer gate transistor (cell transistor) of a memory cell in which a word line is connected to a gate electrode. There is a high probability that reliability problems will occur. Also, DR
AM has 2 refresh cycles for each next generation
Since it is doubled, the duty ratio at which a high electric field is applied to the word line when the normal cycle is repeated is halved for each generation.

Conventionally, in the burn-in of DRAM, the power supply voltage is raised to accelerate the electric field applied to the gate insulating film of the cell transistor. However, since the word lines are sequentially selected, the gate insulating film of the cell transistor is screened. Was taking too long. Therefore, even if the generations of DRAMs change, if the total time required for screening by applying a high electric field to the gate insulating film of the cell transistor is constant, the burn-in test time doubles for each generation. go.

Therefore, there is an increasing need for shortening the DRAM burn-in test time in the future. As one of the solutions, it has been proposed to mount a mode in which a direct current is applied to the word lines to perform burn-in in a state where the number of word lines selected at the same time is increased more than in the normal operation. Hereinafter, this mode is referred to as a time-saving direct current (DC) burn-in test mode in order to distinguish it from the conventional normal burn-in mode.

One of means for realizing the time-saving DC burn-in test mode is, as proposed by Japanese Patent Application No. 2-418371, an extra pad dedicated to the voltage stress test which is not used during normal operation. In this case, by applying a stress voltage to the above pad during the burn-in test in the wafer state, more word lines than the number selected in normal operation are set at the same time, and the burn-in test is performed in this state. Is what you do.

On the other hand, it is also necessary to screen in advance a decrease in withstand voltage between adjacent word lines due to dust. For example, it is divided into two groups, an even-numbered word line group and an odd-numbered word line group in the word line array, and they are simultaneously raised to high levels. By applying a voltage, it is possible to mount a mode in which a sufficient voltage is applied between adjacent word lines to perform burn-in.
-418374. Hereinafter, this mode is referred to as a time-saving type AC (AC) burn-in test mode. 17 to 19 show Japanese Patent Application No. 2-4183.
A circuit for realizing the AC burn-in test mode of the time saving system proposed by No. 74 is shown.

The circuit shown in FIG. 17 raises the control clock signal φBOOT during the operation in the burn-in test mode.
It is used in a bootstrap word line drive type DRAM that transfers charges stored in advance in the bootstrap capacitor CBOOT to the selected word line WL0i → WLi through the N-channel MOS transistors 140 to 142.
Then, in the AC burn-in test mode, while applying the burn-in voltage to the voltage stress test dedicated pad 143, a part of the address signals A0 to An are both set to the "L" level, and the NOR type decoder 144 or 14 is supplied.
The voltage stress is simultaneously applied to the word lines which are not adjacent to each other by simultaneously setting a plurality of cells 5 in the selected state. At this time, the potential of the bit line BL is set to the transfer gate 1 controlled by the bit line precharge signal φPRE.
It is fixed to the ground potential via 46 and the pad 147.

In the circuits shown in FIGS. 18 and 19, pads 148 to 150 dedicated to the voltage stress test are provided, and transfer gates 151 or 152 are connected to one ends of all the word lines WL0i, WL1i. The transfer gate 151 or 152 is selectively driven so as to select the second word line group or the odd word line group, and the selected word line group (in the word line array) is selected from the pads connected to the other ends thereof. Every other word line) is subjected to voltage stress at the same time.

However, in the burn-in test mode using the voltage stress test dedicated pad described above, the voltage stress test cannot be performed on the DRAM encapsulated in the package.

In order to make it possible to set the DC burn-in test mode of the time saving system in a wafer state or a state after encapsulating in a package without requiring a pad dedicated to a voltage stress test, the above-mentioned Japanese Patent Application No. 2-4
As proposed by No. 18371, by inputting a control signal from the outside, the signal on the input side or output side of the word line selection circuit is forcibly controlled to a constant level, and Also, there is a method in which many word lines are simultaneously set in a selected state and a burn-in test is performed in this state.

However, as described above, as a circuit configuration for setting the burn-in test mode of the time saving system by inputting a control signal from the outside, circuits other than those required for the normal operation mode are eliminated as much as possible, It is desirable to suppress the increase in area. In addition, when setting the burn-in test mode of the time saving method, it may be necessary or desirable to control not only the word line selection circuit but also other circuits at the same time. desired.

The circuits shown in FIGS. 17 to 19 are
When the AC burn-in test mode of the time saving method is realized, since the normal operation (DRAM operation) is not performed, it is difficult to predict the failure mode that may occur from the actual operation,
For example, it is impossible to screen in advance a failure mode such as a breakdown voltage reduction between adjacent bit lines.

[0013]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has a high duty ratio AC voltage stress test mode in which a high voltage is applied to a word line in a wafer state or a state after being enclosed in a package. When setting, the pad for exclusive use of the voltage stress test is not required, the circuits other than the circuits required for the normal operation mode are eliminated as much as possible, and it is possible to suppress the increase of the chip area. To provide a semiconductor memory device capable of simultaneously screening any unpredictable failure modes that may occur during normal operation, such as a reduction in withstand voltage between adjacent word lines or between adjacent bit lines, by performing almost the same operation as the above. With the goal.

[0014]

The semiconductor memory device of the present invention is based on a DRAM circuit and a voltage stress test mode based on a predetermined signal input from a part of external terminals used during normal operation of the DRAM circuit. A voltage stress test mode signal generating circuit for generating a signal and a test mode signal from the voltage stress test mode signal generating circuit are received, and only upper bits of a certain bit or more of the output signal of the refresh address counter of the DRAM circuit are provided. A control circuit for controlling to fix the same level and controlling so that lower bits less than the specific bit normally operate to count.

[0015]

A voltage stress test mode signal is generated based on a predetermined signal input from a part of external terminals used during normal operation of the DRAM circuit, and this signal is received to output the output signal of the refresh address counter. Only the upper bits are fixed to the same level. In this case, since the lower bit of the output signal of the refresh address counter changes in accordance with the counter operation, the duty ratio in which a high voltage is applied to the word line of the DRAM circuit is higher than that in the normal operation.
It is possible to set the C voltage stress test mode, and it is possible to screen the decrease in withstand voltage of the insulating film of the memory cell / transfer gate in a short time.

Therefore, no special pad is required to set the voltage stress test mode, and the voltage stress test mode can be set in the wafer state or the state after being encapsulated in the package, and the normal operation is possible. Circuits other than those required for the mode can be eliminated as much as possible, and the increase in chip area can be suppressed.

Furthermore, by performing almost the same operation as a normal DRAM operation, it is possible to simultaneously screen for any unpredictable failure modes that may occur during normal operation, such as a decrease in breakdown voltage between adjacent word lines or between adjacent bit lines. It will be possible. As used herein, "almost the same" means that the word lines are selected at the same time for the memory cell blocks that are considered to be independent from each other with respect to the withstand voltage reduction failure mode because the word lines are sufficiently separated from each other, thereby shortening the screening time. It means that

[0018]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows a part of a DRAM equipped with a time saving AC burn-in test mode according to a first embodiment of the present invention. First, an outline of the DRAM of FIG. 1 will be described.

The DRAM circuit 10 has a normal access mode, a normal burn-in mode, and a standardized multi-bit parallel test mode, and simultaneously applies AC voltage stress to more word lines than the number selected during normal operation. It has a time saving AC burn-in test mode.

Burn-in test mode signal generation circuit 20
Generates the burn-in test mode signal BITAC based on a predetermined signal input from a part of the external terminal 2 used during the normal operation of the DRAM circuit 1. In this example, the burn-in test mode signal BIT
AC goes to a high level "H" when activated, and goes to a low level "L" when inactive.

The burn-in test mode control circuit 21 is
By receiving the burn-in test mode signal BITAC from the signal generating circuit 20 and fixing only the upper bits of the complementary output signal of the refresh address counter 4 of the DRAM circuit 10 to the same level, the DRAM
The setting control is performed so that an AC stress test mode (for example, a time-saving AC burn-in test mode) in which the duty ratio in which a high voltage is applied to the word line WL of the circuit 10 is higher than that in normal operation is performed.

According to the DRAM of FIG. 1, the DRAM circuit 1
When the burn-in test mode signal BITAC is generated based on a predetermined signal input from a part of the external terminal 2 used during the normal operation of 0, only the upper bits of the output signal of the refresh address counter 4 of the DRAM circuit 10 are output. By fixing to the same level, the time-saving AC burn-in test mode is entered.

In this case, since the lower bit of the output signal of the refresh address counter 4 changes in accordance with the counter operation, the duty ratio of applying a high voltage to the word line WL of the DRAM circuit 10 is higher than that in the normal operation. It is possible to set the stress test mode, and it is possible to screen the decrease in withstand voltage of the insulating film of the memory cell / transfer gate in a short time.

Therefore, no special pad is required to set the time-saving AC burn-in test mode, the circuits other than those required for the normal operation mode are eliminated as much as possible, and the increase of the chip area can be suppressed. It will be possible.

In addition, since no special pad is required to set the time-saving AC burn-in test mode, it is possible to set the time-saving burn-in test mode in a wafer state or after being encapsulated in a package. Become. As a result, when performing a time saving AC burn-in test in a wafer state, it is possible to use a test device (probe card or the like) used in a normal function test, and after the package is enclosed in a package, the time saving method A
A normal memory tester can be used for the C burn-in test. Next, the DRAM of FIG. 1 will be described in detail.

The DRAM circuit 10 includes a memory cell array 1 in which a plurality of dynamic memory cells are arranged in a matrix, a word line WL connected to the memory cells in the same row of the memory cell array 1, and the memory cell array 1 described above. Of the bit lines BL connected to the memory cells of the same column and the external terminals 2 ... (Power supply terminal 2a to which the power supply voltage is input from the outside,
An address signal and various control signals (such as an input terminal 2b to which a write enable signal / WE, a row address strobe signal / RAS, and a column address strobe signal / CAS are input), and an external address input from a part of the external terminal 2. Address buffer circuit 3 for amplifying signals
A refresh address counter 4 for generating a refresh address signal for the refresh operation of the memory cell, and an output signal of the address counter 4 and a row address signal output of the address buffer circuit 3 for selecting either one. An address switching circuit 5, a row decoder circuit (word line selecting circuit) 6 having a word line selecting function for selecting an arbitrary row according to an internal row address signal output from the address switching circuit 5, and a word line driving voltage. The row decoder circuit 6 has a source 7 and at least one word line driving MOS transistor (a PMOS transistor in this example) connected between the word line driving voltage source 7 and the word line WL. A word line drive circuit 8 for driving the word line WL according to an output signal; A sense amplifier circuit SA for detecting information read out from the cell to the bit line BL, and a column decoder circuit 9 comprises a column selection circuit CS.

Further, in the DRAM circuit 10, a bit line transfer gate TG which is on / off controlled by the control signal φT is inserted between the input node of the sense amplifier SA and the bit line BL.

A bit line precharge / equalize circuit 11, which is on / off controlled by a bit line equalize signal EQL, is connected to the bit line BL. The bit line precharge / equalize circuit 11 is a bit line. Precharge potential (VBL) generation circuit 12 to V
BL is supplied. In addition, it has a redundant configuration for repairing defects (spare memory cells, spare word lines SWL, spare row decoder / word line drive circuit 13, etc.).

The word line driving voltage source 7 is a boosting circuit for boosting the power supply voltage Vcc supplied from the outside of the semiconductor chip on the chip to generate the word line driving voltage VPP. This word line driving voltage VPP Is supplied as the power source of the word line drive circuit 8.

In this case, the word line driving voltage source 7
May be a charge pump type booster circuit, but it is desirable to use a booster circuit having a large current drive capability (for example, a ring oscillator circuit and a rectifier circuit).

A switching circuit that selects the output of the booster circuit during normal operation, selects an externally supplied word line driving voltage during a voltage stress test, and supplies the selected voltage as a word line driving voltage. (Not shown) may be provided, but in this example, the output node of the word line driving voltage source 7 is connected to the external power supply terminal 2 during the voltage stress test.
For example, a short-circuit connection is made to a, and a VPP-VCC short circuit 14 for supplying a word line driving voltage from the outside during a voltage stress test is provided.

The burn-in test mode signal generation circuit 20, for example, has a WCBR cycle (/ WE signal input //
When the CAS signal input is activated before the / RAS signal input), the row address signal input at the time when the / RAS signal is activated is taken in, and if the combination of the predetermined addresses is the BITAC signal. To "H" level.

As described above, when the burn-in test mode is set by the WCBR cycle, in order to have upward compatibility with the setting method of the multi-bit parallel test mode which is one of the existing functional test modes, As proposed by the inventor of the present application in Japanese Patent Application No. 4-132477, the WC is set at the value of the normal use condition of the power supply voltage (for example, 3 V).
If the BR cycle is used, the conventional multi-bit parallel test mode is entered, and if the power supply voltage is set to a high value outside the normal operating range (for example, 6 V) and the WCBR cycle is performed, the BITAC signal becomes "H" level. Good.

Further, when there are several kinds of burn-in test modes, when the power supply voltage is set to a high value outside the normal operating range, a part of the address signal is specified when the / RAS signal input is activated in the WCBR cycle. A setting method for entering the AC burn-in mode of the time saving method may be adopted by setting the combination (in this example, the A0R and A1R bits are both at the “L” level).

When only the time saving AC burn-in test mode as described above is installed, it is not necessary to adopt the complicated setting method as described above, and for example, only the WCBR cycle is used as the time saving AC burn-in. It is possible to set the test mode, or set a certain external terminal to a voltage outside the normal applied voltage (for example, a voltage higher than the normal power supply voltage; super voltage), and detect this A method of setting by setting the burn-in test mode is also possible.

Burn-in test mode control circuit 21
Receives the burn-in test mode signal BITAC from the burn-in test mode signal generation circuit 20, and fixes only the upper bits of the complementary output signal of the refresh address counter 4 of the DRAM circuit 10 to the same level as described above. In addition to the above, it is desirable that the other circuit parts are also configured to control appropriate circuit states corresponding to the AC burn-in test mode. That is, the spare word line SWL is also controlled to be selectively driven at the same duty ratio as the normal word line WL, the capacity of the drive transistor for the sense amplifier circuit SA is limited, and the control signal φT is forcibly activated. It is desirable to control the level (that is, control the bit line transfer gate TG to be in the ON state in the voltage stress test).

Next, a portion related to the present invention in FIG. 1 will be described in detail with reference to FIGS. 2 to 11. Note that the subscript n of each symbol in the drawing indicates that the memory cell array 1 in FIG. 1 corresponds to one cell block among the plurality of divided cell blocks. FIG. 2 is a circuit diagram showing an example of a part (one) of the row address buffer of the address buffer circuit 3 in FIG.

Here, VCC is a power supply potential, VSS is a ground potential, P1 is a P channel MOS transistor, and N1 to N5.
Is an N-channel MOS transistor, C1 and C2 are MOS capacitors in which the drain and source of the N-channel MOS transistors are commonly connected to the VSS node, 22 is a differential latch circuit, / RLTC is a latch control signal, AINj
(J = 0 to 10) is an address signal input from the outside, V
ref is a reference potential, RACP and / RHLD are gate control signals, and (AIjR, / AIjR) are complementary row address buffer output signals. FIG. 3 is a circuit diagram showing an example of a part (one stage) of the refresh address counter 4 and the burn-in test mode control circuit 21 shown in FIG.

Here, reference numerals 31 to 34 are clocked inverters, 35 is an inverter, and complementary output terminals of each stage of the address counter are, for example, a two-input NOR gate which is a part of the burn-in test mode control circuit 21. 36 are inserted, and the BITACj (j = 0 to 10) signal is input to one input end of the NOR gate 36.
This BITACj signal is set as follows.

That is, in the SDRAM circuit 10 of FIG. 1, when the shared sense amplifier system in which the sense amplifier circuits SA are used in a time division manner between adjacent memory cell blocks is not adopted, or as will be described later, AC is used.
When the transfer gate control signal φT is forcibly set to the "H" level in the burn-in test mode, for example, the upper 9 bits (j
= 2 to 10 bits), the BITAC signal is input as one input of the NOR gate 36 inserted at the output end. Then, the VSS potential (“L” level) is input as an input to one input end of the NOR gate 36 inserted into the output end of the remaining lower 2 bits (j = 0, 1 bit) (that is, the NOR gate 36). ... acts as an inverter).

On the other hand, in the DRAM circuit 10 of FIG. 1, the shared sense amplifier system is adopted, and the eighth bit of the address counter output is the sense amplifier circuit SA.
When the transfer gate control signal φT is not forcibly set to the “H” level in the AC burn-in test mode as will be described later, the address counter output of the address counter output is used. Higher-order, for example, 8 bits (j = 3 to 10 bits)
The BITAC signal is input as one input of the NOR gate 36 inserted in the output end of the. Then, the VSS potential (“L” level) is input as an input of one input end of the NOR gate 36 inserted in the output end of the remaining lower 3 bits (j = 0, 1, 2 bits) (that is, NOR gate 36 acts as an inverter). However, j = 2 corresponds to addresses for selecting cell blocks on both sides of the shared sense amplifier. In addition, (CTj, /
CTj) (j = 0 to 10) are complementary output signals of the address counter. FIG. 4 is a circuit diagram showing an example of a part (one) of the address switching circuit 5 shown in FIG.

Here, 41 is an NMOS for address switching.
Transistor, 42 is an inverter for latch circuit, / R
TRS is a switching signal for selecting the row address buffer output,
CT is a switching signal for selecting the address counter output, (RA
Bj, / RABj) is a selection output (internal row address signal).

The circuits of FIGS. 2 to 4 are as shown in the timing waveform diagrams of FIGS. 5, 6 and 7 corresponding to the normal operation of the DRAM, the refresh operation and the AC burn-in test mode of the time saving system. It is logically configured to realize an operation example.

That is, during the normal operation shown in FIG.
The AC signal is at "L" level, and the DRAM circuit 10 operates in the same manner as a conventional DRAM. In other words, after the row address signal is fetched by activating the / RAS signal, / C
During the operation of fetching the column address signal by activating the AS signal, the CT signal is kept at "L" level and / R
The TRS signal maintains the "H" level. As a result, the row address buffer output signals (AIjR, / AIjR) are selected and the internal row address signals (RABj, / RABj) are selected.
Take in as.

FIG. 6 shows the CBR cycle (that is, / CA
An automatic refresh operation by executing the operation of activating the S signal earlier than the / RAS signal is shown. During this refresh operation, the / RTRS signal immediately goes to the "L" level, and the row address buffer output signal (AIj
R, / AIjR) is no longer selected. At the same time, the CT signal is activated, and the output signals (CTj, / CTj) stored in the address counter 4 at that time are selected and taken in as internal row address signals (RABj, / RABj).
At this time, the refresh operation of the memory cell selected by the word line selection signal is performed.

In the operation in the AC burn-in test mode shown in FIG. 7, the BITAC signal becomes "H" level, and the output signal (C
The upper 9 bits (j = 2 to 10) of Tj, / CTj) are fixed to the “L” level, and the lower 2 bits (j = 0, 1) of the output signal (CTj, / CTj) of the address counter 4
Changes with the counter operation. At this time, if the CBR cycle is executed, the internal row address signal (RABj,
The upper 9 bits (j = 2 to 10) of / RABj) are "H"
The level is fixed to the internal row address signal (RABj,
The lower 2 bits (j = 0, 1) of / RABj) change according to the counter operation. Therefore, only a part of the word line drive circuit 8 is selected, and only a part of the word line WL is selected and becomes the “H” level. FIG. 8A is a circuit diagram showing an example of the burn-in test mode signal generation circuit 20.

Here, WCBR is a signal generated by the input of the clock of the WCBR cycle, / A0R and A1R are a part of the internal row address signal when the / RAS signal input is activated, and ROR is the ROR cycle (/ R
This signal is generated by inputting a clock of RAS only refresh cycle in which only the AS signal is temporarily activated. Reference numeral 61 is a three-input NAND gate, 62 is a flip-flop circuit, and 63 is an inverter.

The circuit of FIG. 8A is logically configured to realize an operation example such as the timing waveform diagram of FIG. 8B. That is, when the WCBR cycle is performed when the A0R and A1R bits of the address signal are each at the "L" level, the BITAC signal rises. After the end of the AC burn-in test mode, the BITOR signal is lowered to the "L" level by executing the ROR cycle. FIG. 9 is a circuit diagram showing an example in which part of the row decoder circuit 6 and the word line drive circuit 8 in FIG. 1 is taken out. Where P
Rn and / PRn are precharge signals for the cell block n, 70 is a differential circuit, and PRCHP is a precharge signal output from the differential circuit 70.

71 is an internal row address signal A2R, / A
It is a NAND circuit that decodes a combination signal of 2R, A3R, / A3R, A4R, and / A4R and outputs an XAi (i = 0 to 7) signal.

72 is an internal row address signal A5R, / A
It is a NAND circuit that decodes a combination signal of 5R, A6R, / A6R, A7R, and / A7R and outputs an XBj (i = 0 to 7) signal.

Reference numeral 73 has a PMOS transistor load for a precharge load whose gate receives the PRCHP signal, and the XAi signal, XBj signal and / RSP signal.
It is a NAND circuit that decodes an n signal (a signal for permitting selection of the word line WL).

Reference numeral 74 has a PMOS transistor for a precharge load whose gate receives the PRCHP signal. Internal address signals (A0R, / A0R), (A1)
R, / A1R) combined signal and said / RSPn
This is a NAND circuit for decoding a signal, and in this example, four cells are provided in one cell block.

Reference numeral 75 is the NAND circuit (row decoder) 7
4 is a first word line drive circuit which is selectively driven by the output of 4 and 76 is a second word line drive circuit which is selectively driven by the output of the NAND circuit (row decoder) 73.

WL0n is the first word line drive circuit 7
One end side is connected to each output node 5 (four in one cell block in this example), and the other end side is a second group of one group. Connected to the drive voltage source node of the drive line drive circuit 76. WDRVn
j is the voltage of the word line WL0n, and / WDRVnj is the inverted level of the word line voltage WDRVnj. WL is the second word line drive circuit 76 of the first group.
Is a word line whose one end is connected to each output node.

The first word line drive circuit 75 is connected between the word line drive PMOS transistor TP connected between the drive voltage source node and the word line WL0n and between the word line and the VSS node. NMOS transistor 7
7, a pull-up PMOS transistor 78 connected between the VCC node and the drive circuit input node, and an inverter 79 connected between the drive circuit input node and the gate of the pull-up PMOS transistor 78. Consists of.

Further, the second word line drive circuit 76.
Is a word line driving PMOS transistor TP connected between the drive voltage source node and the word line WL, an NMOS transistor 77 connected between the word line and the VSS node, a VCC node and a drive circuit input node. And the inverter 7 connected between the drive circuit input node and the gate of the pull-up PMOS transistor 78.
9 and a noise killer NMOS transistor TN which is connected to one end of the word line WL and receives the word line voltage / WDRVnj at its gate.

The circuit of FIG. 9 is logically configured to realize the operation example shown in the timing waveform diagram of FIG. That is, if the BITAC signal is at the "L" level, one word line WL is selected in the activated n memory cell blocks in the memory cell array 1 in either the normal operation or the automatic refresh operation. .. But B
If the ITAC signal goes to "H" level and all but the lower 2 bits (j = 1, 2) of the true complementary signals (RABj, / RABj) of the internal row address signal go to "H" level, the NAND circuit 71 The selection ability of ~ 73 is lost,
The outputs of the NAND circuits 71 to 73 are in the state of being selected at the "L" level. As a result, the word line voltage WD
PMO for driving the word line that RVnj is inputting to the source
The gate potentials of the S transistors TP are all at the "L" level.

Therefore, at this time, four word lines W are provided in accordance with the states of the address bits A0R and A1R selected by the output signal of the refresh counter 4 in the CBR cycle.
When one of the L0i is selected and becomes "H" level, the word line drive circuit 7 connected corresponding to this is selected.
The word line WL is selected by 6. At this time, all n
If this memory cell block is also selected, the word lines WL will rise every four lines in the word line array of all blocks. Then, by repeating the CBR cycle, the rising word lines are exchanged, and C
If the BR cycle is repeated four times, all the word lines WL will rise.

Therefore, more word lines WL than the normal cycle rise at the same time, and the word lines WL
It is possible to efficiently apply an electric field stress to the.
In addition, since the word lines WL are erected every four lines, a high electric field is applied between the adjacent word lines WL, and more defective modes can be screened than when voltage stress is applied to all the word lines WL in terms of DC. it can.

In the AC burn-in test mode, if only the lower 3 bits of the address counter output are changed, the word lines WL rise every 8 lines in the word line array of all blocks. If only the least significant bit of the address counter output is changed, every other word line WL rises in the word line array of all blocks. FIG. 11 is a circuit diagram showing an example of the spare row decoder / word line drive circuit 13 in FIG.

Reference numeral 81 is a NOR input NMOS transistor to which an address signal to be decoded is input to the gate, each source is grounded, and each drain is correspondingly a fuse element F ... Are connected together via. The fuse element F is cut according to the address to be decoded.
Reference numeral 82 denotes a PMOS transistor for precharge, 83 ...
Is a PMOS transistor for pull-up, 84 ... Is an inverter, and 85 ... is a NAND gate.

The circuit of FIG. 11 is logically configured to realize the operation described below. That is, during normal operation (BITAC signal is at “L” level), if only the address signal input to the gate of the NOR input transistor 81 connected to the fuse element F in the cut state is at “H” level, The / RSP signal becomes "L" level and the RSP signal becomes "H" level. Then, the block selection signal R
When the synchronization signal XVLD rises from "L" level to "H" level in the block selected by SLn, /
Since the RSPn signal remains "L" level and the SWSn signal rises from "L" level to "H" level,
The spare word line SWLi (i = 0, 1) is selected according to the logic level of the address signal A0R or / A0R.

Further, when the fuse element F is not cut, an arbitrary NOR input address signal rises to the "H" level, or a NOR input transistor other than the NOR input transistor connected to the cut fuse element F is connected. When the address signal input to the gate of the input transistor 81 rises to the "H" level, the / RSP signal becomes the "H" level, the RSP signal becomes the "L" level, and the / RSPn signal rises together with the XVLD signal. The word line WL is selected as shown. By such operation,
If the BITAC signal is at "L" level, the spare word line SWLi and the word line WL cannot be selected at the same time.

However, in the AC burn-in mode, B
When the ITAC signal becomes "H" level, both the / RSP signal and the RSP signal become "H" level when the address bit A1R is "H" level.

Therefore, when the XVLD signal rises, the SWSn signal and / RSPn signal rise together, and the spare word line SWLi and the word line WL have the address bit A.
It is decoded and started up only by 0R and A1R. As a result, the normal word line WL also becomes the spare word line SWLi.
Also applies AC stress with the same duty ratio. FIG. 12 is a circuit diagram showing an example of one column of the memory cell array 1 in FIG. 1 and a part of the cell peripheral circuit.

Here, MC represents typically two of the memory cells arranged in a matrix, each of which has a source of a transfer gate MOS transistor (cell transistor) T and one end of a capacitor C of the memory cell. Are connected, and the other end of the capacitor C is connected to a capacitor wiring (eg, plate potential VPL). And
The word line WL is connected to the gates of the cell transistors T in the same row.
ni and WL (n + 1) j (representatively two are shown) are connected, and bit lines BLnk and / BLnk (representatively represent one pair) are connected to the drains of the cell transistors T in the same column. It is connected.

The sense amplifier circuit SA includes, for example, an N channel sense amplifier NSA and a P channel sense amplifier P.
A latch type circuit made of SA is used. 91 is N
Two activation control (drive) transistors for the channel sense amplifier NSA, 92 are two activation control (drive) transistors for the P-channel sense amplifier PSA,
Reference numeral 93 is an inverter, 94 is an AND gate, and 95 is a NAND gate.

The bit line transfer gate TG includes a pair of input nodes of the sense amplifier SA and a bit line pair (BL,
/ BL) and an NMOS transistor inserted between the sense amplifier SA and the transfer gate control signal φT.
And bit line pair (BL, / BL) are controlled. For simplification of display, a column selection circuit transfer controlled by a column selection line (not shown) for transmitting the information amplified by the sense amplifier circuit SA to a data line pair (not shown). The gate is omitted.

Bit line precharge / equalize circuit 1
1 is controlled by the bit line equalize signal EQL,
Bit line pair (BL, / BL) on both sides of the sense amplifier SA
Is used for precharging the bit line to the bit line precharge potential VBL and at the same potential.

The / CENB signal generation circuit 96 operates the sense amplifier circuit SA and the circuit on the output side thereof (in the case of a read operation, for example, the operation of fetching the column address and raising the column selection line, and connecting to the data line pair). By activating a buffer circuit (not shown) that is provided, the information on the data line pair is amplified and transferred to the output buffer circuit (not shown), and output to the outside of the chip)
To generate a / CENB signal.

The circuit of FIG. 12 is logically configured so as to realize the operation example described below. That is, BIT
In a normal operation in which the AC signal is at “L” level, if the sense amplifier activation signal SEN rises, the drive transistor 91 for the N-channel sense amplifier NSA is in an optimized state (in this example, two drive transistors 91 The N-channel sense amplifier NSA is activated by the total driving force). Next, if the sense amplifier activation signal SEP rises, the P-channel sense amplifier PSA drive transistor 92 in the optimized state (in this example, the total drive power of the two drive transistors 92) is sensed. The amplifier PSA is activated. After that, if the CREF signal is at the "L" level, the / CENB signal shifts to the "L" level and the column system operation is started. In the CBR cycle, the CREF signal becomes "H" level,
The / CENB signal is kept at "H" level to prohibit the column system operation.

When the BITAC signal becomes "H" level,
Both the N-channel sense amplifier NSA and the P-channel sense amplifier PSA are activated with limited drive power (in this example, the drive power of one drive transistor 91 and the drive power of one drive transistor 92 corresponding to each other). Controlled to be done. As a result, even if the number of sense amplifier circuits SA operating at the same time is large and the respective currents flow at the same time, generation of large noise is prevented. Furthermore, if the BITAC signal is at "H" level,
Even in the CBR cycle, the / CENB signal is kept at the "L" level, so that the column operation is not prohibited. FIG. 13 is a circuit diagram showing an example of the φT / EQL signal generating circuit for generating the φT / EQL signal in FIG.

Here, 100 and 101 are differential circuits and 10
2 to 108 are inverters, and 109 to 111 are NAND gates. WLDOWN is a signal which is at "H" level until the word line WL rises.

The circuit of FIG. 13 is logically configured so as to realize the operation example described below. That is, BIT
In the normal operation in which the AC signal is at "L" level, / RA is selected in the block selected by the block selection signal RSLn.
It goes to "L" level immediately after the S signal / in synchronization with the RSTR signal (the WLDOWN signal is at "H" level until the word line WL rises, so irrelevant in this case), BLH
The Z signal becomes "L" level, the equalizing operation of the bit line pair (BL, / BL) of the selected memory cell block is stopped, and the rising of the word line WL is waited.

When the BITAC signal becomes "H" level,
The φT signal is forcibly clamped to the “H” level. Because, when the shared sense amplifier system is adopted, if the adjacent memory cell blocks are activated at the same time, the φT signal turns off in both blocks.
This is because it is necessary to prevent the sense amplifier circuit SA from being unable to amplify data.

When the shared sense amplifier system is adopted, the memory cell blocks adjacent to each other are located immediately above the address counters for the address bits A0 and A1 so that the memory cell blocks adjacent to each other are not activated at the same time. Addresses may be exchanged so as to arrange a row address counter for selecting, and all the word lines WL may be activated with one set of eight CBR cycles. In this case, it is not necessary to forcibly clamp the φT signal to the high level even in the AC burn-in test mode.

Of course, in the method (not the shared sense amplifier method) in which the dedicated sense amplifier circuit SA is provided in each memory cell block, the above consideration is not necessary when the φT signal itself is not used. FIG. 14 shows
FIG. 2 is a circuit diagram showing an example of a word line drive voltage source 7 (VPP generating circuit) and a VPP-VCC short circuit 14 in FIG. 1.

Here, 120 is a booster circuit for VPP generation,
121 is an inverter circuit, 122 is a NOR gate, CP is a capacitive element, D ... is a diode, R1 and R2 are resistive elements,
123 is a PMOS transistor, 124 is a differential circuit, 1
Reference numeral 25 is a comparison circuit.

The circuit of FIG. 14 is configured so as to realize the operation example described below. That is, BITAC
During normal operation when the signal is at "L" level, VPP line -V
The PMOS transistor 123 between the CC lines is off, and the booster circuit 120 between the VPP line and the VCC line operates to generate the word line driving potential VPP in the chip up to the limit potential corresponding to the reference potential Vref1. When the BITAC signal goes to the "H" level, the booster circuit 120 is deactivated, the VPP-VCC short circuit 14 is activated instead, and the word line drive potential VPP is changed to the external power supply potential VCC.
Is equal to

Next, as a second embodiment of the DRAM of the present invention, a power supply voltage VCC supplied from the outside of the chip is supplied as a word line driving voltage, and the above-mentioned power supply voltage VCC is stepped down on the chip to generate an internal step-down voltage VDD. A case will be described where a power supply voltage down circuit for supplying power to the memory cell peripheral circuit is used.

In the DRAM of the second embodiment, as shown in FIG. 15, a VCC-VDD short circuit 131 for short-circuiting the output node of the power voltage step-down circuit 130 to an external power supply terminal in the AC burn-in mode test is provided. It is desirable to provide it.

As a result, when the AC burn-in mode is set, not only the transfer gate of the memory cell but also
It is possible to accelerate the voltage stress by making the stress of the insulating film of the transistor of the other circuit higher than the value of the normal use. FIG. 15 is a circuit diagram showing an example of the power supply step-down circuit 130 and the VCC-VDD short circuit 131.
Here, 132 is an inverter, and 133 and 134 are PMOs.
An S transistor, 135 is a comparison circuit, and R3 and R4 are resistance elements.

FIG. 16 shows the DRA of the present invention as described above.
FIG. 7 is a timing waveform chart showing an operation example of a setting cycle of an AC burn-in test mode of a time saving method for M, an AC stress test cycle, and a withdrawal cycle from the test. The time saving AC burn-in test mode is executed according to the following steps. First step: The same data is written in the memory cell connected to the same sense amplifier circuit SA via the bit line BL in the normal write mode.

Second step: The WCBR cycle is executed, and the A0R and A1R bits of the address signal are set to "L" level. As a result, an AC burn-in test mode signal is generated.

Third step: The following settings are made. (CT
j, / CTj) (other than j = 0, 1) is set to the “L” level. The drive power of the sense amplifier circuit SA is limited. VPP =
Set to VCC. Set VDD = VCC. (When using a power down circuit). However, in the case of the shared sense amplifier system, the (CTj, / CTj) signals other than j = 0, 1, 2 are set to the “L” level. The φT signal is set to "H" level. Fourth step: Secure a sufficient time tRP (up to several microseconds) to complete the setting of VPP and VDD in the third step. Fifth step: Vcc potential is raised to a high voltage for burn-in. Sixth step: With four or eight CBR cycles as one set, a plurality of sets of AC stress are applied to the word lines WL for a time required. 7th step: Input the clock of ROR cycle, A
Get out of C burn-in mode.

In the above embodiment, the voltage stress test during burn-in has been described as an example, but it goes without saying that the present invention is also effective when the voltage stress test is performed regardless of temperature acceleration.

[0087]

As described above, according to the semiconductor memory device of the present invention, in the case of setting the AC voltage stress test mode in which a high voltage is applied to a word line in a wafer state or a state after being sealed in a package, a high duty ratio is set. To
It does not require a pad dedicated to the voltage stress test, eliminates the circuits other than those required for the normal operation mode as much as possible, and suppresses the increase of the chip area. Any unpredictable failure mode that may occur during normal operation, such as a decrease in breakdown voltage between adjacent bit lines or between adjacent bit lines, can be screened at the same time, and the entire chip can be screened in a form close to actual use conditions in a short time.

[Brief description of drawings]

FIG. 1 is a block diagram showing a part of a DRAM equipped with a time saving AC burn-in test mode according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a part of an address buffer circuit for row address in FIG.

FIG. 3 is a refresh address counter 1 shown in FIG.
FIG. 3 is a circuit diagram showing an example of a part of a stage and a burn-in test mode control circuit taken out.

4 is a circuit diagram showing an example of a part of the address switching circuit in FIG.

5 is a timing waveform chart showing an operation example of the circuits of FIGS. 2 to 4 during a normal operation.

FIG. 6 is a timing waveform chart showing an operation example of a refresh operation of the circuits of FIGS. 2 to 4.

FIG. 7 is a timing waveform chart showing an operation example of the circuit of FIGS. 2 to 4 in the AC burn-in test mode of the time saving method.

8 is a diagram showing an example of a burn-in test mode signal generation circuit and an example of operation waveforms in FIG.

FIG. 9 is a circuit diagram showing an example of a row decoder circuit and a part of a word line driving circuit shown in FIG.

10 is a waveform chart showing an example of operation waveforms of the circuit of FIG.

11 is a circuit diagram showing an example of a spare row decoder / word line drive circuit in FIG.

FIG. 12 is a circuit diagram showing an example in which one column of the memory cell array and a part of a cell peripheral circuit in FIG. 1 are taken out.

13 is a circuit diagram showing an example of a φT / EQL signal generation circuit for generating the φT / EQL signal in FIG.

14 is a word line drive voltage source and VPP-V in FIG.
A circuit diagram showing an example of a CC short circuit.

FIG. 15 is a circuit diagram showing an example of a power supply step-down circuit and a VCC-VDD short circuit provided in a DRAM according to a second embodiment of the present invention.

FIG. 16 is a timing diagram showing a setting cycle, an AC stress test cycle, and a test exit cycle of the time-saving AC burn-in test mode for the DRAM of the present invention.

FIG. 17: A of the currently proposed DRAM time saving system
FIG. 6 is a circuit diagram showing an example of a circuit for realizing a C burn-in test mode.

FIG. 18: A of the currently proposed DRAM time saving system
FIG. 8 is a circuit diagram showing another circuit example for realizing the C burn-in test mode.

FIG. 19: A of the currently proposed DRAM time saving system
FIG. 6 is a circuit diagram showing still another circuit example for realizing the C burn-in test mode.

[Explanation of symbols]

1 ... Memory cell array, 2 (2a, 2b) ... External terminal,
3 ... Address buffer circuit, 4 ... Refresh address counter, 5 ... Address switching circuit, 6 ... Row decoder circuit (word line selection circuit), 7 ... Word line driving voltage source, 8 ... Word line driving circuit, 9 ... Column Decoder circuit,
10 ... DRAM circuit, 11 ... Bit line precharge / equalize circuit, 12 ... Bit line precharge potential (VB
L) generation circuit, 13 ... spare row decoder / word line drive circuit, 14 ... VPP-VCC short circuit, 20 ... burn-in test mode signal generation circuit, 21 ... burn-in test mode control circuit, 36 ... burn-in test mode control circuit Input NOR gate, 120 ... Step-up circuit, 130 ... Power supply step-down circuit, 131 ... VCC-VDD short circuit, MC ... Memory cell, T ... Cell transistor, WL0, WL ... Word line,
SWL ... Spare word line, BL, / BL ... Bit line, TP
... word line driving PMOS transistor, SA ... sense amplifier circuit, CS ... column selection circuit, TG ... bit line transfer gate, BITAC ... burn-in test mode signal.

Claims (9)

[Claims] 1. A DRAM circuit, and a voltage stress test mode signal generation circuit for generating a voltage stress test mode signal based on a predetermined signal input from a part of external terminals used during normal operation of the DRAM circuit. Receiving a test mode signal from the voltage stress test mode signal generation circuit, and controlling so that only upper bits of a certain bit or more of the output signal of the refresh address counter of the DRAM circuit are fixed to the same level,
A semiconductor memory device, comprising: a control circuit for controlling a lower bit less than the specific bit so that the lower bit operates normally. 2. The semiconductor memory device according to claim 1, wherein the DRAM circuit is connected to a memory cell array in which a plurality of dynamic memory cells are arranged in a matrix and memory cells in the same row of the memory cell array. A word line, a bit line connected to a memory cell in the same column of the memory cell array, and an ON / OFF control connected to the bit line by a bit line equalize signal to precharge the bit line to a bit line precharge potential. A bit line precharge circuit for charging, an external terminal to which a power supply voltage, an address signal and various control signals are input from the outside, an address buffer circuit for amplifying an external address signal input from a part of the external terminal, A reference for generating a refresh address signal for the refresh operation of the memory cell. Address counter for switching, an address switching circuit for selecting either the output signal of the refresh address counter or the row address signal output of the address buffer circuit, and the internal row address signal output from the address switching circuit. A row decoder circuit having a word line selecting function for selecting an arbitrary row by means of a word line driving circuit, and at least one word line driving MOS transistor connected between the word line driving voltage source and the word line. A semiconductor memory device comprising: a word line drive circuit that drives the word line according to an output signal of a decoder circuit; and a sense amplifier circuit that detects information read from the memory cell to the bit line. 3. The semiconductor memory device according to claim 2, wherein the DRAM circuit is a spare word line for defect repair,
A spare row decoder / word line drive circuit is provided, and the control circuit further controls so that the spare word line is selectively driven at the same duty ratio as a normal word line in a voltage stress test. Semiconductor memory device. 4. The semiconductor memory device according to claim 3, wherein the control circuit further controls so as to limit the capability of the drive transistor for the sense amplifier circuit. 5. The bit line transfer according to claim 4, wherein the DRAM circuit is inserted between an input node of the sense amplifier circuit and the bit line and is on / off controlled by a control signal. A semiconductor memory device having a gate, wherein the control circuit further controls the bit line transfer gate to an ON state in a voltage stress test. 6. The semiconductor memory device according to claim 2, wherein the word line driving voltage source is a power supply external to the semiconductor chip, or a power supply voltage supplied from outside the semiconductor chip. Is a booster circuit for boosting a voltage on a chip to generate a word line driving voltage, and the word line driving voltage is supplied as a power source of the word line driving circuit. 7. The semiconductor memory device according to claim 6, wherein the control circuit further controls the output node of the booster circuit to be connected to an external power supply terminal during a voltage stress test. apparatus. 8. The semiconductor memory device according to claim 2, wherein the DRAM circuit further lowers a power supply voltage applied from outside the semiconductor chip on the chip to provide a memory cell peripheral circuit. A semiconductor memory device having a power supply voltage down circuit for supplying power, wherein the control circuit further controls to connect an output node of the power supply voltage down circuit to an external power supply terminal in a voltage stress test. 9. The semiconductor memory device according to claim 2, wherein the dynamic memory cell has a transfer gate composed of an N-channel MOS transistor, The driving MOS transistor is
A semiconductor memory device characterized by being a P-channel MOS transistor.