JP4558186B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a test mode in which a plurality of word lines are boosted.
[0002]
[Prior art]
In recent years, semiconductor devices in which a large number of transistors are integrated are used in various electrical products such as workstations and personal computers. In the manufacture of a semiconductor device, burn-in for performing an operation test by applying a higher voltage to the power supply of the semiconductor device in a high temperature atmosphere than usual is required for a reliability test and screening. A defective semiconductor device can be screened by accelerating the deterioration of a defective portion latent in an insulating film or the like contained in the semiconductor device due to stress due to burn-in. As this burn-in, there are known a normal burn-in performed after assembling semiconductor chips and a wafer level burn-in (WBI) performed in the state of a wafer including a plurality of semiconductor chips before assembly.
[0003]
The wafer level burn-in is described in, for example, the document T. Furuyama et al., “Wafer Burn-in (WBI) Technology for RAM's”, 1993 IEDM Tech. Digest, pp. 639-642. Wafer level burn-in has the following advantages over normal burn-in. First, the semiconductor chip is not enclosed in a package or mold. Therefore, burn-in can be performed at a temperature higher than the heat resistance of the package or mold. In addition, since the stress electric field can be set high, the burn-in time is shortened. Second, it is performed before a repair test for replacing a defect with a spare by laser trimming or the like. Therefore, it becomes possible to relieve defects that occur after burn-in by a subsequent repair test. Third, it is possible to know the position of the semiconductor chip where the defect on the wafer is detected. Therefore, this defect information can be easily fed back to the production line for improvement.
[0004]
DRAM is used as the main memory of personal computers. This DRAM includes a plurality of memory cells arranged in a plurality of rows and a plurality of columns. Each memory cell stores 1-bit information of “0” or “1”. The memory cell includes a memory cell transistor and a memory cell capacitor. One electrode of the memory cell capacitor is formed of a cell plate. A plurality of word lines are arranged corresponding to the plurality of rows of memory cells, respectively. Bit line pairs are arranged corresponding to the plurality of columns of memory cells. The gate of the memory cell transistor is constituted by a corresponding word line. The memory cell transistor is connected between the corresponding bit line and the other electrode of the memory cell capacitor.
[0005]
In wafer level burn-in, all word lines are selected simultaneously, or every other word line is simultaneously selected in a stripe shape, and then a voltage is applied to the bit lines and the cell plate from the outside. As a result, a stress voltage is applied to the gate oxide film of the memory cell transistor, the insulating film of the memory cell capacitor, the insulating film between adjacent word lines, the insulating film between adjacent memory cells, and the like.
[0006]
[Problems to be solved by the invention]
FIG. 8 is a circuit diagram showing a part of a DRAM disclosed in, for example, US Pat. No. 5,513,142. In the configuration shown in FIG. 8, the boost signal driver RXD sends the boost signal RX to the boost potential V higher than the power supply potential._PPDrive to. This boosted potential V_PPIs set to a burn-in potential higher than that during normal operation during wafer level burn-in. At the time of wafer level burn-in, 128 word lines are simultaneously driven via the P-channel transistor P1 included in each word driver DRV.
[0007]
However, the drive capability of the boost signal driver RXD is that one word line can be driven from the ground potential GND to the boost potential V at the desired speed._PPDesigned to drive into. Therefore, if 128 word lines are driven simultaneously, the total capacity load of these word lines is too large compared to the drive capability of the boost signal driver RXD, and the charging current to the word lines is large. Therefore, boosted potential V_PPIn combination with the voltage drop in the power supply wiring resistance for transmitting the voltage, the boost signal RX rises slowly and exceeds the logic threshold value of the inverter INV. As a result, the output signal ZRX of the inverter INV slowly decreases, so that the N-channel transistor N2 is slowly turned off. In the meantime, part of the electric charge charged to the word line WL from the boost signal RX through the P-channel transistor P1 passes through the N-channel transistor N2 to the ground potential GND. Therefore, boosted potential V_PPTemporarily rises to an intermediate potential between the desired potential and the ground potential.
[0008]
The logical threshold value of the inverter INV may become higher than the design value due to the deviation of the threshold value of the N-channel transistor and / or the P-channel transistor due to variations in the manufacturing process. In the configuration shown in FIG. 8, the boosted potential V_PPWhen the intermediate potential that temporarily stops becomes lower than the logical threshold value of the highly shifted inverter INV, the potential of the output signal ZRX of the inverter INV may be fixed at a high level. In such a case, the N-channel transistor N2 of the word driver DRV remains on. Therefore, most of the charging current from the boost signal RX to the word line WL is lost to the ground potential GND. As a result, the boost signal RX cannot exceed the threshold value of the inverter INV and saturates at a potential near the logic threshold value of the inverter INV.
[0009]
As described above, the conventional configuration has a problem that the potential of the word line WL does not rise to the burn-in potential during wafer burn-in.
[0010]
An object of the present invention is to obtain a semiconductor device that reliably drives a word line to a burn-in potential during wafer level burn-in.
[0011]
[Means for Solving the Problems]
  A semiconductor device according to first and second inventions includes a boost signal generator for generating a boost signal, a drive signal generator for receiving a boost signal and a wafer burn-in signal, and outputting a drive signal, a plurality of word lines, And a plurality of word drivers connected to each of the plurality of word lines and the output of the boost signal generator.
  Each of the plurality of word drivers is provided between a first drive transistor for transmitting a boost signal to a corresponding word line according to a word line selection signal and a node to which a corresponding low level potential is applied to the word line and the word line. And has a gate connected to the drive signalThe low level potential is selectively transmitted to the corresponding word line according to the potential of the gate, and the gate potential isAnd a second drive transistor that is turned off at the low level.
  The drive signal generator outputs a drive signal that becomes a low level potential as the boost signal rises toward a boost potential that is higher than the power supply potential, and outputs the drive signal in response to the boost signal when the wafer burn-in signal is activated. The potential is low level.
[0012]
  In the semiconductor device according to the first inventionDrive signal generatorIsAn N-channel transistor having a gate for receiving a boosted signal, connected between an output node for outputting a drive signal and a node to which a low level potential is applied, and an output node and a node to which a high level potential is applied Includes a cutoff transistor and a P-channel transistor connected in series betweenMuCut-off transistor is wafer burn-in signalActivationThe P-channel transistor has a gate for receiving a boost signal.The
[0013]
  Preferably, Cutoff transistorIsHas a thinner gate insulating film than P-channel transistorsThe
[0014]
  In the semiconductor device according to the second inventionDrive signal generatorIsA first N-channel transistor having a gate for receiving a boosted signal, connected between an output node for outputting a drive signal and a node to which a low-level potential is applied; an output node and a node to which a high-level potential is applied And a P-channel transistor having a gate for receiving a boost signal, and a first N-channel transistor connected in parallel between the output node and a node to which a low level potential is applied, and a wafer burn-in signalActivationIncluding a second N-channel transistor that is turned on in response toMu
[0015]
  PreferablyThe second N-channel transistor has a thinner gate insulating film than the first N-channel transistorYouThe
[0016]
  3rd and 4thA semiconductor device according to the invention includes a plurality of main word lines extending in a first direction,A plurality of bit line pairs extending along a second direction intersecting the first direction;Arranged along the first directionA sense amplifier band including a plurality of sense amplifiers respectively connected to a plurality of bit line pairs, a plurality of sub word lines extending along the first direction and arranged in a predetermined number corresponding to each main word line, and It includes a plurality of sub word drivers arranged in a direction crossing the sense amplifier band and arranged corresponding to the plurality of sub word lines along the second direction. Each subword driverA gate connected to a corresponding one of a plurality of main word lines;According to the gate potentialA first drive transistor for transmitting one of a plurality of boost signals to a corresponding sub word line; a corresponding sub word line;subA gate connected to a node to which a low-level potential for the word line is applied, and receiving one of a plurality of drive signals corresponding to a plurality of boost signals, respectively.And a second drive transistor that transmits the low level potential of the node to the corresponding sub-word line in accordance with the gate potential and is turned off when the gate potential is at the low level.
  The semiconductor device according to the third and fourth inventions further includesA sub memory block including a plurality of memory cells arranged corresponding to intersections of a plurality of bit line pairs and a plurality of sub word lines,and,Located at the intersection of the sense amplifier band and subword driver bandA boost driver. This boost driver receives a boost signal generator for generating a plurality of boost signals, a plurality of boost signals and a wafer burn-in signal, and as the applied boost signal rises toward a boost potential higher than the power supply potential. A drive signal generator for setting a corresponding drive signal to a low level potential for the drive signal and setting the corresponding drive signal to a low level potential for the drive signal in response to activation of a given wafer burn-in signal. .
[0017]
  In the semiconductor device according to the third invention,The drive signal generatorFor eachConnected between an output node for outputting a drive signal and a node to which a low-level potential for the drive signal is applied;CorrespondingAn N-channel transistor having a gate for receiving a boost signal; andTheIncludes a cutoff transistor and a P-channel transistor connected in series between the output node and a node to which a high level potential is applied.MuCut-off transistor is wafer burn-in signalActivationIs turned off in response to the P channel transistorCorrespondingHas a gate to receive a boost signalThe
[0018]
  Preferably, Cutoff transistorIsHas a thinner gate insulating film than P-channel transistorsThe
[0019]
  In the semiconductor device according to the fourth aspect of the present invention, the drive signal generator is connected between an output node for outputting a corresponding drive signal and a node to which a low-level potential for the drive signal is applied. A first N-channel transistor having a gate for receiving a signal; a P-channel transistor having a gate for receiving a corresponding boosted signal, connected between the output node and a node to which a high-level potential is applied; A wafer burn-in signal applied in parallel with the first N-channel transistor between a node to which a low-level potential for the drive signal is appliedActivationIncludes a second N-channel transistor that is turned on in response to.
[0020]
  Preferably, Second N-channel transistorIsHas a thinner gate insulating film than the first N-channel transistor.Do.Also, Cutoff transistorIsFrom P-channel transistorBecome.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
Hereinafter, a DRAM (Dynamic Random Access Memory) according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a schematic block diagram of the DRAM 100. Referring to FIG. 1, DRAM 100 includes a command decoder 110. The command decoder 110 receives various control signals (for example, a clock enable signal CKE, a chip select signal / CS, a row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal / WE, and a data mask signal DM). ) Is latched in synchronization with a clock signal CLK applied from the outside, and these control signals are decoded. An operation command is designated by a combination of logics of these control signals. Commands include a bank activation command, a read command, a write command, a precharge command, a CBR refresh command, a self-refresh command, and the like. The command decoder 110 decodes a given command and outputs a plurality of types of internal control signals for controlling the operation of the DRAM 100 in response to the command.
[0022]
The DRAM 100 also includes a row address buffer and a refresh counter 120. The row address buffer and refresh counter 120 has an address signal A including a plurality of bits given from the outside.₀-A₁₂And bank address signal BA including multiple bits₀-BA₁In response, a row address signal and an internal bank address signal are output. When the internal control signal from the command decoder 110 indicates that a bank activation command has been given to the command decoder 110, the row address buffer and refresh counter 120 receives an address signal A given from the outside.₀-A₁₂And bank address signal BA₀-BA₁Are supplied as a row address signal and an internal bank address signal.
[0023]
The row address buffer and refresh counter 120 also provides an externally applied address when an internal control signal from the command decoder 110 indicates that a refresh command (for example, a CBR refresh command or a self-refresh command) is applied to the command decoder 110. Signal A₀-A₁₂And bank address signal BA₀-BA₁The row address signal and the internal bank address signal are generated and supplied independently of the above.
[0024]
DRAM 100 further includes a column address buffer and a latency / burst controller 130. The column address buffer and latency / burst controller 130 is provided with an address signal A applied from the outside.₀-A₁₂And bank address signal BA₀-BA₁In response, a column address signal and an internal bank address signal are output. When the internal control signal from the command decoder 110 indicates that a read command or a write command is given to the command decoder 110, the column address buffer and latency / burst controller 130 receives an address signal A given from the outside.₀-A₁₂And bank address signal BA₀-BA₁Are supplied as a column address signal and an internal bank address signal.
[0025]
The column address buffer and latency / burst controller 130 also receives an externally applied address signal A when the internal control signal from the command decoder 110 indicates that the command register 110 has been given a mode register set command.₀-A₁₂Predetermined bits (e.g. A_Four-A₆) / CAS latency is set in response to other predetermined bits (e.g. A₀-A₂) To set the burst length.
[0026]
The DRAM 100 further includes a plurality of banks 140 called banks A, B, C, and D. Each bank has a memory array 141 in which a plurality of memory cells are arranged in a plurality of rows and a plurality of columns, a row decoder 142 for selecting a row of the memory array 141, and a memory cell data appearing in a column of the memory array 141 for detecting and amplifying the memory cell data. Sense amplifier group 143 and column decoder 144 for selecting a column of memory array 141. Each bank 140 is configured such that a memory cell having an address independent of the address of a memory cell selected in another bank can be selected. That is, any memory cell in each bank can be selected regardless of which memory cell is selected in another bank.
[0027]
Row decoder 142 decodes the row address signal and internal bank address signal from row address buffer and refresh counter 120. Then, according to the internal bank address signal (therefore, the bank address signal BA₀-BA₁According to the row address signal of bank 140 (and thus address signal A)₀-A₁₂Select memory cells in a row.
[0028]
The sense amplifier group 143 detects and amplifies data in the memory cells in the row selected by the row decoder 142, which appear in the column of the memory array 141. Column decoder 144 decodes the column address signal and internal bank address signal from column address buffer and latency / burst controller 130. Of the data amplified by the sense amplifier group 143, the data corresponds to the internal bank address signal (therefore, the bank address signal BA₀-BA₁Depending on the column address signal of bank 140 (and therefore address signal A)₀-A₁₂Select the data in the column.
[0029]
Furthermore, the DRAM 100 includes a data controller and an input / output buffer 150. The data controller and I / O buffer 150 is synchronized with the clock signal CLK in response to the internal control signal from the command decoder 110 and the / CAS latency and burst length set in the column address buffer and latency / burst controller 130. The data DQ is output from the memory array 141 to the outside. The data controller / input / output buffer 150 is externally synchronized with the clock signal CLK in response to the internal control signal from the command decoder 110 and the burst length set in the column address buffer and latency / burst controller 130. The given data DQ is supplied to the memory array 141.
[0030]
When the internal control signal from the command decoder 110 indicates that a read command is given to the command decoder 110, the data controller and input / output buffer 150 receives the read command and receives a clock signal corresponding to the value of / CAS latency. Output of the read data DQ is started from the time when the CLK cycle elapses. The read data is output serially to each of the DQ pins having a plurality (for example, four) of burst length values. The data controller and input / output buffer 150 can serially output data from the memory array 141 selected by the column decoder 144 to each DQ pin.
[0031]
In addition, the data controller and input / output buffer 150, when the internal control signal from the command decoder 110 indicates that a write command has been given to the command decoder 110, has a burst length that is serially applied to each DQ pin from the outside. Write data is sequentially taken into the inside in synchronization with the clock signal CLK, and the write data is given to the column of the memory array selected by the column decoder 144. Further, it is possible to prevent a part of the write data serially given by the data mask signal DM from being taken in.
[0032]
DRAM 100 also has a power supply potential V_CCBoosted potential V_PP, Power supply potential V_CCAnd ground potential V_SSIntermediate potential (V_CC+ V_SS) / 2 bit line precharge potential V_BLAnd cell plate potential V_CPIs provided with an internal potential generating circuit group 160. DRAM 100 further includes a pad 161. Pad 161 is boosted potential V_PPIs connected to the power supply wiring that transmits voltage, and the burn-in potential is applied to the pad 161 during wafer burn-in, so that the boosted potential V_PPCan be set to a higher burn-in potential than during normal operation.
[0033]
FIG. 2 is a schematic diagram showing the configuration of the memory array 141 and the sense amplifier group 143. Referring to FIG. 2, memory array 141 includes a plurality of memory blocks MB.₁-MB_nincluding. Memory block MB₁-MB_nEach include a plurality of bit line pairs 141a. The sense amplifier group 143 includes a plurality of sense amplifier bands SB.₁-SB_{n + 1}including. Sense amplifier band SB₁-SB_{n + 1}Each includes a plurality of sense amplifiers 143a. The sense amplifier band located between the memory blocks is provided in common to the memory blocks on both sides thereof. In other words, this DRAM employs a so-called shared sense amplifier configuration.
[0034]
Bit line pair 141a extends along a column of memory cells. Each of bit line pair 141a is arranged corresponding to a column of memory cells of a corresponding memory block. Sense amplifier band SB₁-SB_{n + 1}The sense amplifiers 143a included in each of the memory cells are arranged along a row of memory cells.
[0035]
Figure 3 shows memory block MB₁-MB_nOne of the memory blocks MB_i2 is a schematic diagram showing the configuration of a row decoder 142. FIG. Referring to FIG. 3, a plurality (128 in this embodiment) of main word lines 141b are connected to memory block MB._iPlaced on top. Each main word line 141b extends along a row of memory cells. Row decoder 142 is memory block MB_iMain row decoder MRD provided corresponding to_iincluding.
[0036]
Main row decoder MRD_iIn normal operation, when a corresponding memory block is selected, one of the plurality of main word lines 141b is set to a selection level (low level) according to an address signal. Further, the remaining main word line 141b is set to the non-selected level (boosted potential V_PP). On the other hand, the main row decoder MRD_iDuring wafer level burn-in, all the main word lines 141b are set to the low level of the selected level in response to the wafer burn-in signal WBI becoming high level indicating wafer level burn-in. This wafer burn-in signal WBI is generated by the command decoder 110 shown in FIG. When wafer level burn-in is designated by a combination of an external control signal and an external address signal, this wafer burn-in signal WBI goes high.
[0037]
The row decoder 142 also includes a plurality of subword driver bands SWDB.₁-SWDB_Fiveincluding. Memory block MB_iIs the subword driver band SWDB₂-SWDB_FourMultiple sub memory blocks by SMB₁-SMB_FourIt is divided into. Sub memory block SMB₁-SMB_FourEach includes a plurality of sub-word lines 141c. Sub word line 141c is arranged corresponding to the row of memory cells in the corresponding sub memory block. Sub-word line 141c extends along the row of memory cells. Subword driver band SWDB₁-SWDB_FiveEach includes a plurality of sub-word drivers 142a disposed along the columns of memory cells. The sub word driver 142a is connected to the sub word line 141c.
[0038]
Sub memory block SMB₁-SMB_FourFocusing on one of them, four adjacent sub word lines 141c correspond to one main word line 141b. The sub word drivers 142a connected to the four sub word lines 141c are connected to the corresponding main word line 141b in common. At the same time, each of the sub word drivers 142a includes a plurality of boost signals BT for selecting any of the four adjacent sub word lines 141c.₀ ⁺-BT_Three ⁺Receive one of the correspondence. Here, the + suffix in the upper right indicates that the high level is the power supply potential V_CCHigher boost potential V_PPIndicates that In each sub word driver 142a, the potential of the corresponding main word line 141b becomes the low level of the selected level, and the corresponding boosted signal has the boosted potential V of the selected level._PPWhen this boosted potential V_PPIs transmitted to the corresponding sub-word line 141c.
[0039]
Row decoder 142 further includes a sub-row decoder SRD. Sub-row decoder SRD has multiple memory blocks MB₁-MB_nAre provided for each bank 140 in common. The sub-row decoder SRD is activated in accordance with the address signal when the corresponding bank 140 is activated during normal operation.₀ ⁺-/ X_Three ⁺One of them is set to the low level of the selection level. In this embodiment, the sub-row decoder SRD performs sub-decode signal / X according to the lower 2 bits of the row address signal.₀ ⁺-/ X_Three ⁺One of them is set to the low level of the selected level, and the rest is the boosted potential V of the non-selected level_PPAnd
[0040]
The sub-row decoder SRD responds to the wafer burn-in signals WBIE and WBIO during wafer level burn-in, and generates a sub-decode signal / X₀ ⁺-/ X_Three ⁺Even number / X₀ ⁺And / X₂ ⁺Only odd number / X₁ ⁺And / X_Three ⁺Only or both / X₀ ⁺-/ X_Three ⁺Is the low level of the selection level. More specifically, when the wafer burn-in signal WBIE is at a high level and WBIO is at a low level, the sub-row decoder SRD has a sub-decode signal / X₀ ⁺-/ X_Three ⁺Even number / X₀ ⁺And / X₂ ⁺Only low level. When the wafer burn-in signal WBIE is low and WBIO is high, the sub-row decoder SRD outputs the sub-decode signal / X₀ ⁺-/ X_Three ⁺Odd number / X₁ ⁺And / X_Three ⁺Only low level. In addition, when both the wafer burn-in signals WBIE and WBIO are at the high level, the sub row decoder SRD outputs the sub decode signal / X.₀ ⁺-/ X_Three ⁺Are all low level.
[0041]
Wafer burn-in signals WBIE and WBIO are generated by command decoder 110 shown in FIG. Wafer burn-in signals WBIE and WBIO are controlled by a combination of external control signals and external address signals. When at least one of the wafer burn-in signals WBIE and WBIO is at a high level, the wafer burn-in signal WBI is at a high level. Wafer burn-in signals WBIE and WBIO are signals for simultaneously selecting even-numbered subword lines and odd-numbered subword lines, respectively. Therefore, when only even-numbered sub-word lines are simultaneously selected during wafer level burn-in, the wafer burn-in signals WBI and WBIE are in the active high level and WBIO is in the inactive low level. When only odd-numbered sub word lines are simultaneously selected, wafer burn-in signals WBI and WBIO are in the active high level and WBIE is in the inactive low level. Further, when all sub-word lines are selected simultaneously, wafer burn-in signals WBI, WBIE and WBIO are all in an active high level. During normal operation, the wafer burn-in signals WBI, WBIE and WBIO are all inactive and at a low level.
[0042]
Subword driver band SWDB₁-SWDB_FiveSense amplifier band SB_{i + 1}And intersect so as to form an intersection region CR. Row decoder 142 further includes a boost driver 142b disposed in intersection region CR.
[0043]
FIG. 4 is a specific circuit diagram of the sub word driver 142a. Referring to FIG. 4, subword driver 142a includes a P-channel drive transistor 142aa. Drive transistor 142aa has a gate connected to a corresponding one of a plurality of main word lines 141b. The gate of drive transistor 142aa is a signal / MWL transmitted by corresponding main word line 141b._mReceive. The source of the drive transistor 142aa is a plurality of boost signals BT₀ ⁺-BT_Three ⁺One of the corresponding BT_k ⁺Receive. The drain of drive transistor 142aa is connected to sub word line 141c. In addition, the back gate of the drive transistor 142aa has a boosted potential V_PPIs given. Drive transistor 142aa receives signal / MWL transmitted through corresponding main word line 141b._mIs low, the corresponding boost signal BT_k ⁺Is transmitted to the corresponding sub-word line 141c.
[0044]
Sub-word driver 142a also includes an N-channel drive transistor 142ac connected between sub-word line 141c and node 142ab to which a low-level potential for the word line is applied. The gate of drive transistor 142ac is connected to the corresponding main word line 141b, and the signal / MWL_mReceive. In this embodiment, the node 142ab has a ground potential V_SSHowever, in order to suppress the subthreshold leakage current of the memory cell, a negative potential lower than the ground potential may be applied.
[0045]
Sub word driver 142a further includes an N channel drive transistor 142ad connected between corresponding sub word line 141c and node 142ab. The gate of the drive transistor 142ad is a plurality of boost signals BT₀ ⁺-BT_Three ⁺Multiple drive signals / DV corresponding to each₀-/ DV_ThreeOne of the corresponding / DV_kReceive. This drive signal / DV_kIs the corresponding boost signal BT_k ⁺Is the boosted potential V_PPAs the voltage rises toward, the drive signal becomes a low level potential. In this embodiment, the low level potential for the drive signal is the same as the ground level V as the low level potential for the word line._SSIt is. However, the low level potential for the drive signal may be made lower than the low level potential for the word line so as to be different from each other.
[0046]
Drive signal / DV₀-/ DV_ThreeAre driven to a low level for a drive signal in response to a wafer burn-in signal WBIE or WBIO. More specifically, when the wafer burn-in signal WBIE is at high level, the even drive signal / DV₀And / DV₂Is at a low level. When the wafer burn-in signal WBIO is at high level, the odd numbered drive signal / DV₁And / DV_ThreeIs at a low level.
[0047]
FIG. 5 is a circuit diagram showing a configuration of the boost driver 142b. Referring to FIG. 5, boost driver 142b generates boost signal BT₀ ⁺And BT₂ ⁺Or BT₁ ⁺And BT_Three ⁺Includes a boost signal generator 142ba. Boost signal generator 142ba has subdecode signal / X₀ ⁺-/ X_Three ⁺And boost signal BT₀ ⁺-BT_Three ⁺Is generated. Therefore, the boost signal BT₀ ⁺-BT_Three ⁺Is the subdecode signal / X₀ ⁺-/ X_Three ⁺As well as the address signal. The boost signal BT₀ ⁺-BT_Three ⁺Each also follows a wafer burn-in signal WBIE or WBIO. Boost signal generator 142ba is a P-channel transistor PT₁And PT₂including. Boost signal generator 142ba is also an N channel transistor NT₁And NT₂including. P-channel transistor PT₁And PT₂The source of the power supply resistance R₁Through step-up potential V_PPIs receiving.
[0048]
P-channel transistor PT₁And N channel transistor NT₁And subdecode signal / X₀ ⁺Or / X₁ ⁺In response to boost signal BT₀ ⁺Or BT₁ ⁺Is configured to output an inverter. P channel transistor PT₂And N channel transistor NT₂And subdecode signal / X₂ ⁺Or / X_Three ⁺In response to boost signal BT₂ ⁺Or BT_Three ⁺Is configured to output an inverter.
[0049]
Boost driver 142b also has a drive signal / DV₀And / DV₂Or / DV₁And / DV_ThreeIncluding a drive signal generator 142bb. Drive signal generator 142bb is a drive signal / DV₀Or / DV₁Is output node ND₁And a node ND to which a low level potential for the drive signal is applied₂N-channel transistor NT connected between_Threeincluding. N-channel transistor NT_ThreeIs the boost signal BT₀ ⁺Or BT₁ ⁺Having a gate to receive. In this embodiment, the node ND₂Has the same ground potential V as the low level potential for the word line._SSIs given.
[0050]
The drive signal generator 142bb is also connected to the output node ND₁And node ND to which high level potential is applied_ThreeCut-off transistor CT and P-channel transistor PT connected in series between_Threeincluding. This cut-off transistor CT is a P-channel transistor. Node ND_ThreeThe power supply resistance R₂Through the power supply potential V_CCIs given. Node ND_ThreeThe high level potential applied to the power supply potential V_CCInstead of boosted potential V_PPIt doesn't matter. The gate of the cut-off transistor CT receives a wafer burn-in signal WBIE or WBIO. The cut-off transistor CT is turned off in response to the wafer burn-in signal WBIE or WBIO. P-channel transistor PT_ThreeIs the boost signal BT₀ ⁺Or BT₁ ⁺Having a gate to receive.
[0051]
The drive signal generator 142bb further includes a P-channel transistor PT_FourAnd N-channel transistor NT_Fourincluding. P-channel transistor PT_ThreeAnd N-channel transistor NT_ThreeIs the boost signal BT₀ ⁺Or BT₁ ⁺According to drive signal / DV₀Or / DV₁Is configured to output an inverter. P channel transistor PT_FourAnd N-channel transistor NT_FourIs the boost signal BT₂ ⁺Or BT_Three ⁺According to drive signal / DV₂Or / DV_ThreeIs configured to output an inverter. The cut-off transistor CT cuts off the supply of the high-level potential to these inverters when the wafer burn-in signal WBIE or WBIO is at the high level. The cut-off transistor CT is provided in common for these inverters. The cut-off transistor CT may be provided for each of these inverters. An increase in area can be suppressed by providing them in common.
[0052]
Cut-off transistor CT is N-channel transistor NT_ThreeDrive signal / DV in response to wafer burn-in signal WBIE or WBIO₀-/ DV_ThreeA circuit for assisting in setting the potential to a low level potential is configured.
[0053]
Drive signal / DV₀-/ DV_ThreeEach of the boost signal BT₀ ⁺-BT_Three ⁺The corresponding signal is the boosted potential V_PPAs it rises toward, it becomes a low level potential. P-channel transistor PT when wafer burn-in signal WBIE or WBIO is high_ThreeAnd PT_FourThe supply of a high level potential to is cut off. Therefore, drive signal / DV₀-/ DV_ThreeIs reliably set to the low level potential, the drive transistor 142ad shown in FIG. 4 is surely turned off. As a result, it is ensured that the potential of the sub word line 141c is the boosted potential V._PPTo rise.
[0054]
In the boost driver 142b shown in FIG. 5, the wafer burn-in signal WBIE or WBIO given to the gate of the cut-off transistor CT is the power supply potential V._CCThe gate insulating film of the cut-off transistor CT is the P-channel transistor PT₁-PT_FourIt is thinner than the insulating film. By thinning the insulating film in this way, the drive signal / DV due to the insertion of the cut-off transistor CT₀-/ DV_ThreeIt is possible to suppress the delay of the rise. That is, the ground potential V through the drive transistor 142ad of the sub word line 141c shown in FIG._SSIt is possible to suppress a delay in reset timing.
[0055]
FIG. 6 is a circuit diagram showing a part of the memory array 141, the row decoder 142, and the sense amplifier 143. Referring to Figure 6, memory block MB_iIncludes a plurality of memory cells 141d arranged in a plurality of rows and a plurality of columns. Memory cell 141d is arranged corresponding to the intersection of bit line pair 141a and sub-word line 141c. Memory block MB_iIs a sub memory block SMB including a plurality of columns of memory cells 141d.₁-SMB_FourIt is divided into Sub memory block SMB₁-SMB_FourEach includes a plurality of sub-word lines 141c provided corresponding to the rows of memory cells 141d, respectively. Each sub word line 141c is connected to a memory cell 141d in the corresponding row. Sub memory block SMB₁-SMB_FourEach include a plurality of bit line pairs 141a provided corresponding to the columns of memory cells 141d, respectively. Each bit line pair 141a is connected to a memory cell 141d in the corresponding column. Sub memory block SMB₁-SMB_FourA plurality of sub word drivers 142a connected to each of the sub word lines 141c are provided on both sides of each of the sub word drivers 141a.
[0056]
Each memory cell 141d has a cell plate potential V on one electrode._CPA memory capacitor consisting of an N channel transistor connected between the other electrode of the memory capacitor CP and the bit line BL or / BL constituting the bit line pair 141a and having a gate connected to the sub word line 141c TR.
[0057]
Sense amplifier band SB_{i + 1}Is the power supply potential V_CCPower supply line 143b, ground potential V_SSPower supply line 143c, common source line 143d, common source line 143e, and bit line precharge potential V_BLIncluding a precharge potential line 143f. Sense amplifier band SB_{i + 1}Sense amplifier enable signal / PSE_{i + 1}Depending on the common source line 143d, the power supply potential V_CCA P-channel transistor 143g for charging is included.
Sense amplifier band SB_{i + 1}In addition, the sense amplifier enable signal NSE_{i + 1}The common source line 143e is connected to the ground potential V according to_SSIncludes an N-channel transistor 143h for discharging to a low voltage.
[0058]
Sense amplifier band SB_{i + 1}Amplifies the potential difference of the bit line pair 141a and sets one potential of the bit line to the power supply potential V_CCThe other potential to ground potential V_SSA plurality of sense amplifiers 143a. Each of the sense amplifiers 143a is cross-coupled, and the potential of the higher bit line of the bit lines BL or / BL is set to the power supply potential V._CCP-channel transistor PT for amplifying to₁₁And PT₁₂including. Each of sense amplifiers 143a is also cross-coupled, and the potential of the lower bit line of bit lines BL or / BL is set to the ground potential V._SSN-channel transistor NT to amplify₁₁And NT₁₂including. The sense amplifier 143a is connected to the power supply potential V from the power supply lines 143b and 143c._CCAnd ground potential V_SSSupplied.
[0059]
Sense amplifier band SB_{i + 1}In addition, bit line equalize signal BLEQ_{i + 1}In response to this, a bit line precharge / equalize circuit 143i for equalizing / precharging the potentials of bit lines BL and / BL is included. The bit line precharge / equalize circuit 143i is connected to the bit line equalize signal BLEQ._{i + 1}N-channel transistor NT for equalizing potentials of bit lines BL and / BL according to₁₃including. The bit line precharge / equalize circuit 143i is also connected to the bit line equalize signal BLEQ._{i + 1}In response to the bit line BL and / BL potential, the bit line precharge potential V_BLN-channel transistor NT for precharging₁₄And NT₁₅including.
[0060]
Sense amplifier band SB_{i + 1}Includes an isolation gate circuit 143j connected between the bit line pair 141a and the sense amplifier 143a. The isolation gate circuit 143j is an N-channel transistor NT₁₆And NT₁₇including. This pair of N-channel transistors NT₁₆And NT₁₇Is the bit line isolation signal BLI_2iOr BLI_{2i + 1}Having a gate to receive. This bit line isolation signal BLI_2iAnd BLI_{2i + 1}Is boosted potential V in response to the address signal_PPOr ground potential V_SSIt becomes. Each of the isolation gate circuits 143j has a bit line isolation signal BLI_2iOr BLI_{2i + 1}In response to this, the corresponding bit line pair 141a is separated from sense amplifier 143a and bit line precharge / equalize circuit 143i.
[0061]
In addition, sense amplifier band SB_{i + 1}Includes a data bus 143k for transmitting data from memory array 141. Each of the data buses 143k includes a pair of data bus lines. Furthermore, sense amplifier band SB_{i + 1}Each of which is a column select signal CSL_pA data transfer circuit 143m for selectively connecting the bit line pair 141a and the data bus 143k according to (p = 0, 1,...) is included. This data transfer circuit 143m includes an N-channel MOS transistor NT₁₈And NT₁₉including.
[0062]
Furthermore, sense amplifier band SB_{i + 1}Is the bit line equalize signal BLEQ_{i + 1}In response, common source line precharge / equalize circuit 143n for equalizing / precharging the potentials of common source lines 143d and 143e is included. The common source line precharge / equalize circuit 143n generates a bit line equalize signal BLEQ._{i + 1}N-channel transistor NT for equalizing potentials of common source lines 143d and 143e according to₂₀including. The common source line precharge / equalize circuit 143n also has a bit line equalize signal BLEQ._{i + 1}In response to the potential of the common source lines 143d and 143e, the bit line precharge potential V_BLN-channel transistor NT for precharging_{twenty one}And NT_{twenty two}Including.
[0063]
Embodiment 2. FIG.
Hereinafter, a DRAM according to another embodiment of the present invention will be described with reference to FIG. The DRAM of the second embodiment is different from the DRAM of the first embodiment in the configuration of the boost driver 142b. Hereinafter, this difference will be described. Referring to FIG. 7, in the second embodiment, N-channel transistor transistor NT is used instead of cut-off transistor CT._FiveAnd NT₆Is placed. N-channel transistor NT_FiveOutput node ND₁And a node ND to which a low level potential is applied₂Connected between. N-channel transistor NT_FiveAnd NT₆N-channel transistor NT_ThreeAnd NT_FourAre connected in parallel.
[0064]
N-channel transistor NT_FiveAnd NT₆N-channel transistor NT_ThreeAnd NT_FourDrive signal / DV in response to wafer burn-in signal WBIE or WBIO₀-/ DV_ThreeA circuit for assisting to set the potential to a low level is formed.
[0065]
N-channel transistor NT_FiveAnd NT₆Is turned on in response to the wafer burn-in signal WBIE or WBIO. N-channel transistor NT when wafer burn-in signal WBIE or WBIO is high_FiveAnd NT₆Turns on. Therefore, drive signal / DV₀-/ DV_ThreeIs forcibly set to a low level potential, the drive transistor 142ad shown in FIG. 4 is surely turned off. As a result, it is ensured that the potential of the sub word line 141c is the boosted potential V._PPTo rise.
[0066]
In the boost driver 142b shown in FIG. 7, the N-channel transistor NT_FiveAnd NT₆The wafer burn-in signal WBIE or WBIO applied to the_CCN-channel transistor NT_FiveAnd NT₆The gate insulation film is an N-channel transistor NT₁-NT_FourIt is thinner than the insulating film. By thinning the insulating film in this way, the switch speed increases and the drive signal / DV₀-/ DV_ThreeIt is possible to suppress the delay in rising and falling.
[0067]
【The invention's effect】
As described above, according to the present invention, the word line is reliably connected to the boosted potential V during wafer level burn-in._PPThere is an effect that it is possible to obtain a semiconductor device to be driven at a high speed.
[Brief description of the drawings]
FIG. 1 is an overview of a DRAM chip according to a first embodiment of the present invention;
FIG. 2 is a schematic diagram of a memory array according to the first embodiment of the present invention.
FIG. 3 is a schematic diagram of a row decoder and a memory block according to the first embodiment of the present invention.
FIG. 4 is a circuit diagram of a sub word driver according to the first embodiment of the present invention.
FIG. 5 is a circuit diagram of a boost driver according to the first embodiment of the present invention.
FIG. 6 is a circuit diagram of the memory array according to the first embodiment of the present invention.
FIG. 7 is a circuit diagram of a boost driver according to a second embodiment of the present invention.
FIG. 8 is a circuit diagram of a conventional word driver.
[Explanation of symbols]
142ba boost signal generator, 142bb drive signal generator
141c Sub word line
142aa drive transistor, 142ab node
142ad drive transistor
142a Subword driver
NT_Three, NT_Four N-channel transistor
ND₁ Output node, ND₂, ND_Three node
CT cut-off transistor
PT_Three, PT_Four P-channel transistor
NT_Five, NT₆ N-channel transistor
141b Main word line
143a sense amplifier
141a Bit line pair
SB₁-SB_{n + 1} Sense amplifier band
SWDB₁-SWDB_Five Subword driver band
141d memory cell, SMB₁-SMB_Four Sub memory block
142b Boost Driver

Claims (9)

A boost signal generator for generating a boost signal;
The boost signal and the wafer burn-in signal are received, a drive signal that becomes a low level potential is output as the boost signal rises toward a boost potential higher than the power supply potential, and the boost signal is activated when the wafer burn-in signal is activated A drive signal generator for setting the drive signal to the low level potential in response to
A plurality of word lines, and a first drive transistor connected to each of the plurality of word lines and the output of the boost signal generator, each for transmitting the boost signal to a corresponding word line in accordance with a word line select signal A second drive transistor connected between the corresponding word line and a node to which a low-level potential for the word line is applied, and having a gate for receiving the drive signal and being turned off when the drive signal is at the low level With multiple word drivers including
The drive signal generator is connected between an output node for outputting the drive signal and a node to which the low-level potential is applied, and has an N-channel transistor having a gate for receiving the boost signal, and the output node A cut-off transistor and a P-channel transistor connected in series with a node to which a high-level potential is applied; the cut-off transistor is turned off in response to the activation of the wafer burn-in signal; Is a semiconductor device having a gate for receiving the boost signal.   The semiconductor device according to claim 1, wherein the cut-off transistor has a thinner gate insulating film than the P-channel transistor. A boost signal generator for generating a boost signal;
The boost signal and the wafer burn-in signal are received, a drive signal that becomes a low level potential is output as the boost signal rises toward a boost potential higher than the power supply potential, and the boost signal is activated when the wafer burn-in signal is activated. A drive signal generator for setting the drive signal to the low-level potential in response to
A plurality of word lines, and each of the plurality of word lines and an output of the boost signal generator are connected to each other, and each transmits the boost signal to the corresponding word line in accordance with a word line selection signal designating the corresponding word line. And a gate connected to the corresponding word line and a node to which a low-level potential for the word line is applied, and receiving the drive signal, and selectively according to the gate potential A plurality of word drivers including a second drive transistor that transmits the low level potential to a corresponding word line and is turned off when the gate potential is low;
The drive signal generator is connected between an output node for outputting the drive signal and a node to which the low-level potential is applied, and has a first N-channel transistor having a gate for receiving the boost signal; The first node is connected between an output node and a node to which a high level potential is applied, and has a gate for receiving the boost signal, and between the output node and a node to which the low level potential is applied. A second N-channel transistor connected in parallel with the N-channel transistor and turned on in response to activation of the wafer burn-in signal.   The semiconductor device according to claim 3, wherein the second N-channel transistor has a thinner gate insulating film than the first N-channel transistor. A plurality of main word lines extending in a first direction;
A sense amplifier band including a plurality of sense amplifiers respectively connected to a plurality of bit line pairs arranged along the first direction and extending along a second direction intersecting the first direction;
A plurality of sub-word lines extending along the first direction and arranged in a predetermined number corresponding to the main word lines;
A plurality of boosted signals are arranged along the second direction so as to correspond to the plurality of sub word lines, each having a gate connected to a corresponding one of the plurality of main word lines. The plurality of boost signals are connected between a first drive transistor for transmitting one of the corresponding ones to the corresponding sub word line and a node to which a low level potential for the corresponding sub word line and the sub word line is applied. A second gate that receives one of a plurality of drive signals corresponding to each of the first and second drive signals, transmits the low level potential of the node to the corresponding sub-word line according to the gate potential, and is turned off when the gate potential is low level. A plurality of subword drivers including a drive transistor, and a subword driver disposed in a direction intersecting the sense amplifier band. Band,
A sub memory block including a plurality of memory cells arranged corresponding to intersections of the plurality of bit line pairs and the plurality of sub word lines, and arranged in an intersection region of the sense amplifier band and the sub word driver band; The boost signal generator for generating the plurality of boost signals, the plurality of boost signals and the wafer burn-in signal, and a corresponding drive as the applied boost signal rises toward a boost potential higher than the power supply potential. A step-up driver including a drive signal generator having a signal as a low level potential for a drive signal and a corresponding drive signal as a low level potential for the drive signal in response to activation of a given wafer burn-in signal Prepared,
The drive signal generator is connected between an output node for outputting each corresponding drive signal and a node to which a low level potential for the drive signal is applied, and has an N channel having a gate for receiving the corresponding boost signal A transistor, and a cut-off transistor and a P-channel transistor connected in series between the output node and a node to which a high-level potential is applied, wherein the cut-off transistor is responsive to activation of the wafer burn-in signal A semiconductor device which is turned off and the P-channel transistor has a gate for receiving the corresponding boost signal.   The semiconductor device according to claim 5, wherein the cut-off transistor has a thinner gate insulating film than the P-channel transistor. A plurality of main word lines extending in a first direction;
A plurality of sub-word lines arranged so as to extend along the first direction and having a predetermined number arranged corresponding to each of the main word lines;
A plurality of bit line pairs arranged to extend along a second direction intersecting the first direction;
A sense amplifier band including a plurality of sense amplifiers disposed along the first direction and connected to the plurality of bit line pairs,
A gate disposed along the second direction and corresponding to each of the plurality of sub-word lines, each having a gate connected to a corresponding one of the plurality of main word lines; A first drive transistor for selectively transmitting one of a plurality of boost signals to a corresponding sub word line according to a gate potential, and a node to which a low level potential for the corresponding sub word line and sub word line is applied A gate connected to each other and receiving a corresponding one of a plurality of drive signals respectively corresponding to the plurality of boosted signals, and selectively transmits the low level potential to a corresponding word line according to the gate potential. a second drive transistor gate potential is turned off when the low level comprises including multiple sub-word driver, the sense amplifier vans Sub-word driver band that intersects with,
A sub memory block including a plurality of memory cells arranged corresponding to intersections of the plurality of bit line pairs and the plurality of sub word lines, and arranged in an intersection region of the sense amplifier band and the sub word driver band; The boost signal generator for generating the plurality of boost signals, the plurality of boost signals and the wafer burn-in signal, and a corresponding drive as the applied boost signal rises toward a boost potential higher than the power supply potential. A boosting driver including a drive signal generator that sets a low-level potential for a drive signal and a corresponding drive signal to a low-level potential for the drive signal when a given wafer burn-in signal is activated;
The drive signal generator is connected between an output node for outputting a corresponding drive signal and a node to which a low level potential for the drive signal is applied, and has a gate for receiving a corresponding boost signal. An N channel transistor, a P channel transistor connected between the output node and a node to which a high level potential is applied, and having a gate for receiving the corresponding boosted signal; a low level for the output node and the drive signal; A semiconductor device including a second N-channel transistor connected in parallel to the first N-channel transistor between a node to which a potential is applied and turned on in response to activation of the applied wafer burn-in signal.   The semiconductor device according to claim 7, wherein the second N-channel transistor has a thinner gate insulating film than the first N-channel transistor.   The semiconductor device according to claim 1, wherein the cutoff transistor is a P-channel transistor.

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