JPH05342112A - Memory control circuit - Google Patents

Abstract

PURPOSE:To efficiently specify the defective part of a memory by preserving the defective part of the memory by a hardware and providing a circuit for reading out the preserved defective part by a central processing unit in a memory control circuit. CONSTITUTION:An error latch part 12 monitors RAS0#, RAS1# signals 13, CAS0H#, CAS0L#, CAS1L#, and CAS1L# signals 14, a WE# signal 15 and a memory address 16. In such a state, when a parity error signal 17 from a parity comparing part 11 becomes active, the error latch part 12 latches a monitoring signal as error information in the inside. To the memory address 16, a row address and a column address are subjected to time division and supplied and the respective addresses are fetched to the inside of the error latch part 12 by the RAS0#, RAS1# signals 13 and the CAS0H#, CAS0L#, CAS1H# and CAS1L# signals 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control circuit which can be used in a computer using a memory.

[0002]

2. Description of the Related Art A conventional memory control circuit will be described below with reference to the drawings. FIG. 3 shows a conventional memory control circuit. In FIG. 3, 1 is an address translation unit, 2
Is a decoder unit, 3 is a data buffer, 4 is a parity generation unit, 5 is a parity compare unit, and 6 is a parity error signal.

The operation of the memory control circuit thus configured will be described below. The parity generation unit 4 generates a parity bit and outputs it to the memory when the memory is written. The parity compare unit 5 activates the parity error signal 6 when a memory parity error occurs, and indicates the error occurrence to the central processing unit. However, the parity compare unit 5 does not return any error information. At this time, conventionally, the defective portion of the memory is displayed by the address of the central processing unit by the error processing routine of the software.

[0004]

However, in the above-mentioned configuration, since the analyzer only knows the defective portion by the CPU address returned by the error processing routine of the software, the actual defective portion of the memory can be easily specified. It was difficult. Further, in a system having a plurality of memory banks, it is difficult to find an actual defective bank because the bank is designated by a control signal (RAS, CAS, WE signal, etc.) other than the address.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a memory control circuit which can realize the efficiency of specifying a memory defective portion.

[0006]

In order to achieve the above object, the memory control circuit of the present invention is a memory control circuit for storing a defective portion of a memory by hardware and reading the stored defective portion by a central processing unit. The configuration is provided in the control circuit.

[0007]

With the above structure, the memory failure analyzer can know the defective memory address and the defective bank, and the efficiency of the memory failure analysis can be greatly improved. Moreover, recent memory control circuits are realized on a large-scale integrated circuit, and a circuit for realizing the memory failure analysis can be realized at a very low cost.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a memory control circuit according to an embodiment of the present invention. In FIG. 1, 7 is an address conversion unit for generating an address from the central processing unit to the memory, 8 is a decoder unit for generating a control signal from the central processing unit to the memory, and 9 is a data buffer unit.
Reference numeral 10 is a parity generation unit, 11 is a parity compare unit that detects the presence or absence of a parity error, and 12 is an error latch unit that stores a memory address and a memory control signal when the parity error occurs as error information. 13 is a RAS0 #, RAS1 # signal, 14
Is CAS0H #, CAS0L #, CAS1H #, CAS
1L # signal and 15 are WE # signals, which are memory control signals. 16 is a memory address and 17 is a parity error signal.

In FIG. 1, DR is used as a memory device.
It is assumed that AM is used and two memory banks with a 16-bit data width are used. Each bank is distinguished by the RAS0 # and RAS1 # signals 13, and each bank is identified by CAS0H #, CAS0L #, CAS1H #,
It is assumed that the CAS1L # signal 14 can be used for reading and writing in 8-bit units, and the parity bit is composed of 1 bit for every 8 bits. At this time, the air latch section 12
RAS0 #, RAS1 # signal 13, CAS0H #, C
AS0L #, CAS1H #, CAS1L # signal 14, WE
# Signal 15 and memory address 16 are being monitored. Here, when the parity error signal 17 from the parity compare unit 11 becomes active, the error latch unit 12 internally latches the monitoring signal as error information. The memory address 16 is supplied with the row address and the column address time-divided, but each address is RAS.
0 #, RAS1 # signal 13, CAS0H #, CAS0L
It is taken into the inside of the error latch unit 12 by the #, CAS1H #, and CAS1L # signals 14.

FIG. 2 is an internal block diagram of the error latch unit 12. In FIG. 2, 18 to 21 are latches, 22 is a row address latch, 23 is a column address latch, 24 is a RAS latch, 25 is a CAS latch, 26 to 29 are tristate buffers, 30 to 31 are AND gates, and 32 is DELAY. , 33 is an address decode, 34 is a CPU address, 35 is an I0R # signal, 36 is an AEN signal, and 37 is CPU data.

When the central processing unit is accessing the memory, the latch 18 always latches the row address to the DRAM. The latch timing is performed when the output of the AND gate 30 becomes active. The latch 19 always latches the column address when the central processing unit is accessing the memory. The latch timing is performed when the output of the AND gate 31 becomes active. Similarly, the latch 20 is RAS0 #, RAS1 # when the central processing unit is accessing the memory.
No. 13 and WE # signal 15 are latched, and latch 21 is CAS0H
#, CAS0L #, CAS1H #, CAS1L # signals 14
Latch. The latch timing of the latch 20 is performed by the output of the AND gate 31, and the latch timing of the latch 21 is performed by delaying the output of the AND gate 31 by DELAY32. By the above operation, the contents of the latches 18, 19, 20, 21 are updated every memory access of the central processing unit. Here, when a parity error occurs, the parity error signal 17 is issued from the parity conveyor unit 11 of FIG. This is the parity error signal 17
Row address latch 22, column address latch
23, the RAS latch 24, and the CAS latch 25 take in the contents of the latch 18, the latch 19, the latch 20, and the latch 21, respectively.

As described above, the error information includes the row address latch 22, the column address latch 23, the RAS latch 24,
Stored in the CAS latch 25, the RAS latch 24,
The contents of the CAS latch 25 can be used to identify the bank of defective memory. The latched error information can be read by the central processing unit via the tri-state buffers 26, 27, 28 and 29. That is, the tri-state buffers 26, 27, 28, 29 are assigned to specific addresses in the I / O space of the central processing unit, and the address decode 33
Decodes the CPU address 34, the I0R # signal 35, and the AEN signal 36, enables the corresponding tri-state buffer, and outputs the contents as CPU data 37. As a result, when a parity error occurs and the central processing unit enters the parity error processing routine, the defective portion of the memory can be easily displayed on the display.

[0013]

As described above, the memory control circuit of the present invention can easily indicate the defective portion of the memory by capturing the defective portion of the memory as hardware. This can give appropriate information to the analyst in the analysis of repair and market defects in the product development stage and process. Also, the test software can obtain detailed information about the memory without knowing the detailed structure of the hardware. Therefore, it is very useful for improving the efficiency of memory failure analysis. Further, since the current memory control circuit is integrated into one chip as a large-scale integrated circuit, this function can be realized without increasing the number of parts.

[Brief description of drawings]

FIG. 1 is a block diagram of a memory control circuit according to an embodiment of the present invention.

FIG. 2 is an internal configuration diagram of an error latch unit in the memory control circuit according to the embodiment of the present invention.

FIG. 3 is a block diagram of a conventional memory control circuit.

[Explanation of symbols]

 12 Error Latch 18 to 21 Latch 22 Row Address Latch 23 Column Address Latch 24 RAS Latch 25 CAS Latch 26 to 29 Tri-State Buffer 33 Address Decode

Claims (1)

[Claims] 1. A circuit for generating a control signal to a memory based on a control signal from a central processing unit, and a circuit for storing a memory address and a memory control signal as error information when a memory parity error occurs, A memory control circuit having a circuit for reading error information by a central processing unit.