JPH05342111A - Memory testing system - Google Patents

Abstract

PURPOSE:To test a memory attached to a main processor without spending time compared with conventional test without imposing a burden on the main processor. CONSTITUTION:A memory test starting address accumulating part ADRREG 8 and a test finishing part 9 accumulate a starting address and an end address instructed from a CPU 1, respectively. A test address generating part 10 updates successively an address from the start address, and supplies it to a memory part 14. A test data generating part 7 generates write data and supplies the data to an MEM 14 and a test end detecting part 11 compares a memory access address with the end address, and finishes the sequence, in the case they coincide with each other. A data comparing part 16 reads out the data from the starting address after the sequence is finished and compares the data with the data generated by the same sequence. A non-coincidence information accumulating part 17 accumulates the address and the data and notifies them to the CPU 1, in the case the data are in discordance and notifies the normal end information to the CPU 1 in the case all addresses are finished normally.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a central control unit having a main processor used in a data processing device and the like and a memory section associated therewith, and more particularly to a memory test system for testing the memory section.

[0002]

2. Description of the Related Art Conventionally, in a test of a memory section of a central control unit, a main processor writes data in the memory section, then reads the data, and whether or not the data can be normally written in and read from the memory section. I'm testing.

[0003]

In the conventional memory test method described above, since the main processor directly performs this memory test, a load is applied to the main processor and it takes time to test the memory section. was there.

[0004]

According to a memory test method of the present invention, a start address and an end address designated by the main processor are accumulated in a central control unit having a main processor and a memory section attached to the main processor. Means, means for updating the addresses sequentially from the start address and supplying the addresses to the memory section, means for generating write data to the memory section together with the addresses and supplying the same to the memory section, a memory access address and an end address. Means for terminating the memory write sequence when compared and matched, and means for sequentially reading data from the start address after the sequence and comparing the data with the data created in the same sequence as when writing
When the comparison result indicates that the data do not match, the address and the data are stored, and the main processor is notified, and when all the addresses are normally ended, a normal end information is notified to the main processor. is there.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, a central controller is a main processor (CPU) 1 and a storage memory device (MEM CARD).
It is configured to include 2 and 3. MEM CARD3
Is for memory expansion, internal configuration is MEM CARD2
Since it is exactly the same as, the internal illustration is omitted. MEM CA
The RD 2 includes an address signal interface unit (ADR GT) 4 that receives an address signal from the CPU 1 and a control signal interface unit (CNT) that also receives a control signal.
GT) 5, a data interface unit (DATA GT) 6 that also transmits and receives data, a memory unit (MEM) 14 for storing data, and write data to the MEM 14 together with an address signal is generated and supplied to the MEM 14. A memory test control unit and a test data generation unit (CONT & DATAG) 7, a memory test start address storage unit (ADR REG) 8 for storing a test start address instructed by the CPU 1, and a test end address instructed by the CPU 1 The memory test end address storage unit (ADR REG) 9 to be stored, the memory test address generation unit (ADRCNT) 10 that sequentially updates the address from the start address and supplies it to the MEM 14, and the memory access address and the end address are compared and matched. End the memory write sequence Causing the memory testing end detection unit and (ADR CMP) 11, a memory address selector (S
EL) 12 and memory control signal selection unit (SEL) 13
And a data buffer (BUF) 15 and a data comparison unit (DATA CMP) 16 for sequentially reading data from the start address after the end of the corresponding sequence and comparing this data with the data created in the same sequence as when writing
If the data do not match as a result of this comparison, the corresponding address and data are accumulated and the CPU 1 is notified, and if all addresses are normally completed, the normal end information is sent to the CPU.
1 is provided.

The operation will be described below. During the memory test, the memory test start address is transferred from the main processor (CPU) 1 to the memory test start address storage unit (ADR R
EG) 8 and the memory test end address is set in the end address storage unit (ADR REG) 9 and then the main processor (CPU) 1 controls the memory test control unit and the test data generation unit (CONT & DATAG) 7 To start.

The memory test control section and test data generation section 7 controls the memory address selection section (SEL) 12, the memory control signal selection section (SEL) 13, and the data interface section (DATA GT) 6 to store the memory. Department (ME
M) 14 includes a memory test address generator (ADR CN)
T) 10 for address information, and memory test control section and test data generation section (CONT & DATA) 7 for memory control signals (memory read, memory write signals, etc.)
And test memory write data.

After the completion of one write sequence, the memory write address and the memory test end address are compared by the memory test end detecting section (ADR CMP) 11,
The match / mismatch information is notified to the memory test control unit and test data generation unit (CONT & DATAG) 7. If they do not match, the memory test address generator (ADRC
The address of the NT) 10 is updated, and the write data to the memory is newly generated and written in the memory unit (MEM) 14. After this sequence is repeated, if the memory write address and the memory test end address match, the memory test end detection unit (ADR CMP) 11 sends matching information to the memory test control unit and test data generation unit (CONT).
& DATAG) 7 and notify the end of the write sequence.

After that, the data in the memory unit (MEM) 14 is sequentially read from the memory start address, and the data at the time of writing is written in the memory test control unit and the test data generating unit (CONT) by the same method as that at the time of writing.
& DATAG) 7 and the read data is compared with the data comparison unit (DATA CMP) 6
If they match, the read address is sequentially updated and the memory test end address is executed. If all addresses match, the main processor (C
PU) 1 is notified of normal end, and the memory test control unit and test data generation unit (CONT & DATAG) 7
Memory address selection unit (SEL) 12, memory control signal selection unit (SEL) 13, and data interface unit (D)
The ATAGT) 6 is controlled to supply the memory unit (MEM) 14 with the address information, the memory control signal, the data, etc. from the main processor (CPU) 1, and the series of memory test processing is completed.

When a data mismatch is detected during the test, the memory access address at that time, the memory test control section, and the test data generation section (CONT &
DATA generated in DATA 7 and memory unit (ME
M) The data read from 14 is stored in the mismatch information storage unit (R
EG) 17 and notifies the main processor (CPU) 1 of abnormal termination, and the memory test control unit and test data generation unit (CONT & DATAG) 7 select the memory address selection unit (SEL) 12 and memory control signal selection. Department (S
EL) 13 and data interface unit (DATA G
T) 6 is controlled to supply address information, memory control signals, data, etc. from the main processor (CPU) 1 to the memory unit (MEM) 14, and a series of memory test processing is completed.

In addition, in the system in which the main processor (CPU) 1 is operated using the storage memory device (MEM CARD) 2, when the storage memory device (MEM CARD) 3 is added as a memory extension, the storage memory device is added. After the (MEM CARD) 3 is installed in the system, a memory test is started in the storage memory device (MEM CARD) 3, and only the storage memory device (MEM CARD) 2 is operated until the test is completed. , After confirming that the memory test of the storage memory device (MEM CARD) 3 is completed normally,
CARD) 2 and 3 are used to expand the memory capacity for operation.

[0013]

As described above, according to the present invention, the means for accumulating the start address and the end address designated by the main processor, the means for sequentially updating the address from the start address and supplying the same to the memory section, and the memory access address. Means for terminating the memory write sequence when they match and the end address, and means for sequentially reading data from the start address after the sequence and comparing the data with the data created in the same sequence as when writing By including means for accumulating the address and data when the data do not match as a result of comparison and notifying the main processor and notifying the main processor of normal termination information when all the addresses are normally terminated,
There is an effect that the memory test of the memory unit associated with the main processor can be performed without imposing a load on the main processor and in a shorter time than in the past.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

1 Main Processor (CPU) 2, 3 Storage Memory Device (MEM CARD) 4 Address Signal Interface Unit (ADR GT) 5 Control Signal Interface Unit (CNT GT) 6 Data Interface Unit (DATA GT) 7 Memory Test Control Unit and Test Data generator (C
ONT & DATAG 8 Memory test start address storage unit (ADR RE
G) 9 Memory test end address storage (ADR RE
G) 10 Memory test address generator (ADR CN
T) 11 Memory test end detection unit (ADR CMP) 12 Memory address selection unit (SEL) 13 Memory control signal selection unit (SEL) 14 Memory unit (MEM) 15 Data buffer (BUF) 16 Data comparison unit (DATA CMP) 17 Discrepancy information storage unit (REG)

Claims (1)

[Claims] 1. A central control unit having a main processor and a memory section associated with the main processor,
Means for accumulating a start address and an end address instructed by the main processor, means for sequentially updating addresses from the start address and supplying the addresses to the memory section, and write data for writing to the memory section together with the addresses And a means for terminating the memory write sequence when the memory access address and the end address are compared with each other, and a sequence in which the data is sequentially read from the start address after the sequence and the data and the same sequence as at the time of writing. The means for comparing with the data created in the above, and when the data do not match as a result of the comparison, the address and the data are accumulated and the main processor is notified, and when all the addresses are normally ended, the normal end information is sent. Means for notifying the main processor. Li test method.