JPH05341013A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To provide a semiconductor integrated circuit which is capable of enhancing the circuit evaluation efficiency in its reliability test. CONSTITUTION:A semiconductor integrated circuit concerned includes at least one failure sensing means 1-1 through 1-n to sense a specified type of failure and a clock stopping means 3 which fixes to H or L the level of a clock pulse CLK supplied to the whole or a part of the integrated circuit on the basis of the sensing result given by the said means and stops the supply. The clock stopping means 3 resumes supply of the clock pulse CKK to the whole or part of the integrated circuit in conformity to a reset signal RST given from inside and outside of the integrated circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a semiconductor integrated circuit with improved test efficiency such as reliability evaluation.

[0002]

2. Description of the Related Art When a semiconductor integrated circuit (hereinafter abbreviated as LSI) such as a microprocessor and a memory is commercialized, a reliability test is conducted. This reliability test is further composed of a plurality of tests, one of which is a life test. This life test is for a certain period (usually about 10 years) when the user uses the LSI under the recommended conditions.
It is a test that guarantees normal operation. Since it is difficult to actually carry out the life test for 10 years, set the power supply voltage, operating temperature, etc. to the worst conditions (high voltage, high temperature) that are stricter than the recommended conditions, accelerate the deterioration of the LSI, and accelerate it for a short period (usually Test for about 2000 hours). Briefly, the life test is performed by operating the LSI in a high temperature oven by applying a high power supply voltage.

FIG. 4 shows a jig configuration diagram used for a life test. In the figure, the test device is a test LSI 61 (hereinafter, simply referred to as DUT (Device Under T
est)), a pattern generator 53 that generates a clock pulse or a test pattern to be applied to the DUT 61, and a power supply 5 that supplies the DUT 61.
1 and 1. Although not shown, the DU
An LSI tester for performing initial evaluation, intermediate (lap) evaluation, and final evaluation of T61 is required.

By the way, usually, LSI failures can be classified into three types: initial failures, accidental failures, and wear failures. That is, in general, the failure occurrence rate when time is plotted on the horizontal axis is a bathtub-shaped curve as shown in FIG. 8, but the initial failure period gradually decreases with time, and the failure rate is constant over time. It is categorized into three types: accidental failure period according to pattern, damage due to fatigue, wear, corrosion, etc. There is.

The purpose of the life test is to predict the life of the LSI by drawing a bathtub-like failure curve as shown in FIG. 8, that is, the time until the initial failure disappears and the wear failure occurs. To predict the time. Therefore, in order to accurately draw this failure curve, a large number of samples and multiple lap measurements are required.

The processing procedure of the conventional life test will be described with reference to the flowchart shown in FIG. It should be noted that here, a total of 2000 hours was evaluated and the lap measurement was 1
It shall be performed when 68 hours, 500 hours, and 1000 hours have passed.

First, all DUTs are evaluated by an LSI tester to confirm that all are good samples (step S11). Next, the sample is placed in a high-temperature oven and operated at a high power supply voltage while applying a clock pulse and a test pattern to the input (step S1).
2). When 168 hours have passed, all DUTs are taken out of the oven and evaluated using the LSI tester (step S13). Here, the defective products are analyzed for defects, and only the non-defective products are put in the high temperature oven again, and 5
Lap evaluation after lapse of 00 hours (steps S14 and S1
5), lap evaluation after 1000 hours (step S1
6 and S17) and the final evaluation after 2000 hours (steps S18 and S19).

Further, the conventional LSI incorporates a parity error checker and a self-test circuit, and
It is possible to judge whether each circuit constituting the SI is normal or abnormal.

[0009]

Therefore, in the conventional semiconductor integrated circuit, in order to draw an accurate bathtub-like failure curve, many lap evaluations must be performed on a large number of samples, and the evaluation of There was a problem of reducing efficiency.

Further, normally, only one power source is supplied to the test semiconductor integrated circuit. Therefore, in the case where a failure occurs such that the power source and the ground are short-circuited in one chip among many test semiconductor integrated circuits. In some cases, the power supply voltage supplied to other tested semiconductor integrated circuits may drop.
In this case, since the normal power supply voltage is not applied to the normal test semiconductor integrated circuit, there is a problem that the reliability of the evaluation data is lowered.

Further, when a failure occurs in the test semiconductor integrated circuit, the failure location and the cause of the failure are analyzed. At this time, if there is only one failure in the test semiconductor integrated circuit, the failure easily occurs. It is possible to analyze the location and the cause of the failure, but if the clock pulse, test pattern, and power are supplied even after the failure occurs, other failures will occur, making failure analysis difficult. There was a problem of being lost.

The present invention solves the above problems,
It is an object of the present invention to provide a semiconductor integrated circuit capable of improving the evaluation efficiency of a reliability test in the evaluation of the semiconductor integrated circuit.

[0013]

In order to solve the above problems, the first feature of the present invention is to provide at least one abnormality detecting means 1 for detecting a predetermined abnormality as shown in FIG.
1 to 1-n and the clock pulse CLK supplied to all or part of the semiconductor integrated circuit based on the detection results of the abnormality detecting means 1-1 to 1-n are at "H" level or "L" level. It is fixedly provided with the clock stop means 3 for stopping the supply.

A second feature of the present invention is that in the semiconductor integrated circuit according to claim 1, the clock stopping means 3 is
The supply of the clock pulse CLK to the whole or a part of the semiconductor integrated circuit is restarted by the reset signal RST from inside and outside the semiconductor integrated circuit.

The third feature of the present invention is shown in FIG.
, At least one abnormality detecting means 1-1 to 1-n for detecting a predetermined abnormality and the abnormality detecting means 1-1.
Power supply stop means 5 for stopping the power supply to all or part of the semiconductor integrated circuit based on the detection results of 1-n.
And to have.

A fourth feature of the present invention is that in the semiconductor integrated circuit according to claim 3, the power supply stopping means 5 is
The power supply to all or part of the semiconductor integrated circuit is restarted by the reset signal RST from inside and outside the semiconductor integrated circuit.

Further, the fifth feature of the present invention is that shown in FIG.
, At least one abnormality detecting means 1-1 to 1-n for detecting a predetermined abnormality and the abnormality detecting means 1-1.
Based on the detection result of 1-n, the input data IDATA supplied to all or part of the semiconductor integrated circuit is
Data supply stopping means 7 is provided for fixing the H "level or the" L "level and stopping the supply or preventing the state transition of the whole or a part of the semiconductor integrated circuit from affecting the input data IDATA. That is.

A sixth aspect of the present invention is the semiconductor integrated circuit according to the fifth aspect, wherein the data supply stopping means 7 is provided.
Is a reset signal RST from inside or outside the semiconductor integrated circuit.
To restart the supply of the input data IDATA to the whole or a part of the semiconductor integrated circuit.

[0019]

In the semiconductor integrated circuit of the first and second features of the present invention, as shown in FIG.
A predetermined abnormality is detected by -n, and when the abnormality is detected, the clock pulse CLK supplied to the whole or a part of the semiconductor integrated circuit by the clock stopping means 3 is supplied.
The supply is stopped by fixing the H "level or the" L "level, and the reset signal RST from inside and outside the semiconductor integrated circuit
As a result, the supply of the clock pulse CLK to all or part of the semiconductor integrated circuit is restarted.

Thus, in the reliability test, for example, if the elapsed time of current consumption is drawn, the total current consumption will decrease by a constant current each time one semiconductor integrated circuit fails, and the initial failure will disappear. Up to, as well as the time to wear failure,
In addition, since a test can be performed with a relatively small amount of samples by a simple procedure, it is possible to realize a semiconductor integrated circuit capable of improving the evaluation efficiency of the reliability test without lowering the evaluation efficiency.

Further, in the semiconductor integrated circuit of the third and fourth features of the present invention, as shown in FIG. 1B, the abnormality detecting means 1-1 to 1-n detect a predetermined abnormality and the abnormality is detected. When it is detected, the power supply stopping means 5 stops the power supply to all or part of the semiconductor integrated circuit. Also,
By a reset signal RST from inside and outside the semiconductor integrated circuit,
Power supply to all or part of the semiconductor integrated circuit is restarted.

Therefore, the same effect can be obtained by performing the reliability test similar to that of the semiconductor integrated circuit having the first and second characteristics. Moreover, even if a short-circuit fault occurs such that the power supply and the ground are short-circuited in a certain test semiconductor integrated circuit, the power supply voltage supplied to the other test semiconductor integrated circuits does not drop, so the reliability of the evaluation data is high. Does not decrease.

Further, in the semiconductor integrated circuit having the fifth and sixth characteristics of the present invention, as shown in FIG. 1C, the abnormality detecting means 1-1 to 1-n detect a predetermined abnormality, and the abnormality is detected. If detected, the input data ID supplied to the whole or part of the semiconductor integrated circuit by the data supply stopping means 7.
ATA is fixed at "H" level or "L" level,
The supply is stopped or the state transition of the whole or a part of the semiconductor integrated circuit is prevented from affecting the input data. In addition, a reset signal R from inside and outside the semiconductor integrated circuit
By ST, the supply of the input data IDATA to the whole or part of the semiconductor integrated circuit is restarted.

Therefore, the same effect can be obtained by performing a reliability test similar to that of the semiconductor integrated circuit having the first and second characteristics.

Further, in the semiconductor integrated circuit of the first to sixth features of the present invention, in the reliability test, the supply of the clock pulse, the power supply, or the test pattern is stopped at the time of occurrence of a failure, so that the semiconductor integrated circuit under test is tested. If a failure occurs in the
It can be implemented reliably.

[0026]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 shows a circuit diagram of a semiconductor integrated circuit according to the first embodiment of the present invention.

In the figure, in the semiconductor integrated circuit of this embodiment, a parity error checker 1-1 for performing a parity check of an internal bus and the like as an abnormality detecting means, and a self-test execution for confirming a self-test execution result. A self-test execution result checker 1-2 for confirming the result, and a parity error checker 1-1 and a self-test execution result checker 1-2 as clock stopping means.
On the basis of the detection results chk1 and chk2, the clock pulse CLK supplied to all or part of the semiconductor integrated circuit is fixed at "H" level or "L" level
The clock stop circuit 3 for stopping the supply is provided.

The clock stop circuit 3 includes a parity error checker 1-1 and a self-test execution result checker 1.
-Input OR gate 11 that ORs the detection results chk1 and chk2 of -2 and the output of the flip-flop 13
And OR gate 11 output to external input clock CLOCK
The D-type flip-flop 13 which is held in synchronization with the input signal CLO and is cleared by the reset signal RST, and the input clock CLO.
It is composed of a 2-input OR gate 15 which takes the logical sum of CK and the output of the flip-flop 13 and outputs it as an internal clock CLK.

FIG. 3 is a timing chart for explaining the operation of this embodiment.

In the T1 cycle of the first clock, since the error generation signals from the parity error checker 1-1 and the self-test execution result checker 1-2 are inactive, the external input clock CLOCK is directly used as the internal clock CLK in the semiconductor integrated circuit. Supplied in the circuit.

In the T2 cycle, an error is detected by the parity error checker 1-1, and the parity error signal c
hk1 is active. In the T3 cycle, the content of the flip-flop 13 changes to the "H" level, whereby the input clock CLOCK is masked by the OR gate 15, and as the internal clock CLK, a signal which is always fixed at the "H" level in the semiconductor integrated circuit. Is supplied. Here, the internal circuit of the semiconductor integrated circuit uses the internal clock CLK.
Is fixed to the "H" level, it does not operate and consumes no current.

Next, in the Tn cycle, the reset signal RS
When T is activated, the output of the flip-flop 13 becomes "L" level in the cycle Tn + 1, and the external input clock CLOCK is directly supplied to the semiconductor integrated circuit as the internal clock CLK.

Next, when performing a life test of the semiconductor integrated circuit having such a structure, a jig having a structure as shown in FIG. 4 is used as in the conventional case.

The processing procedure of the life test is shown in the flowchart of FIG. As shown in the figure, the procedure is extremely simple compared to the conventional one, and LS is performed in step S1.
The test semiconductor integrated circuit is initially evaluated by the I tester and is operated in the high temperature oven for 2000 hours (step S2).

In the life test of this embodiment, drawing the bathtub-shaped failure curve shown in FIG. 8 is equivalent to drawing the elapsed time of the consumption current indicated by the ammeter 57 (see FIG. 6). This is because the semiconductor integrated circuit of the present embodiment consumes a constant current during operation. That is, as shown in FIG.
The fact that the total current consumption decreases by a constant current I each time one semiconductor integrated circuit 61 above 5 fails is used.

Therefore, by drawing a characteristic curve of operating time-current consumption as shown in FIG. 6, it is possible to predict the time until the initial failure disappears and the time until the abrasion failure occurs.

In this embodiment, the abnormality detecting means is
Although the parity error checker 1-1 and the self-test execution result checker 1-2 are illustrated as examples, other abnormality detecting means may be provided.

Next, FIG. 7A shows a configuration diagram of a semiconductor integrated circuit according to a second embodiment of the present invention. The figure shows a concrete circuit example of the power supply stopping means 5 for stopping the power supply to all or part of the semiconductor integrated circuit based on the detection results of the abnormality detecting means 1-1 to 1-n. Yes, as in the first embodiment, the detection results chk of the parity error checker 1-1, the self-test execution result checker 1-2, etc.
From 1 and chk2, when an error occurs, the switch SW is turned off to stop the power supply to all or part of the semiconductor integrated circuit, and the reset signal RST turns on the switch SW. The power supply to the semiconductor integrated circuit is restarted again.

With such a structure, a reliability test such as a life test can be performed by a simple procedure, as in the first embodiment. In addition, even if a failure such as a short circuit between the power supply and the ground occurs in a certain test semiconductor integrated circuit, the power supply to that test semiconductor integrated circuit is stopped, so the power supply voltage to be supplied to other test semiconductor integrated circuits. Does not decrease, and the reliability of evaluation data does not decrease.

Further, FIG. 7B shows a configuration diagram of a semiconductor integrated circuit according to the third embodiment of the present invention. This figure shows the input data ID supplied to all or part of the semiconductor integrated circuit based on the detection results of the abnormality detection means 1-1 to 1-n.
ATA is fixed at "H" level or "L" level,
The specific circuit example of the data supply stopping means 7 for stopping the supply is shown, and similarly to the first embodiment, the detection result chk1 of the parity error checker 1-1 and the self-test execution result checker 1-2, etc. When an error occurs from chk2, the input data IDATA supplied to the whole or a part of the semiconductor integrated circuit is fixed at "H" level, the supply is stopped, and the reset signal RS
Input data IDA to the semiconductor integrated circuit again by T
It will restart the supply of TA.

The data supply stop circuit 7 has a structure similar to that of the first embodiment for supplying a clock pulse to the latches or flip-flops of all or part of the semiconductor integrated circuit when an abnormality occurs. It is also possible to fix the H ″ level so that the state transition of all or part of the semiconductor integrated circuit is not changed.

With such a structure, a reliability test such as a life test can be performed by a simple procedure, as in the first embodiment.

In the semiconductor integrated circuits of the first, second, and third embodiments, the supply of the clock pulse, the power supply, or the test pattern is stopped at the time of failure occurrence in the reliability test. When a failure occurs in the circuit, the failure location and the failure cause can be reliably analyzed.

[0045]

As described above, according to the semiconductor integrated circuit of the first and second features of the present invention, the abnormality detecting means detects a predetermined abnormality, and when the abnormality is detected, the clock is stopped. The clock pulse supplied to all or part of the semiconductor integrated circuit by means of "H" level or "L"
As the level is fixed, the supply is stopped, and the supply of the clock pulse to all or part of the semiconductor integrated circuit is restarted by the reset signal from inside and outside the semiconductor integrated circuit. If we draw the time course of, the total current consumption will decrease by a constant current each time one semiconductor integrated circuit fails,
It is possible to predict the time until the initial failure disappears and the time until the wear failure occurs, and it is possible to test with a relatively small amount of sample by a simple procedure, so that the evaluation efficiency is not reduced. It is possible to provide a semiconductor integrated circuit capable of improving the evaluation efficiency of the reliability test without lowering the reliability of the evaluation data even in the case of a short circuit failure.

According to the semiconductor integrated circuit of the third and fourth aspects of the present invention, the abnormality detecting means detects a predetermined abnormality, and when the abnormality is detected, the semiconductor integrated circuit is operated by the power supply stopping means. In the reliability test, the power supply to all or part of the circuit is stopped, and the power supply to all or part of the semiconductor integrated circuit is restarted by the reset signal from inside and outside the semiconductor integrated circuit. , It is possible to improve the evaluation efficiency, and when a failure such as a short-circuit between the power supply and the ground occurs in one test semiconductor integrated circuit, the power supply voltage supplied to the other test semiconductor integrated circuits is reduced. It is possible to provide a semiconductor integrated circuit that can improve the reliability of evaluation data without the need.

Further, according to the semiconductor integrated circuit of the fifth and sixth features of the present invention, the abnormality detecting means detects a predetermined abnormality, and when the abnormality is detected, the semiconductor integrated circuit is performed by the data supply stopping means. Input data supplied to the whole or part of the circuit is fixed at "H" level or "L" level to stop the supply, or the state transition of the whole or part of the semiconductor integrated circuit is affected to the input data. Moreover, since the supply of the input data to all or part of the semiconductor integrated circuit is restarted by the reset signal from inside and outside the semiconductor integrated circuit, it is possible to improve the evaluation efficiency in the reliability test. A possible semiconductor integrated circuit can be provided.

According to the semiconductor integrated circuit of the present invention,
In the reliability test, the supply of the clock pulse, power supply, or test pattern is stopped at the time of failure occurrence, so it is possible to reliably analyze the failure location and cause when a failure occurs in the semiconductor integrated circuit under test. A possible semiconductor integrated circuit can be provided.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the principle of the present invention. FIG. 1 (1) is claims 1 and 2, FIG. 1 (2) is claims 3 and 4, and FIG.
Are claims 5 and 6.

FIG. 2 is a circuit diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 3 is a timing chart explaining the operation of the semiconductor integrated circuit of the first embodiment.

FIG. 4 is a configuration diagram of a jig for a life test of a semiconductor integrated circuit.

FIG. 5 is a flowchart illustrating a processing procedure of a life test of the present invention.

FIG. 6 is a characteristic curve of operating time-current consumption in the life test of the first embodiment.

7 (1) is a circuit diagram of a semiconductor integrated circuit according to a second embodiment of the present invention, and FIG. 7 (2) is a circuit diagram of a semiconductor integrated circuit according to a third embodiment of the present invention. is there.

FIG. 8 is a failure curve in a life test of a conventional semiconductor integrated circuit.

FIG. 9 is a flowchart illustrating a processing procedure of a conventional semiconductor integrated circuit life test.

[Explanation of symbols]

 1-1 to 1-n abnormality detection means 1-1 parity error checker 1-2 self-test execution result checker 3 clock stop circuit (clock stop means) 5 power supply stop means 7 data supply stop means 11, 21, 31 3 inputs OR gate 13, 23, 33 D-type flip-flop 15, 35-1 to 35-m-12 2-input OR gate SW switch CLOCK External input clock (pulse) CLK Internal clock (pulse) RST Reset signal chk1 to chkn Error occurrence signal (Abnormality detection signal) Vcc power supply chk1 parity error signal chk2 self-test error signal DATA input data D0 to Dm-1 input data IDATA internal data ID0 to IDm-1 internal data T1 to Tn + 1 cycle 51 power supply 53 pattern generator 5 Rack 57 ammeter 61 subjects a semiconductor integrated circuit (DUT) I tested the semiconductor integrated circuit 1 consumption current per

Claims (6)

[Claims] 1. At least one abnormality detecting means for detecting a predetermined abnormality, and a clock pulse supplied to all or part of the semiconductor integrated circuit based on a detection result of the abnormality detecting means.
A semiconductor integrated circuit having a clock stop means for stopping the supply at a fixed H "level or" L "level. 2. The clock stopping means restarts supply of a clock pulse to all or part of the semiconductor integrated circuit in response to a reset signal from inside or outside the semiconductor integrated circuit. Semiconductor integrated circuit. 3. At least one abnormality detecting means for detecting a predetermined abnormality, and power supply stopping means for stopping the power supply to all or part of the semiconductor integrated circuit based on the detection result of the abnormality detecting means. A semiconductor integrated circuit having. 4. The power supply stopping means restarts power supply to all or part of the semiconductor integrated circuit in response to a reset signal from inside or outside the semiconductor integrated circuit. Semiconductor integrated circuit. 5. At least one abnormality detecting means for detecting a predetermined abnormality, and input data supplied to all or part of the semiconductor integrated circuit based on a detection result of the abnormality detecting means is "H".
It is characterized in that it has a data supply stopping means for fixing the level or the "L" level and stopping the supply or preventing the state transition of the whole or a part of the semiconductor integrated circuit from affecting the input data. Semiconductor integrated circuit. 6. The data supply stopping means restarts the supply of input data to all or part of the semiconductor integrated circuit in response to a reset signal from inside or outside the semiconductor integrated circuit. The semiconductor integrated circuit described.