JPH05341001A - Data judging circuit for simultaneous judgment of two pieces of data - Google Patents

Abstract

PURPOSE:To make mode setting for two selectors so that a control circuit emits their respective pieces of data and to enter the two judgement data pieces into a plurality of judging circuits upon being distributed. CONSTITUTION:An FF 1 stores an expected value, while a counter 2 makes frequency dividing of a clock 12. A frequency dividing circuit 3 stores the output of the FF 1 at the timing of counter 2, while a control circuit 4 emits clocks 41-44 and mode changeover signals 45, 46. A selector 5 selects the output of the circuit 3. while FF's 6A, 6B store pieces of data 14, 15. Selectors 7A, 7B emit data 15 or data 15. FF's 8A-8D are for the expected value retiming. while FF7S 8E-8H are for judgement data retiming. Judging circuits 9A-9D compare the judgement data 14, 15 with the expected value 11, and the results are emitted one by one.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data judging circuit of an IC tester for judging the quality by comparing an output from a test device with an expected value.

[0002]

2. Description of the Related Art Next, the structure of a conventional data decision circuit will be described with reference to FIG. 6, 1 is an FF for sampling expected value, 2 is a counter for generating a clock for expected value retiming, 21 is an FF for sampling judgment data,
Reference numeral 22 is a counter for generating a clock for judgment data retiming, 8A to 8D are FFs for expected value retiming, and 8E to
Reference numeral 8H is an FF for determination data retiming, and 9A to 9D are determination circuits.

The FF1 of FIG. 6 inputs the expected value 11, inputs the clock 12 to the counter 2, and inputs the expected value 11 to the FFs 8A to 8D at the timing of the counter 2. FF21
Inputs the judgment data 17, inputs the strobe signal 16 to the counter 22, and the FF8 at the timing of the counter 22.
The judgment data 17 is input to E to 8H. Judgment circuit 9A-
9D compares the expected value 11 and the determination data 17 with each other, and sequentially outputs the determination results.

Next, the timing chart of FIG. 6 will be described with reference to FIG. 7A shows the waveform of the clock 12, and FIG. 7A shows the waveform of the expected value 11 input to the FF1. Figure 7
C is the output waveform of FF1, and FIGS.
Is the timing output. Fig. 7 ~ FF is FF8A ~ 8D
It is the waveform of the expected value 11 output from. Since the counter 2 in FIG. 6 has four outputs, the expected value 11 is input to every four FFs 8A to 8D.

FIG. 7 shows the waveform of the strobe signal 16, FIG. 7 shows the waveform of the judgment data 17 input to the FF 21, and FIG. 7 shows the output waveform of the FF 21. 7 is a waveform output from the counter 22, and FIGS.
It is a waveform of the determination data 17 which is input to the FFs 8E to 8H every four and is sequentially input to the determination circuits 9A to 9D.

[0006]

In FIG. 6, another identical circuit must be provided in order to determine two signals at the same time. According to the present invention, when the two judgment data are judged, the control circuit sets the mode of the two selectors so that the control circuit outputs different data, and the control circuit controls the timing of the expected value and the judgment data input to the judgment circuit. Then 2
An object of the present invention is to provide a data judgment circuit for judging two judgment data simultaneously by distributing one judgment data to a plurality of judgment circuits and inputting the judgment data.

[0007]

To achieve this object, according to the present invention, an FF1 for storing an expected value 11 at a timing of a clock 12, a counter 2 for dividing the clock 12 and an output of the FF1 for a counter 2 are provided. And a control circuit 4 which inputs the mode signal 13 and outputs the clocks 40 to 44 at the timing of the strobe signal 16 and outputs the mode switching signal 45 and the mode switching signal 46. The selector 5 that outputs the output of the frequency circuit 3 at the timing of the clock 40 of the control circuit 4, and the F that stores the data 14 at the timing of the strobe signal 16
F6A, FF6B that stores data 15 at the timing of strobe signal 16, and selector 7 that outputs data 14 or data 15 according to the mode switching signal 45 of control circuit 4 by using the outputs of FF6A and FF6B as inputs
A, FF8A, FF8B, and FF8 that store the outputs of the selector 7B and the selector 5, which receive the output of the FF6A and the output of the FF6B as input and output the data 14 or the data 15 by the mode switching signal 46 of the control circuit 4, respectively.
C, FF 8D, and FF that receives the output of the selector 7A
8E and FF8G, and F that receives the output of the selector 7B
F8F and FF8H, the output of FF8A and FF8E is input by the clock 41 of the control circuit 4, the determination circuit 9A that outputs the determination result, and the output of FF8B and FF8F is input by the clock 42 of the control circuit 4, and the determination result is The output of FF8C and FF8G is input by the determination circuit 9B which outputs and the clock 42 of the control circuit 4, and the output of FF8D and FF8H is input by the determination circuit 9C which outputs the determination result and the clock 44 of the control circuit 4, The control circuit 4 is provided with a clock 4
1 and the clock 42 are operated at the same timing, and the clock 43 and the clock 44 are operated at the same timing.

[0008]

Next, the structure of the data judging circuit according to the present invention will be described with reference to FIG. Reference numeral 3 in FIG. 1 is a frequency dividing circuit for outputting the expected value 11 at a timing divided by 4, and 4 is a clock 40.
Control circuits for controlling the timings of ~ 44, selectors for selecting the output of the frequency dividing circuit 3 by the clock 40 of the control circuit 4, 6A and 6B for FF for sampling the judgment data,
7A and 7B are selectors that select which of the judgment data 14 and 15 is to be output according to the mode controlled by the signal of the control circuit 4, and 8A to 8D are clocks 41 to 44 of the control circuit 4 for selecting the selector 5. F to input output
In F and 8E to 8H, the judgment data is the clock 4 of the control circuit 4.
1 to 44, the FF 1, the counter 2, and the determination circuits 9A to 9D are the same as those in FIG.

Next, the configuration of the control circuit 4 will be described with reference to FIG. 8A is a CPU, and 4B to 4E are counters. In FIG. 8, the mode signal 13 from the outside is input to the CPU 4A. The CPU 4A inputs a control signal to each of the counters 4B to 4E by the mode signal 13, and outputs clocks 40 to 44 whose timings are controlled by the counters 4B to 4E at the timing of the strobe signal 16. The control circuit 4 also outputs the mode switching signals 45 and 46.

In FIG. 1, when there is one judgment data, for example, when only the data 14 is judged, the selectors 7A and 7A
The mode is input to the control circuit 4 so that both B output the data 14, and the data 14 is input to the FFs 8E to FF8H. When there are two judgment data, for example, the selector 7A
The data 14 is input to the selector 7 and the data 15 is input to the selector 7B.
The mode is set in the control circuit 4 so as to input. As a result, the data 14 is input to FF8E and FF8G,
Data 15 is input to FF8F and FF8H.

The outputs of the selector 4 are uniformly connected to the FFs 8A to FF8D, and the clocks 41 to 41 of the control circuit 4 are connected.
Enter 44. FF8E to FF8H are FF8A to F
The clock 41 of the control circuit 4 is synchronized with F8D.
The data 14 and the data 15 are input according to ~ 44. The determination circuits 9A to 9D input the expected value 11 and the determination data 14 and 15 and output the determination result.

Next, the operation of FIG. 1 will be described with reference to the time charts of FIGS. 2 and 3. FIG. 2 shows the operation when there is one piece of determination data. 2A shows the waveform of the clock 12, and FIG. 2A shows the data of the expected value 11 input to the FF1. FIG. 2C shows the output waveform of FF1. Figure 2
2 is a clock waveform that is output from a to d by dividing the clock 12 by 4. The expected values output from the Q1 to Q4 terminals of the frequency dividing circuit 3 at the timings in FIGS. 1
The data of 1 is input to the D1 to D4 terminals of the selector 5, respectively. 2 shows the waveform of the select signal of the selector 5, which is output at the timing of the strobe signal 16 input to the control circuit 4. FIG. 2C shows the output of the selector 5, which outputs the data of the expected value 11 at the timing of FIG. 2 shows a waveform of the strobe signal 16, which is a timing signal for the FF 6A, FF 6B and the control circuit 4.

FIG. 2 shows the waveform of the judgment data 14 input to the FF 6A or FF 6B, and FIG. 2 shows the FF 6A or FF 6B output at the timing of the strobe signal 16.
Is the output data of. Since there is only one judgment data, FF6
One of A and FF6B is not used. 2 is the control circuit 4
FIG. 7 is a waveform diagram of a select signal output from the selector 7A and input to the selector 7A. Here, a waveform when the data 14 is selected is shown as an example. FIG. 3T shows output data of the selectors 7A and 7B.

3A to 3C are output from the control circuit 4, and F
The waveforms of the clocks 41 to 44 input to F8A to 8H are only the determination data 14, so 1 is set in FF8A to 8H.
One judgment data 14 is judged. 3 to 4 are data of the expected value 11 input to the determination circuits 9A to 9D, respectively, and the expected value 11 is input at the timing when the strobe signal 16 is divided by 4 by the clocks 41 to 44 of the control circuit 4. 3A to 3F are waveforms of the determination data 14 input to the determination circuits 9A to 9D, respectively, and the control circuit 4 inputs the determination data 14 with clocks 41 to 44 obtained by dividing the strobe signal 16 by four. FIG. 3 shows the output data of the decision circuits 9A and 9C, and FIG. 3 shows the output data of the decision circuits 9B and 9D. In this way, the determination circuit 9A
9D to judgment data 14 and the corresponding expected value 11
Is input and the determination results are sequentially output.

Next, the operation for simultaneously determining the two determination data 14 and 15 will be described with reference to FIGS. 4A to 4E are the same as FIG. 4 shows the waveform of the data 14 input to the FF 6A, and FIG. 4 shows the waveform of the data 15 input to the FF 6B. FIG. 4 shows the output waveform of the FF 6A output at the timing of the strobe signal 16, and FIG. 4T shows the output waveform of the FF 6B output at the timing of the strobe signal 16. FIG. 5G is a selection signal of the selector 7A and is a state diagram in which the data 14 is being selected. FIG. 5A shows a state where the select signal of the selector 7B is selected and the data 15 is selected.

FIG. 5D shows the output data of the selector 7A, and FIG. 5N shows the output data of the selector 7B. As shown in FIGS. 5 and 5, data 14 and data 15 are output to the selectors 7A and 7B, respectively. Figure 5
H is the waveform of the clocks 41 to 44 output from the control circuit 4 and input to the FFs 8A to 8H.
Since there are two 15, the FFs 8A to 8H are divided and the two determination data 14 and 15 are determined.

5A to 5F show the expected value 11 input to the decision circuits 9A to 9D. The control circuit 4 divides the strobe signal 16 into two clocks 41 and 42 to determine the decision circuit 9A.
9B is operated and the decision circuits 9C and 9D are set to the same clock 4
Operate at 1.42. 5 is a decision circuit 9A-9
The determination data is input to D. The control circuit 4 operates the determination circuits 9A and 9B with clocks 43 and 44 obtained by dividing the strobe signal 16 by two, and operates the determination circuits 9C and 9D with the same clocks 43 and 44. FIG. 5A shows the determination circuit 9
A is the output data of the determination circuit 9C, and FIG. 5 is the output data of the determination circuit 9B and the determination circuit 9D.

Of the judgment circuits 9A to 9D, the judgment circuit 9A
When the 9B and the judgment circuits 9C and 9D are moved as two sets at the same time for judgment, both the expected value 11 and the judgment judgment data are fixed for only two cycles, so the set value of the judgment point (strobe signal 16) can be limited. .. Therefore, the expected value 11 is read at the timing of the clock 12, and the timing of the expected value 11 input to the selector 5 by the strobe signal 16 of the control circuit 4 is retaken so that the determination points are not limited.

[0019]

According to the present invention, when the two judgment data are judged, the control circuit 4 sets the mode of the two selectors so as to output different data, and the expected value 11 to be inputted to the judgment circuit is set. Since the timing of the determination data is controlled by the control circuit and the two determination data are distributed and input to the plurality of determination circuits, the two determination data can be determined simultaneously.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a data determination circuit according to the present invention.

FIG. 2 is a time chart when there is one determination data in FIG.

FIG. 3 is a time chart following FIG.

FIG. 4 is a time chart when there are two determination data in FIG.

FIG. 5 is a time chart following FIG.

FIG. 6 is a configuration diagram of a data determination circuit according to a conventional technique.

FIG. 7 is a time chart of FIG.

8 is a configuration diagram of a control circuit 4 in FIG.

[Explanation of symbols]

 1 FF 2 counter 3 frequency dividing circuit 4 control circuit 5 selector 6A / 6B FF 7A / 7B selector 8A-8H FF 9A-9D determination circuit

Claims (1)

[Claims] 1. A first FF (1) which stores an expected value (11) at a timing of a first clock (12), a counter (2) which divides the frequency of the first clock (12), The frequency divider circuit (3) that stores the output of FF (1) of 1 at the timing of the counter (2) and the mode signal (13) as input, and the second clock (40) at the timing of the strobe signal (16). , A third clock (41), a fourth clock (42), a fifth clock (43) and a sixth clock (44) are output to output the first mode switching signal (45) and the second mode. The control circuit (4) that outputs the switching signal (46) and the output of the frequency divider circuit (3) are connected to the first clock (4) of the control circuit (4).
The first selector (5) that outputs at the timing of 0), the second FF (6A) that stores the first data (14) at the timing of the strobe signal (16), and the second data (15). Is stored at the timing of the strobe signal (16), the output of the second FF (6A) and the output of the third FF (6B) are input, and the third of the control circuit (4) By the mode switching signal (45) of 1,
The second selector (7A) that outputs the first data (14) or the second data (15), the output of the second FF (6A) and the output of the third FF (6B) are input, By the second mode switching signal (46) of the control circuit (4),
A third selector (7B) that outputs the first data (14) or the second data (15) and a fourth F that stores the output of the first selector (5), respectively.
F (8A), 5th FF (8B), 6th FF (8C), 7th FF
(8D) and the eighth FF (8E) which receives the output of the second selector (7A)
And the ninth FF (8G), and the tenth FF (8G) which receives the output of the third selector (7B).
F) and the 11th FF (8H), and the 3rd FF (8H) by the 3rd clock (41) of the control circuit (4).
A) and the output of the 7th FF (8E) as input, the 1st judgment circuit (9A) which outputs the judgment result, and the 4th FF (by the 4th clock (42) of the control circuit (4) 8
B) and the output of the eighth FF (8F) as input, the second determination circuit (9B) that outputs the determination result, and the fifth clock (43) of the control circuit (4) causes the fifth FF ( 8
C) and the output of 9th FF (8G) are input, the 3rd judgment circuit (9C) which outputs the judgment result, and the 6th FF (6th FF 8
D) and the output of the 10th FF (8H) are input, and the 4th judgment circuit (9D) which outputs a judgment result is provided. The control circuit (4) is the 3rd clock (41) and the 4th Clock (4
A data judging circuit for judging two data at the same time, characterized in that 2) is operated at the same timing and the fifth clock (43) and the sixth clock (44) are operated at the same timing.