JPH05335946A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To easily converge a loop disturbance without need of fine-adjustment of a gain constant of a gain constant circuit even when an input signal of a PLL circuit (phase locked loop circuit) is fluctuated. CONSTITUTION:The PLL circuit outputting a clock signal synchronously with an input signal is featured to be provided with a phase comparator circuit 11 outputting a voltage proportional to a phase difference between the input signal and the clock signal, a gain constant circuit 12 receiving an output of the phase comparator circuit 11, an LPF 13 receiving an output of the gain constant circuit 12, a VCO 14 generating a clock signal whose frequency is controlled in response to an output level of the LPF 13 and giving it to the phase comparator circuit 11, and a frequency detection circuit 16 counting a mean frequency of the input signal based on the clock signal, discriminating whether the frequency of the synchronization clock is a prescribed value or below or a prescribed value or over with respect to the input signal, and controlling the output voltage of the phase comparator circuit 11 depending on the result of discrimination.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit (PLL circuit), and more particularly to a frequency detection circuit used for quickly converging the loop when the capture range of the phase comparison circuit is narrow. It relates to a PLL circuit.

[0002]

2. Description of the Related Art FIG. 6 shows a PLL having a frequency detection circuit.
A conventional example of a circuit is shown.

In this PLL circuit, a phase comparison circuit (PD) 61 compares the phases of an input signal (pulse signal) and an output signal (synchronous clock) of a voltage controlled oscillator circuit (VCO) 68, and the positions of both signals are compared. It outputs a voltage proportional to the phase difference. The output signal of the phase comparison circuit 61 is the first gain constant (Kp) for determining the loop gain.
It becomes one input of the adding circuit 66 via the circuit 62.

The frequency dividing circuit 63 receives an input signal (pulse signal).
Is divided by N. Frequency detection circuit (FD) 64
Is the average frequency of the output signal of the frequency dividing circuit 63
The output signal of the CO 68 is used as a reference for counting, and a signal proportional to the counting result is output in, for example, a PWM (pulse width modulation) format. The output signal of the frequency detecting circuit 64 becomes the other input of the adding circuit 66 through the second gain constant (Kf) circuit 65 for determining the loop gain.

The output signal of the adder circuit 66 is supplied as a control voltage of the VCO 68 through a low pass filter (LPF) 67 for determining the loop characteristic. This V
The CO 68 generates a clock signal whose oscillation frequency is controlled according to the control voltage level and supplies it to the phase comparison circuit 61.

The phase comparison circuit 61, the first gain constant circuit 62, the addition circuit 66, the LPF 67 and the VCO 68.
Are connected in a loop to form a phase locked loop, and in the steady state (phase locked state), the VCO 68 outputs a clock signal synchronized with the input signal. FIG. 7A shows
The detection characteristics of the phase comparison circuit 61 are shown.

As can be seen from this characteristic, the detected phase difference is −
Output voltage of -Vp when π, + Vp when + π
And outputs a voltage that linearly changes within the range of -Vp to + Vp in response to a linear change within the range of -π to + π. FIG. 7B shows the detection characteristic of the frequency detection circuit 64.

As can be seen from this characteristic, the phase comparison circuit 6
1, the count value Ct is detected when the frequency of the synchronous clock is outside the capture range on the high side with respect to the input signal.
If ≦ (M−m), and the frequency of the sync clock is lower than the capture range on the low frequency side of the input signal, C
t ≧ (M + m), and in the region within the capture range, (M−m) <Ct <(M + m), the output becomes zero (high impedance state), and in the steady state, C
t = M. The above (M-m) <Ct <(M + m)
The area of is a PD operation area in which the loop gain of the phase locked loop is determined according to the output of the phase comparison circuit 61 and is controlled to be in the phase locked state.

On the other hand, in a region where the frequency of the synchronous clock is higher than that of the input signal, Ct ≦ (M−m) and a voltage (−Vf or less) proportional to the count value is output. Similarly, in the region where the frequency of the synchronous clock is low with respect to the input signal, (M + m) ≦ Ct, and a voltage (+ Vf or more) proportional to the count value is output.

Thus, Ct ≦ (M−m) or (M +
In the region where m) ≦ Ct, the FD is controlled so that the loop gain of the phase locked loop is determined according to the output of the frequency detection circuit 64 and the phase locked loop shifts to the PD operating region.
This is the operating area.

By the way, in recent years, digitalization of signal processing has progressed, and a PLL circuit is applied to a digital time base corrector (TBC) or the like for extracting a bit clock of digital data and absorbing fluctuations in the time base direction. Think about when. In this case, when the conventional PLL circuit as described above is used, it is necessary to finely adjust the addition ratio of the gain constant Kf of the gain constant circuit 63 and the gain constant Kp of the gain constant circuit 62. Further, if the gain constants Kf and Kp are not well balanced, there is a problem that the convergence of the loop is deteriorated when the input signal fluctuates.

[0012]

As described above, in the PLL circuit having the conventional frequency detection circuit, it is necessary to finely adjust the addition ratio of each gain constant of the two gain constant circuits, and the input signal fluctuates. There was a problem that the convergence of the loop deteriorated at times.

The present invention has been made to solve the above problems, and even when the input signal fluctuates, the loop can be easily converged without requiring fine adjustment of the gain constant of the gain constant circuit. An object is to provide a phase locked loop circuit.

[0014]

A phase locked loop circuit of the present invention compares a phase of an input signal and a clock signal, and outputs a voltage proportional to the phase difference between the two signals, and a phase comparison circuit for this phase comparison circuit. A gain constant circuit that amplifies the output signal of the circuit by a predetermined constant, a low-pass filter to which the output signal of this gain constant circuit is input, and a frequency depending on the voltage level of the output signal of this low-pass filter. Outputs a controlled clock signal and supplies it to the phase comparison circuit,
In a steady state, a voltage controlled oscillator circuit that outputs a clock signal synchronized with the input signal, and the average frequency of the input signal or its frequency-divided signal is counted with the clock signal as a reference, and the input signal or its frequency-divided signal is calculated. On the other hand, it is determined whether the frequency of the synchronous clock is in a region below a predetermined value or above a predetermined value, and the output voltage of the phase comparator circuit is set to a negative or positive constant value according to the result of this determination. And a frequency detecting circuit for controlling.

[0015]

In the operating region of the frequency detection circuit, polarity determination is performed as to whether the frequency of the synchronizing clock is lower than the predetermined value or lower than the input signal or higher than the predetermined value.
Depending on the polarity discrimination result, the output of the phase comparison circuit is controlled so as to be a constant negative or positive voltage in the direction of converging the phase locked loop. Converges quickly. Therefore, even when the input signal fluctuates, the loop can be easily converged without requiring fine adjustment of the gain constant of the gain constant circuit.

If the output of the phase comparison circuit is controlled so as to have the maximum value in the output characteristics, the output of the phase comparison circuit in the operation area of the frequency detection circuit and the output of the phase comparison circuit in the operation area of the phase comparison circuit are Because it has continuity,
The phase locked loop converges more smoothly. Further, by using the integral type low-pass filter, it is possible to effectively utilize the entire operating range of the voltage controlled oscillator circuit.

[0017]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows a PLL circuit according to an embodiment of the present invention.

In this PLL circuit, the phase comparison circuit (PD) 11 compares the phases of the input signal (pulse signal) and the output signal (synchronous clock) of the VCO, and outputs a voltage proportional to the phase difference between the two signals. To do. The gain constant (Kp) circuit 12 amplifies the output voltage of the phase comparison circuit 11 by a predetermined constant multiple and is used to determine the loop gain. The integral type LPF 13 is
The output signal of the gain constant circuit 12 is input and the DC component thereof is extracted and has a role of determining the loop characteristic. The VCO 14 generates a clock signal whose frequency is controlled according to the voltage level of the output signal of the LPF 13 and supplies it to the phase comparison circuit 11, and outputs a clock signal synchronized with the input signal in a steady state. is there.

The frequency dividing circuit 15 divides the input signal by N and is used as necessary. The frequency detection circuit (FD) 16 counts the average frequency of the input signal from the frequency dividing circuit 15 with the clock signal as a reference, and determines whether the frequency of the synchronous clock is a predetermined value or less with respect to the input signal. It is determined whether the area is equal to or more than the value. Then, the frequency detection circuit 16 determines the negative or positive constant voltage in the direction in which the phase comparison circuit output converges in the phase locked loop (in this example, the phase difference vs. output of the phase comparison circuit 11 according to the determination result). The voltage is controlled to be the minimum value or the maximum value in the characteristic). As an example of this control, the output of the phase comparison circuit 11 is set to -Vp.
The voltage is switched to that of the power supply (not shown) or the + Vp power supply (not shown). The phase comparison circuit 11, the gain constant circuit 12, the LPF 13 and the VCO 14 are connected in a loop to form a phase locked loop. Figure 2 (a) shows
The detection characteristics of the phase comparison circuit 11 are shown.

As can be seen from this characteristic, the detected phase difference is −
Output voltage of -Vp when π, + Vp when + π
And outputs a voltage that linearly changes within the range of -Vp to + Vp in response to a linear change within the range of -π to + π. FIG. 2B shows the control characteristic of the frequency detection circuit 16.

As can be seen from this characteristic, the phase comparison circuit 1
1, the count value Ct is detected when the frequency of the synchronous clock is outside the capture range on the high side with respect to the input signal.
If ≦ (M−m), and the frequency of the sync clock is lower than the capture range on the low frequency side of the input signal, C
t ≧ (M + m), and in the region within the capture range, (M−m) <Ct <(M + m), the output becomes zero (high impedance state), and in the steady state, C
t = M. The above (M-m) <Ct <(M + m)
The area (2) is a PD operation area in which the loop gain of the phase locked loop is determined according to the output of the phase comparison circuit 11 and controlled so as to be in the phase locked state.

On the other hand, in the region where the frequency of the synchronous clock is high with respect to the input signal, Ct ≦ (M−m) and a constant equal to the minimum value (−Vp) on the output characteristic of the phase comparison circuit 11. Output voltage. Similarly, in the region where the frequency of the synchronous clock is low with respect to the input signal, (M + m) ≦ C
It becomes t and the maximum value (+
It outputs a constant voltage equal to Vp).

Thus, Ct≤ (M-m) or (M +
In the region where m) ≦ Ct, the output of the phase comparison circuit 11 is −
The FD operation region is controlled by the output of the frequency detection circuit 16 so as to be Vp or + Vp and is controlled so that the phase locked loop shifts to the PD operation region. Next, the operation of the PLL circuit of the above embodiment will be described.

The frequency detection circuit 16 determines whether it is the FD operation region or the PD operation region, and further, the FD
In the operating region, polarity determination is performed to determine whether the frequency of the synchronous clock is low or high with respect to the input signal. When the determination result is the FD operation area,
According to the polarity determination result, the output of the phase comparison circuit 11 is controlled so as to have a constant negative or positive voltage in the direction of converging the phase locked loop. The loop converges quickly.

In this case, the output of the phase comparison circuit 11 is controlled so as to have the maximum value (-Vp or + Vp) on the output characteristics, and the output of the phase comparison circuit and the PD in the FD operation region are controlled.
Since the output of the phase comparison circuit in the operating region has continuity, the convergence of the phase locked loop in the transient state becomes extremely good, and the phase locked loop converges more smoothly. Therefore, even when the input signal fluctuates, the loop can be easily converged without requiring fine adjustment of the gain constant of the gain constant circuit 12 of the PLL circuit.

The LPF 13 can effectively utilize the entire operation range of the VCO 14 and converge the phase locked loop within the operation range of the VCO 14 by using an integral type LPF as shown in FIG. 3, for example. it can. In FIG. 3, R1 and R2 are resistors, c is a capacitor, and 30 is an operational amplifier circuit. FIG. 4 shows an example in which the PLL circuit of the present invention is applied to a digital time base correction circuit.

In FIG. 4, the input signal is a video signal demodulated from an optical pickup of a laser disk player, or a video signal in a video tape recorder or the like. The input video signal is converted into a digital signal by an analog-digital conversion circuit (ADC) 41 and then written in a time axis correction RAM (random access memory) 42 for absorbing jitter in the time axis direction. The digital signal read from the time axis correction RAM 42 is converted into an analog signal by the digital-analog conversion circuit (DAC) 43 and becomes an output video signal. The clock used for the analog-digital conversion and RAM writing is a synchronous clock signal synchronized with the input video signal,
It is generated by the L circuit 50.

The PLL circuit 50 has, as a basic configuration,
Phase comparison circuit (PD) 1 as described above with reference to FIG.
1. Gain constant circuit (not shown), LPF 13, VCO
14, a frequency detection circuit (FD) 16 and a sync separation circuit 44. FIG. 5A shows a PLL circuit 5
2 shows the detection characteristic of the phase comparison circuit 11 within 0, and FIG.
It has the characteristics described above with reference to (a). Figure 5
2B shows the detection characteristic of the frequency detection circuit 16 in the PLL circuit 50, which has the control characteristic as described above with reference to FIG.

The video signal converted into a digital signal is
The phase is input to the phase comparison circuit 11 and the sync separation circuit 44
And the horizontal sync signal is separated. The frequency detection circuit 16 counts the horizontal synchronizing signal with the synchronizing clock signal as a reference to determine the PD operation area. For example NTSC
In the case of the video signal of the system, its color carrier frequency fsc
If the frequency of the synchronous clock signal is set to four times (3.58 MHz) (14.32 MHz), the frequency detection circuit 1
The count value of 6 becomes M = 910. In this case, the PD operation area is M = 909 to 9 in consideration of the deviation of the count value of ± 1.
11, and the FD operation region is M ≦ 908, 912 ≦ M.

In the above digital time axis correction circuit, even when the input signal fluctuates when a transient operation such as an address search operation is performed in the laser disk player, the gain constant of the gain constant circuit is finely adjusted. The loop can be easily converged without the need, and the performance of the player can be improved.

[0031]

As described above, according to the PLL circuit of the present invention, even when the input signal fluctuates, the loop can be easily converged without requiring fine adjustment of the gain constant of the gain constant circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a PLL circuit of the present invention.

FIG. 2 is a diagram showing characteristics of a phase comparison circuit and a frequency detection circuit in FIG.

FIG. 3 is a circuit diagram showing an example of an LPF in FIG.

FIG. 4 is a block diagram showing an example of a digital time base correction circuit to which the PLL circuit of the present invention is applied.

5 is a diagram showing the characteristics of the phase comparison circuit and the frequency detection circuit in FIG.

FIG. 6 is a block diagram showing a conventional PLL circuit.

7 is a diagram showing the characteristics of the phase comparison circuit and the frequency detection circuit in FIG.

[Explanation of symbols]

11 ... Phase comparison circuit, 12 ... Gain constant circuit, 13 ... L
PF, 14 ... VCO, 15 ... Frequency divider circuit, 16 ... Frequency detection circuit.

Claims (3)

[Claims] 1. A phase comparison circuit that compares the phases of an input signal and a clock signal and outputs a voltage proportional to the phase difference between the two signals, and a gain that amplifies the output voltage of this phase comparison circuit by a predetermined constant multiple. A constant circuit, a low-pass filter to which the output signal of the gain constant circuit is input, a clock signal whose frequency is controlled according to the voltage level of the output signal of the low-pass filter, and the phase comparison A voltage-controlled oscillator circuit that supplies a circuit and outputs a clock signal in synchronization with the input signal in a steady state; and counts the average frequency of the input signal or a frequency-divided signal thereof with the clock signal as a reference. With respect to the frequency-divided signal, it is determined whether the frequency of the synchronous clock is in a region equal to or lower than a predetermined value or in a region equal to or higher than a predetermined value. Phase locked loop circuit characterized by comprising a frequency detecting circuit for controlling the output voltage of the phase comparator circuit a negative or positive constant value. 2. The phase locked loop circuit according to claim 1, wherein the frequency detection circuit sets the output voltage of the phase comparison circuit to a minimum value or a maximum value on the phase difference vs. output characteristic according to the result of the determination. A phase-locked loop circuit characterized by being controlled so as to be equal to. 3. The phase-locked loop circuit according to claim 1, wherein the low-pass filter is an integral type low-pass filter.