JPH05335940A - Non-integer frequency divider circuit - Google Patents

Abstract

PURPOSE:To attain frequency division with simple circuit configuration even for a non-integer frequency division ratio. CONSTITUTION:A clock frequency divider means 10 at first generates a 1st frequency division clock resulting from a master clock MC divided by a 1st integer being an integral part of a non-integer and a 2nd frequency division clock resulting from frequency-dividing the master clock by a 2nd integer being the sum of 1 and the 1st integer. Either the 1st frequency division clock or the 2nd frequency division clock is selected based on a frequency division signal DS and the selected signal is outputted as an output frequency division clock DCP. The frequency division signal DS is a signal outputted by a frequency division signal generating means 20 and a signal resulting from frequency- dividing the output frequency division clock DCP by a frequency division ratio being a fraction part of the non-integer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency divider circuit used in a transmission device or the like, and more particularly to a non-integer frequency divider circuit having a non-integer frequency division ratio.

In recent years, the global standardization of ISDN (Integrate Services Digital Network) has been changed to CCITT (International Telegraph and Telephone Advisory Committee; Internatio).
nalTelegraph and Telephone Consultative Committe
e) is being promoted. Speed up in this
SONET (Sy
SDH (Synchronous Digital Hierarchy) was established in 1988 based on digital hierarchy such as nchrous Optical NETwork), and NNI was used as an interface inside the communication network.
(Network Node Interface) standardization recommendation was adopted.

Here, the fundamental frequency of SDH, NNI and the like recommended by CCITT is 51.84 [MHz]. On the other hand, the fundamental frequency of the conventional digital hierarchy in Japan and North America is 1.544 [MH
z]. Therefore, in Japan and North America, SDH and NN
When communication is performed in accordance with I or the like, it is necessary to perform frequency conversion with a fundamental frequency such as SDH and NNI.

[0004]

2. Description of the Related Art In a conventional transmission device or the like, when a master clock is frequency-converted from a high frequency to a low frequency,
The frequency is divided at a predetermined frequency division ratio. The frequency division ratio of such a frequency divider circuit is generally an integer value.

By the way, SDH is used as a master clock.
In order to convert the fundamental frequency such as NNI and NNI to the fundamental frequency of digital hierarchy in Japan and North America, the frequency division ratio is 51.84 [MHz] /1.544 [MHz] = 6480/193, which is an integer value. It is not the ratio. For this reason, in the past, in order to perform the above frequency conversion, first, SD
It is necessary to frequency-convert the fundamental frequency such as H and NNI to a high frequency of 193 times, and then perform frequency conversion to a low frequency by a frequency dividing circuit having a frequency division ratio of 6480.

[0006]

However, SDH and N
When the fundamental frequency of NI or the like is converted to a high frequency of 193 times, it becomes 51.84 [MHz] × 193≈10 [GHz], which is a frequency that is almost unrealizable from the viewpoint of the allowable speed of the device. Therefore, there is a problem in that the master clock in the high speed region cannot be divided by a division ratio having a non-integer value.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a non-integer frequency dividing circuit that can perform frequency division with a simple circuit configuration even if the frequency dividing ratio is a non-integer value. And

[0008]

FIG. 1 is a diagram for explaining the principle of the present invention which achieves the above object. The non-integer frequency dividing circuit of the present invention comprises a clock frequency dividing means 10 and a frequency divided signal generating means 20.

The clock dividing means 10 divides the master clock MC by a first integer, which is an integer part of a non-integer value, and a second divided clock by adding 1 to the first integer. And a second frequency-divided clock that is divided by an integer, and selects either the first frequency-divided clock or the second frequency-divided clock based on the frequency-divided signal DS to output the frequency-divided clock. DC
Output as P.

Further, the divided signal generating means 20 divides the output divided clock DCP by the dividing ratio of the fractional part of the non-integer value,
The divided signal DS is output.

[0011]

The clock dividing means 10 first divides the master clock MC by the first integer which is an integer part of the non-integer value, and the first divided clock by adding 1 to the first integer. A second divided clock divided by an integer of 2 is generated. One of the first divided clock and the second divided clock is selected based on the divided signal DS, and is output as the output divided clock DCP. This divided signal DS is a signal output by the divided signal generating means 20,
It is a signal obtained by dividing the output frequency-divided clock DCP by the frequency division ratio of the non-integer decimal part.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a diagram showing an embodiment of the present invention. The non-integer frequency dividing circuit of the present invention is a frequency dividing circuit incorporated in a transmission device and includes a frequency dividing counter 11, a frequency dividing counter 12, a selector 13, a frequency dividing counter 21 and a frequency dividing counter 22. The frequency division counter 11 and the frequency division counter 12
The circuit composed of the selector 13 and the selector 13 corresponds to the clock frequency dividing means 10 of FIG. Similarly, a circuit composed of the frequency division counter 21 and the frequency division counter 22 corresponds to the frequency division signal generation means 20.

The frequency dividing counter 11 outputs the output frequency-divided clock D.
CP is input as a reset signal, and master clock M
C is divided by k and output as a divided clock CP (k). The frequency dividing counter 12 receives the output frequency-divided clock DCP as a reset signal and inputs the master clock MC ((k
The frequency is divided by +1 and output as the divided clock CP (k + 1). The selector 13 selects either the divided clock CP (k) or the divided clock CP (k + 1) based on the divided signal DS and outputs it as the output divided clock DCP.

The frequency division counter 21 has a frequency division reset signal D.
R is input, the output divided clock DCP is divided by p, and (c
/ B) The divided signal DS having a period is output. The frequency division counter 22 frequency-divides the output frequency-divided clock DCP by b and outputs the frequency-divided reset signal DR.

Next, the operation of the non-integer frequency dividing circuit of the present invention will be described. First, the master clock MC is input to the frequency division counter 11 and the frequency division counter 12. The frequency division counter 11 frequency-divides the master clock MC by k and outputs the frequency-divided clock CP (k). Similarly, the frequency division counter 12 frequency-divides the master clock MC by (k + 1) and outputs the frequency-divided clock CP (k + 1). It should be noted that the frequency division counter 11 and the frequency division counter 12 are both reset to "1" when the output frequency division clock DCP is input, and newly count clock pulses to perform frequency division.

Then, the output divided clock CP
(K) and the divided clock CP (k + 1)
Input to 3. The selector 13 outputs one of the divided clocks based on the divided signal DS
Output as P. Specifically, when a low level is input as the divided signal DS, the divided clock CP
(K) is output as the output divided clock DCP, and when a high level is input as the divided signal DS, the divided clock CP (k + 1) is output as the output divided clock DCP.

Further, the output divided clock DCP which is output
Is input to the frequency dividing counter 21 and the frequency dividing counter 22. The frequency division counter 21 frequency-divides the output frequency-divided clock DCP by p and outputs the frequency-divided signal DS. The frequency division counter 21 is reset when the frequency division reset signal DR is input, and newly performs frequency division. Similarly, the frequency division counter 2
2 divides the output divided clock DCP by b and outputs it as a divided reset signal DR.

Therefore, the frequency-divided signal DS output from the frequency-division counter 21 is output as a high-level signal p times during one cycle in which the output frequency-divided clock DCP is frequency-divided by b. That is, the high-level divided signal D is generated every (p / b) cycle.
It means that S is output.

The divided clock CP (k) is selected when the divided signal DS thus output is a low level signal, and the divided clock CP (k) is selected when the divided signal DS is a high level signal.
By selecting and outputting (+1), it is possible to perform frequency division of a non-integer value.

Here, the non-integer frequency division ratio (a / b) can be expressed by the following equation. a / b = k + c / b (1) (where a, b, and c are all integers, k is an integer part of the division ratio, and c / b is a decimal part of the division ratio, If the frequency is divided by the ratio k division: (k + 1) division = (b−c): c (2) on the right side of the above equation (1) (which is a fraction), a non-integer value is obtained. We next prove that the division of can be realized. By modifying the right side of the equation (1), k + c / b = (kb + c) / b = (kb + c + kc-kc) / b = {(c (k + 1) + k (bc)} / b = (k + 1) (c / B) + k (bc) / b (3) where c <(b / 2), the above formula (3)
The first term of (b / c) can be transformed into the following equation.

B / c = p + (q / c) (4) When c> (b / 2), {b / (bc)} of the second term of the above formula (3). Can be transformed into the following equation.

B / (bc) = p + {q / (bc)} (5) where p and q are integers, and p is (b
/ C) is the integer part, and (q / c) is the fractional part of (b / c). If the formula (5) is followed, the frequency division counter 2
It is necessary to invert and output the divided signal DS output from 1.

Therefore, during one cycle of the frequency division by b, the phase is delayed by q clocks to perform frequency division p times by the frequency division circuit (k + 1) and frequency division (bc) times by frequency division circuit k. If you do
It is possible to perform frequency division of a target non-integer frequency division ratio (k + c / b).

FIG. 3 is a time chart showing an example of the operation of the embodiment of FIG. 2, showing the case of the frequency division ratio (12/5). This time chart shows changes of each signal shown in FIG. 2 with the passage of time, and these signals are shown from the top in the master clock MC, the divided clock CP (k),
Divided clock CP (k + 1), divided reset signal DR,
The divided signal DS and the output divided clock DCP are shown. In the figure, “H” indicates a high level signal level, and “L” indicates a low level signal level.

The coefficients for satisfying the above equations (1), (4) and (5) are as follows. That is, since a / b = 12/5 = 2 + (2/5) ... (6), [k = 2, b = 5, c =
2]. Further, since c <(b / 2), [p = 2, q = 1] according to the equation (4). Therefore, in the non-integer frequency divider of the present invention, each variable value is set to [k
= 2, b = 5, c = 2], the frequency division reset signal DR
After inputting, the phase is delayed by one clock and the frequency dividing counter 21 divides the frequency by two.

In the figure, the period from time t31 to time t36 is an example of one cycle of the output divided clock DCP. At time t31, since the frequency division signal DS is a high level signal, the clock pulse of the frequency division clock CP (k + 1) output from the frequency division counter 12 is output as the clock pulse of the output frequency division clock DCP. .. Upon receiving the rising edge of the clock pulse of the output divided clock DCP, the frequency division counter 11 and the frequency division counter 12 initialize the counter value to "1". After that, the frequency division counter 11 and the frequency division counter 12 operate at times t31 and t.
Each time a clock pulse of the output divided clock DCP such as 32, t33, t34, and t35 is input, the counter value is initialized to "1", and counting is newly started.

Further, from time t31, the master clock M
One clock after C, the divided reset signal DR changes from a low level to a high level signal, and the divided signal DS changes from a high level to a low level signal. At this point, the frequency division counter 21 initializes the counter value to "1" in response to the fall of the frequency division reset signal DR. Similarly, the frequency division counter 22 initializes the counter value to "1" in response to the fall of the output frequency division clock DCP.

At time t32, since the frequency division signal DS is a low level signal, the clock pulse of the frequency division clock CP (k) output from the frequency division counter 11 is output as the clock pulse of the output frequency division clock DCP. Has been done. At this point, the frequency division counter 21 and the frequency division counter 2
The counter values of 2 are all "1".

Further, from time t32, the master clock M
One clock after C, the count value of the frequency division counter 21 is "1" in response to the fall of the frequency division reset signal DR.
Is initialized to, and the counter value of the frequency division counter 22 is “2”.
become.

At time t33, since the frequency-divided signal DS is a low level signal as at time t32, the clock pulse of the frequency-divided clock CP (k) output from the frequency-division counter 11 is the output frequency-divided clock DCP. Is output as the clock pulse of. At this point, the frequency division counter 2
The counter value of 2 is "2".

Further, from time t33, the master clock M
One clock after C, the counter value of the frequency division counter 21 is “2” in response to the rising of the frequency division reset signal DR.
And the counter value of the frequency division counter 22 becomes “3”.

At time t34, since the divided signal DS is a high level signal, the clock pulse of the divided clock CP (k + 1) output from the divided counter 12 is output as the clock pulse of the output divided clock DCP. Has been done. At this time, the counter value of the frequency division counter 21 is “2”, and the counter value of the frequency division counter 22 is “3”.
Is.

Further, from time t34, the master clock M
One clock after C, the counter value of the frequency division counter 21 is initialized to "1" in response to the fall of the frequency division signal DS, and the counter value of the frequency division counter 22 becomes "4".

At time t35, since the frequency-divided signal DS is a low level signal, the clock pulse of the frequency-divided clock CP (k) output from the frequency-division counter 11 is output as the clock pulse of the output frequency-divided clock DCP. Has been done. At this time, the counter value of the frequency division counter 21 is "1", and the counter value of the frequency division counter 22 is "4".
Is.

Further, from time t35, the master clock M
One clock after C, the counter value of the frequency division counter 21 becomes "2" in response to the rising edge of the frequency division signal DS,
The counter value of the frequency division counter 22 becomes “5”.

At time t36, since the frequency division signal DS is a high level signal, the clock pulse of the frequency division clock CP (k + 1) output from the frequency division counter 11 is output as the clock pulse of the output frequency division clock DCP. Has been done. At this time, the counter value of the frequency division counter 21 is “2”, and the counter value of the frequency division counter 22 is “5”.
Is.

Further, from time t36, the master clock M
One clock after C, the divided reset signal DR changes from a low level to a high level signal, and the divided signal DS changes from a high level to a low level signal. At this point, the frequency division counter 21 initializes the counter value to "1" in response to the fall of the frequency division reset signal DR. Similarly, the frequency division counter 22 initializes the counter value to "1" in response to the fall of the output frequency division clock DCP. This is the same operation as each signal one clock after the master clock MC from the time 31.

Therefore, the master clock MC input in one cycle from time t31 to time t36
The number of clock pulses of is 12 and the number of clock pulses of the output divided clock DCP to be output is 5. In this way, with respect to the master clock MC, the frequency division ratio (12 /
It can be divided in 5).

FIG. 4 is a diagram showing another embodiment of the present invention. Another non-integer frequency division circuit of the present invention is a frequency division counter 1
4, a frequency division counter 21 and a frequency division counter 22. The same elements as those in FIG. 2 are designated by the same reference numerals and the description thereof will be omitted. Here, the frequency dividing counter 14 corresponds to the clock frequency dividing means 10 in FIG.

The frequency division counter 14 outputs the output frequency-divided clock D.
CP is input as a reset signal, the master clock MC is divided by either k or (k + 1) based on the divided signal DS, and output as an output divided clock DCP. For example, when a low level is input as the divided signal DS, the divided clock divided by k is output as the output divided clock DCP, and when a high level is input as the divided signal DS ( k + 1) The frequency-divided divided clock is output as the output divided clock DCP.

Specifically, the frequency division counter 14 is (k +
1) Consists of only a frequency division counter. Then, when the output divided clock DCP is input as the reset signal, if a low level is input as the divided signal DS, "1" is initialized as a counter value, and a high level is set as the divided signal DS. If it has been input, "0" is initialized as the counter value. Depending on the initially set counter value, the master clock MC is divided by either k or (k + 1).

Next, the operation of another non-integer frequency dividing circuit of the present invention will be described. First, the master clock MC is input to the frequency dividing counter 14. The frequency dividing counter 14 frequency-divides the master clock MC by k or (k + 1) based on the frequency-divided signal DS, and outputs it as an output frequency-divided clock DCP. The frequency division counter 14 outputs the output frequency-divided clock DC.
It is reset when P is input, and frequency division is newly performed.

Then, the output divided clock DC is output.
P is input to the frequency dividing counter 21 and the frequency dividing counter 22. The frequency division counter 21 outputs the output frequency division clock DCP
The frequency is divided and output as a divided signal DS. The frequency division counter 21 is reset when the frequency division reset signal DR is input, and newly performs frequency division. Similarly, the frequency division counter 22 frequency-divides the output frequency-divided clock DCP by b and outputs the frequency-divided reset signal DR.

Therefore, the frequency-divided signal DS output from the frequency-division counter 21 is output as a high-level signal p times during one cycle in which the output frequency-divided clock DCP is frequency-divided by b. That is, the high-level divided signal D is generated every (p / b) cycle.
It means that S is output.

When the frequency-divided signal DS thus output is a low-level signal, the counter value is initially set to "1" so that the frequency-divided signal is divided by k before being output. Since the value is initialized to "0" (k +
1) Since the frequency is divided and output, the frequency division can be performed with a non-integer frequency division ratio.

The output frequency-divided clocks DCP obtained by the non-integer frequency-dividing circuit are not necessarily equidistant. That is, the clock pulse divided by k is output in one section of one cycle, and the clock pulse divided by (k + 1) is output in the other sections. This output frequency-divided clock DCP uses a PLL (Phase-Lock) as required.
ed Loop) circuit or the like, it is possible to easily convert to an output divided clock at equal intervals.

SDH is used as the master clock MC.
In order to convert the fundamental frequency such as NNI and NNI to the fundamental frequency of digital hierarchy in Japan or North America, the division ratio is (6480/193), so (k + c /
When transformed into the form of b), it becomes 6480/193 = 33 + 111/193. Therefore, each coefficient is [k = 3 by the above equation (1).
3, b = 193, c = 111]. Further, since c> (b / 2) from these coefficients, 193 / (193-111) = 2 + 29/82 is obtained, so that according to the equation (5), [p = 2, q = 29].

Therefore, in the non-integer frequency dividing circuit of the present invention, each variable value is [k = 33, b = 193, c = 11.
1], the frequency is delayed by 29 clocks after the frequency-division reset signal DR is input and frequency-divided by the frequency-division counter 21 to divide the phase into two, without converting the fundamental frequency such as SDH and NNI into a high frequency in advance. Non-integer frequency division can be performed directly.

In the above description, the non-integer frequency dividing circuit of the present invention is applied to the transmission device, but the present invention is not limited to this, and may be applied to a device for performing non-integer frequency division. If the frequency division ratio (k + c / b) of a non-integer value can be represented by (k + 1 / b), that is, (c = 1), the frequency division counter 21 may be omitted. In this case, the frequency division counter 22
Is output as the divided signal DS. Therefore, by eliminating the frequency dividing counter 21, the number of circuit components can be reduced and the cost can be suppressed.

[0050]

As described above, according to the present invention, the master clock is the first integer (k) which is the integer part of the non-integer value.
The divided clock divided by, and the second obtained by adding 1 to the first integer
Since it is configured to select and output the divided clock divided by the integer (k + 1) of, even if the master clock is divided by a non-integer division ratio, the master clock has a high frequency in advance. It is possible to realize with a simple circuit configuration without the need for frequency conversion into.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram showing an example of the present invention.

FIG. 3 is a time chart showing an example of the operation of the embodiment of FIG.

FIG. 4 is a diagram showing another embodiment of the present invention.

[Explanation of symbols]

 10 clock dividing means 20 divided signal generating means MC master clock DS divided signal DCP output divided clock

Claims (4)

[Claims] 1. A non-integer frequency division circuit for dividing a master clock by a non-integer frequency division ratio, wherein the master clock (MC) is divided by a first integer which is an integer part of the non-integer value. A first divided clock and a second divided clock divided by a second integer obtained by adding 1 to the first integer are generated, and the first divided clock is generated based on the divided signal (DS). A clock frequency dividing means (10) for selecting one of the frequency-divided clock and the second frequency-divided clock and outputting it as an output frequency-divided clock (DCP), and the output frequency-divided clock (DCP). A non-integer frequency dividing circuit, comprising: a frequency-divided signal generating means (20) for frequency-dividing by a frequency-dividing ratio of a fractional part of a non-integer value and outputting the frequency-divided signal (DS). 2. The clock frequency dividing means (10), when the frequency dividing ratio is (a / b), a / b = k + m = k + (c / b) (where a, b, c Is an integer, k is an integer part of the division ratio, and m is a fractional part of the division ratio), the master clock (MC) is divided by k to generate a first divided clock (CP). A first frequency division counter (11) which outputs as (k)) and a second frequency division counter (12) which frequency-divides (k + 1) and outputs as a second frequency-divided clock (CP (k + 1)). , The first divided clock (CP (k)) or the second divided clock (CP (k + 1)) is selected based on the divided signal (DS) to output the output component. A non-uniform circuit according to claim 1, further comprising a selector (13) for outputting as a peripheral clock (DCP). The frequency divider circuit. 3. The clock frequency dividing means (10), when the frequency dividing ratio is (a / b), a / b = k + m = k + (c / b) (where a, b, c Are integers, k is an integer part of the division ratio, and m is a fractional part of the division ratio), and the master clock (MC) is divided by k based on the division signal (DS) or 2. The fifth frequency division counter (14) according to claim 1, further comprising a fifth frequency division counter (14) for selecting and dividing one of the (k + 1) frequency divisions and outputting it as the output frequency division clock (DCP). Non-integer divider circuit. 4. The frequency division signal generation means (20), when the frequency division ratio is (a / b), a / b = k + m = k + (c / b) = (k + 1) (c / b) + k (bc) / b (where a, b, and c are all integers, k is an integer part of the division ratio, and m is a decimal part of the division ratio), and b / c = p + (q / c) {c <
When (b / 2)} b / (bc) = p + {q / (bc)} {c>
(B / 2)} [where p and q are integers, p is an integer part of (b / c), and (q / c) is a decimal part of (b / c)] After inputting the fourth frequency division counter (22) for frequency-dividing the output frequency-divided clock (DCP) by b and outputting the frequency-divided reset signal (DR), only q clocks after inputting the frequency-divided reset signal (DR). A third frequency division counter (21) which delays the phase and frequency-divides the output frequency-divided clock (DCP) and outputs the frequency-divided signal (DS) having a period (c / b). The non-integer frequency divider circuit according to claim 1, which is characterized in that.