JPH05335840A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To provide a semiconductor integrated circuit operated efficiently by preventing increase in power consumption while being compatible with a wide range of a power supply voltage. CONSTITUTION:The circuit is provided with a power supply voltage discrimination circuit 1 discriminating a power supply level to select and operate any bias circuits B whose output level differs. A prescribed bias voltage is outputted from the bias circuit B selected by the power supply voltage discrimination circuit 1 based on a power supply Vcc and an internal circuit 5 is operated based on the bias voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit capable of operating in a wide range of power supply voltages.

In recent years, a cordless telephone for consumer use uses 2V as a power supply voltage for a child device and 5V for a parent device. Therefore, it is required that the semiconductor integrated circuit used in such a cordless telephone be configured to operate efficiently at either the power supply voltage of 2V or 5V.

[0003]

2. Description of the Related Art In a conventional cordless telephone for consumer use, a 2V specification PLL synthesizer circuit used in a handset has an operation margin so that it can be operated even when the power supply voltage is 5V, so that the handset and the handset can operate. A common PLL synthesizer circuit is used to reduce manufacturing costs.

[0004]

In the PLL synthesizer circuit that can operate in a wide range of power supply voltage as described above, when the 2V specification PLL synthesizer circuit is used at the power supply voltage of 5V in the master unit, the power supply voltage rises. Accordingly, there is a problem that power consumption increases.

An object of the present invention is to provide a semiconductor integrated circuit capable of operating efficiently while preventing power consumption from increasing while supporting a wide range of power supply voltages.

[0006]

FIG. 1 illustrates the principle of the present invention. That is, the power supply voltage determination circuit 1 that determines the power supply level and selects one of the bias circuits B having different output levels to operate it.
Is provided, a constant bias voltage is output from the bias circuit B selected by the power supply voltage determination circuit 1 based on the power supply Vcc, and the internal circuit 5 is operated based on the bias voltage.

Further, as shown in FIG. 2, in the power supply voltage determination circuit 1, a voltage obtained by stepping down the power supply Vcc at a constant rate is input to the base of one transistor Tr1 forming a differential circuit, and the differential circuit is connected. A reference voltage irrelevant to the change of the power supply Vcc is input to the base of the other transistor Tr3 constituting the power supply Vcc, and the voltage level of the power supply Vcc is determined.

[0008]

The bias circuit B corresponding to the change in the power supply Vcc is selected by the power supply voltage determination circuit 1, and the internal circuit 5 is driven by the constant bias voltage output from the selected bias circuit B.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment embodying the present invention will now be described with reference to FIG.
And FIG. 3 will be described. In the power supply voltage determination circuit 1 shown in FIG. 2, a resistor R1 and a resistor R2 are connected in series between a high potential side power source Vcc and a low potential side power source GND, and the resistance values of the resistors R1 and R2 are the same. It is set to a value. Therefore, the potential of the node A between the resistors R1 and R2 is Vcc.
It is set to / 2.

The node A is connected to the base of the NPN transistor Tr1, the collector of the transistor Tr1 is connected to the power source Vcc through the resistor R3, and the emitter is connected to the collector of the transistor Tr2 which operates as a current source.

The collector of the transistor Tr3 which forms a differential circuit together with the transistor Tr1 is connected to the power source Vcc through the resistor R4, and the emitter is the transistor T3.
It is connected to the collector of r2. When the activation signal Vcs is input to the base of the transistor Tr2, the transistors Tr1 and Tr3 forming the differential circuit are activated.

The base of the transistor Tr3 is a resistor R5.
Is connected to the power supply Vcc via a diode D
It is connected to the ground GND through 1 to D3. Therefore, the base potential of the transistor Tr3 is the diode D1.
It is set to about 2.4V by D3.

The collector of the transistor Tr1 is PNP.
It is connected to the base of the transistor Tr4, the emitter of the transistor Tr4 is connected to the power supply Vcc via the resistor R6, and the collector is connected to the ground GND via the resistor R7.

The collector of the transistor Tr3 is PNP.
It is connected to the base of the transistor Tr5, the emitter of the transistor Tr5 is connected to the power supply Vcc via the resistor R8, and the collector is connected to the ground GND via the resistor R9.

The collector of the transistor Tr4 is PNP.
It is connected to the base of the transistor Tr6, the emitter of the transistor Tr6 is connected to the 5V bias circuit 2, and the collector is connected to the ground GND.

The collector of the transistor Tr5 is PNP.
It is connected to the base of the transistor Tr7, the emitter of the transistor Tr7 is connected to the 2V bias circuit 3, and the collector is connected to the ground GND.

The 5V bias circuits 2 and 2V
The output voltage of the bias circuit 3 is the PLL synthesizer circuit 4
Output as a bias voltage. The circuit configurations of the 5V bias circuit 2 and the 2V bias circuit 3 are the same,
As an example, the configuration of the 5V bias circuit 2 will be described with reference to FIG.
Is connected to the power source Vcc via.

The bases of the transistors Tr8 and Tr9 are N
It is connected to the collector of the PN transistor Tr10, the base of the transistor Tr10 is connected to the ground GND via the resistor R11, and the emitter is connected to the ground GND.

The collector of the transistor Tr8 is a power source V
It is connected to cc, and the emitter is connected to the collector of the NPN transistor Tr11 via the resistor R12. Also,
The collector of the transistor Tr11 is connected to the base of the transistor Tr10, and the emitter is connected to the ground GND via the resistor R13.

The collector of the transistor Tr9 is a power source V
cc, the emitter is connected to the output terminal Tout, and the NPN transistor Tr1 is connected via the resistor R13.
Connected to 2 collectors.

The collector of the transistor Tr12 is connected to its base, and its base is connected to the base of the transistor Tr11 via a resistor R14. The emitter of the transistor Tr12 is ground GN.
Connected to D.

5V bias circuit 2 constructed in this way
Then, the transistor Tr6 is turned on and its input signal V
When in falls to the level of the ground GND, the transistors Tr8 and Tr9 are turned off, and the transistors Tr10 to Tr12 are also turned off.

Therefore, the output signal Vout output from the output terminal Tout is in a floating state, and the bias voltage cannot be supplied to the PLL synthesizer circuit 4. On the other hand, when the transistor Tr6 is turned off, the bases of the transistors Tr8 and Tr9 are connected to the resistor R1 from the power source Vcc.
The base current is supplied via 0 to the same transistor Tr.
8, Tr9 is turned on, and based on this, the transistor Tr10
~ Tr12 is also turned on.

Therefore, the output signal Vout is outputted as a constant voltage based on the constants of the transistors Tr8 to Tr12 and the resistors R10 to R14, and the output signal Vout is supplied to the PLL synthesizer circuit 4 as a bias voltage.

The above 5 which operates with a power supply Vcc of 5V
The above-mentioned constants are set so that the V bias circuit 2 and the 2V bias circuit 3 operating with the 2V power supply Vcc output the output signal Vout having the same potential.

Next, the operation of the power supply voltage determination circuit 1 configured as described above will be described. Now, 5V as the power supply Vcc
Is supplied, the node A becomes 2.5V, and the base potential of the transistor Tr1 becomes higher than the base potential of the transistor Tr3 which is set to 2.4V.

Then, the transistor Tr1 is turned on and the transistor Tr3 is turned off. Accordingly, the transistor Tr4 is turned on and the transistor T3 is turned on.
r5 is turned off.

When the transistor Tr4 is turned on, the transistor Tr6 is turned off, and when the transistor Tr5 is turned off, the transistor Tr7 is turned on. Therefore, the 2V bias circuit 3 becomes inoperative, the 5V bias circuit 2 becomes active when the power supply Vcc is 5V, and the output signal Vout of the 5V bias circuit 2 is output to the PLL synthesizer circuit 4 as a bias voltage. ..

On the other hand, when 2V is supplied as the power supply Vcc, the node A becomes 1V and the base potential of the transistor Tr1 becomes lower than the base potential of the transistor Tr3 which is set to 2.4V.

Then, the transistor Tr1 is turned off and the transistor Tr3 is turned on, and accordingly, the transistor Tr4 is turned off and the transistor T3 is turned on.
r5 is turned on.

When the transistor Tr4 is turned off, the transistor Tr6 is turned on, and when the transistor Tr5 is turned on, the transistor Tr7 is turned off. Therefore, the 5V bias circuit 2 becomes inoperative, the 2V bias circuit 3 becomes active when the power supply Vcc is 2V, and the output signal Vout of the 2V bias circuit 3 is output to the PLL synthesizer circuit 4 as a bias voltage. ..

As described above, in this embodiment, when 5V is supplied as the power supply Vcc, the power supply voltage supply circuit 1 supplies 5V.
The bias circuit 2 is activated and its 5V bias circuit 2
Outputs a constant bias voltage to the PLL synthesizer circuit 4.

On the other hand, when 2V is supplied as the power supply Vcc, the 2V bias circuit 3 is activated by the power supply voltage supply circuit 1, and the 2V bias circuit 3 outputs a constant bias voltage to the PLL synthesizer circuit 4.

Therefore, a constant bias voltage is always supplied to the PLL synthesizer circuit 4 regardless of whether the power supply Vcc is supplied with a voltage of 5V or 2V. It does not increase.

In the above embodiment, the bias circuit is selected on the basis of the voltage level of the power supply Vcc, but the bias circuit may be selected on the basis of the current level supplied from the power supply Vcc.

[0036]

As described above in detail, the present invention has an excellent effect of providing a semiconductor integrated circuit which can cope with a wide range of power supply voltages, prevent increase in power consumption, and operate efficiently. ..

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing an embodiment of the present invention.

FIG. 3 is a circuit diagram showing a bias circuit according to an embodiment.

[Explanation of symbols]

 1 Power supply voltage judgment circuit 5 Internal circuit Vcc power supply B Bias circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shinji Saito 1844-2, Kozoji-cho, Kasugai-shi, Aichi Fujitsu Viel SII Co., Ltd.

Claims (2)

[Claims] 1. A power supply voltage determination circuit (1) for determining a power supply level and selecting one of a plurality of bias circuits (B) having different output levels to operate, The bias circuit (B) selected by the power supply voltage determination circuit (1) outputs a constant bias voltage based on the power supply (Vcc) and operates the internal circuit (5) based on the bias voltage. Semiconductor integrated circuit. 2. The power supply voltage determination circuit (1) inputs a voltage obtained by stepping down a power supply (Vcc) at a constant rate to the base of one transistor (Tr1) forming a differential circuit, 2. The semiconductor integrated device according to claim 1, wherein a reference voltage irrelevant to a change in the power source (Vcc) is input to the base of the other transistor (Tr3) to be configured to determine the voltage level of the power source (Vcc). circuit.