JPH05335417A - Automatic designing method of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the dead space of an internal circuit and a peripheral circuit to a minimum, and arrange chip terminals at optimum positions, without deteriorating LSI chip function, by using an automatic layout program. CONSTITUTION:As to a block to be registered in a library for automatic layout, a peripheral circuit 1 or the like is registered as the circuit block, so as to be different from the terminal block constituted of lines, terminals 4, etc. Thereby useless space is eliminated from the arrangement on a chip.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a large scale integrated circuit (hereinafter,
The present invention relates to a pattern layout of an integrated circuit such as an LSI) and is particularly used for a CAD (Computer Aided Design) system.

[0002]

2. Description of the Related Art Conventionally, a semiconductor substrate on which an LSI is mounted (hereinafter referred to as a chip) has a chip layout configuration as shown in FIG. The LSI constitutes an integrated circuit including an internal circuit having functions such as a memory and a logic, a terminal connected to an external circuit, an input / output circuit serving as a buffer at the time of input / output, and the like.

In recent years, high integration and miniaturization of LSI have progressed, and it is an important step in manufacturing a semiconductor integrated circuit device to examine a chip layout which is useful for this tendency. A silicon semiconductor is used for the semiconductor substrate, and the internal circuit 1 is formed in the central portion of the silicon semiconductor substrate 10. The terminal row 4 is formed in the peripheral portion along each side. The terminals formed in the terminal row 4 include the input terminals 4
1, an output terminal 42, a VDD power supply terminal 43, and a GND power supply terminal 44. The input circuit 2 and the output circuit 3 are arranged between the terminal row 4 and the internal circuit 1, and the input terminal 41 and the output terminal 42 are arranged in the center through the input circuits 4 and the output circuit 3. Connected to the internal circuit 1. In addition, each power supply line 5 passes through the input circuit and the output circuit, and each power supply line 5 is connected to the VD of the terminal row 4.
The D power supply terminal 43 and the GND power supply terminal 44 are connected.

[0004]

As described above, in recent LSIs, fine processing technology has advanced, and the degree of integration on one chip exceeds 1 million elements. However, around each terminal of the LSI chip, the thickness of the bonding wire used for connecting to the lead frame or the method of connecting the bonding wire, for example, for electrostatic breakdown such as addition of protection circuit or latch-up Due to the measures against external noise, the microfabrication technology is not particularly advanced compared to the miniaturization of internal circuits. On the other hand, in the LSI industry, diversification of product specifications, LS
It is desired to reduce the I-chip size and the LSI development period, and in particular, ASICs represented by gate arrays and standard cells respond to the needs of such times with CAD-assisted automatic design.

When designing the layout of an LSI, elements such as transistors and capacitors may be laid out one by one on a chip in order to reduce the time and labor required for the design and facilitate various verifications. In general, a layout design is performed in advance for each functional block having a certain degree of function, and the layout of the functional blocks and wiring design are performed to complete the layout of the entire chip. With the rapid development of the LSI technology as described above, the complexity of the logic design and the layout design is increasing. Hierarchical design methods have been adopted as one means for this, and the design efficiency has been improved. In this method, first, logical design is performed top-down for each hierarchy, and then layout design is performed bottom-up for each hierarchy based on the result. In this case, in the layout design, a plurality of blocks accommodating the functional circuits are arranged in each layer, and wiring is provided between the blocks to realize a desired circuit.

Generally, in the design of an LSI chip by an automatic layout program, the turnaround of the design is shorter than the manual design, but the degree of freedom in design is small and the LSI chip size tends to be large. In particular, since the miniaturization of the LSI chip periphery is not advanced compared to the internal circuit,
The degree of freedom in design is low, and in particular, the chip size is determined by the size of the area occupied by the peripheral circuits of the above-mentioned terminals such as the input circuit 2 and the output circuit 3 with respect to the chip size, which makes it impossible to reduce the size. Cause The problem of the conventional technique will be described with reference to FIGS. FIG. 10A is an outer frame block diagram in which the size and position of elements of an input circuit device including an input circuit and an input terminal of a conventional LSI chip are taken into consideration, and includes a symbol indicating the input circuit. There is. The input circuit 2 in the figure is
It is arranged inside the chip with respect to the input terminal 41. Xin
Indicates the width of the block.

FIG. 10B is an outer frame block diagram in consideration of the size and position of the elements of the output circuit device including the output circuit 3 and the output terminal 42 of the conventional LSI chip. Contains the indicated symbol. The output circuit 3 in the figure is arranged inside the chip from the output terminal 42. Xout indicates the width of the block. Figure 10
FIG. 7C is a block diagram in consideration of the size and position of the power supply line 5 and the VDD power supply terminal 43 of the conventional LSI chip. The power supply line 5 in the figure includes one connected to the VDD power supply terminal 43 and one connected to the GND power supply terminal 44, and both are arranged inside the VDD power supply terminal 43 in the chip. Xpwr indicates the width of the block. Figure 10
FIG. 7D is a block diagram in consideration of the size and position of the power supply line 5 and the GND power supply terminal 44 of the conventional LSI chip. The power supply line 5 in the drawing is arranged inside the chip with respect to the GND power supply terminal 44.

The block shown in FIG. 10 is prepared as an automatic layout library, and an LSI chip is designed by using it for layout as required. FIG. 11 is a plan view of an LSI chip in which internal circuits, input / output circuits, terminals, etc. are formed on the chip by an automatic layout program and a lead frame attached to the chip. Although the internal circuit and the input / output circuit are formed on the chip 11,
It is omitted in the figure. The terminals (bonding pads) 14 on the four sides of the chip 11 and the lead frame 12 are electrically connected by the bonding wires 13. The chip 11 is supported by the hanging pins 15 of the lead frame 12 and mounted and fixed on the required chip mounting portion 16. FIG. 12 is an enlarged plan view in which a corner portion A of the LSI chip shown in FIG. 11 is enlarged. In the figure, the bonding wire 13 is a terminal 14 on the chip 11.
To the lead end of the lead frame 12 and the length thereof is L. Also, the bonding wire 13
Is W. The angle formed between the lead wire 12 and the bonding wire 13 of the enlarged corner portion is φ.

The terminals 14 are required to be as small as possible in accordance with the miniaturization and high integration of the LSI, and it is necessary to narrow the arrangement interval. However, depending on the thickness W of the bonding wires 13 or the bonding wires are connected. Due to technical constraints in operating the connection device, there is a minimum limit to its size and spacing. Therefore, the widths Xin, Xout, and Xpwr of each block are determined by this limit dimension. Further, in order to ensure the electrical connection between the terminal 14 and the lead frame 12, the distance L between the connection ends of the bonding wire 13, the lead frame 12 and the bonding wire 1
The angle φ formed by 3 is limited, and the arrangement position of each terminal 14 is restricted to a specific place. The restriction on the arrangement position of each terminal is determined by the chip size and the positional relationship between the chip and the lead frame.

FIG. 9 shows an LSI chip in which 12 blocks are arranged on each side using the blocks of FIG. In the figure, Xb indicates the width of the internal circuit, and Yb indicates the height of the internal circuit. Now, set the widths Xin, Xout, and Xpwr of each peripheral block to 0.
Assuming 3 mm, the total block width per side is 0.3
mm × 12 = 3.6 mm. On the other hand, if the internal block size is Xb × Yb = 3 mm × 3 mm, in this case, a dead space is generated between the internal circuit and the peripheral circuit including the input circuit or the output circuit. If this dead space can be eliminated, the chip size can be further reduced. Further, when the terminals must be arranged also in the corners of the chip due to the restriction of the terminal positions described above, it is necessary to bend the power supply lines in the corners, and therefore the block of FIG. 10 cannot be arranged. ..

The present invention has been made under the circumstances as described above.
The purpose is to minimize the dead space between the internal circuit and the peripheral circuit including the input circuit or the output circuit without impairing the function of the I chip, and to arrange the terminals on the chip at the optimum positions. There is.

[0012]

The present invention is characterized in that circuits or lines and terminals are prepared in separate blocks as a library for automatic layout and automatically designed. That is, an automatic design method for a semiconductor integrated circuit device according to the present invention includes means for forming each circuit block of an input circuit, an output circuit, a peripheral circuit of an input / output circuit and an internal circuit, and a block of a power supply line, an input terminal and an output terminal. Using the means for forming each terminal block of the input / output terminal and the power supply terminal and a predetermined block among the circuit blocks and the block of the power supply line, the peripheral circuit, the internal circuit and the power supply are provided on the semiconductor substrate. A means for arranging and arranging lines, a means for arranging necessary terminals at an optimum position around the internal circuit of the semiconductor substrate by using a predetermined block in the terminal block, and a means for arranging on the semiconductor substrate And a means for connecting the formed terminal to the peripheral circuit formed on the semiconductor substrate, the internal circuit, and the power supply line.

Pads formed in the peripheral portion of the semiconductor substrate are used for the terminals of the terminal block. The pad may be formed on a corner of the semiconductor substrate. A plurality of circuits among the peripheral circuits can be connected to one pad. Any of the pads may be connected to one of the peripheral circuits. The input circuit or the output circuit is also formed in the corner of the semiconductor substrate, and the input circuit or the output circuit is connected to the adjacent input circuit or the output circuit to thereby connect the adjacent input circuit or the output circuit. It can be connected to the internal circuit via. It is also possible to connect a plurality of predetermined circuits of the peripheral circuit to the pad and connect a plurality of circuits not connected to the pad to each other and use them as a part of the internal circuit. The width of the wiring connecting the pad and a predetermined circuit of the peripheral circuit can be made larger than the widths of other wirings.

[0014]

The width of the input / output block around the LSI is limited not by the area occupied by the input / output circuit but by the size of the terminals and the positional interval. Therefore, if each of the input circuit and the input terminal, the output circuit and the output terminal, the power supply line and the power supply terminal, etc. is a separate block, the block width of each of the input circuit, the output circuit and the power supply line is It is possible to design with the minimum width without being restricted by the size and the position interval.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view of a chip on which a semiconductor integrated circuit device according to an embodiment of the present invention is formed. The chip has an input circuit 2 and an input terminal 41, an output circuit 3 and an output terminal 42, V
The DD power supply terminal 43, the GND power supply terminal 44, and the internal circuit 1 including functional circuits such as logic are formed. The terminal row 4 in which these terminals are arranged is formed on four sides of the chip 1. Each power supply line 5 passes through the input circuit 2 and the output circuit 3. Figure 7 (a)
FIG. 3 is a circuit block diagram in consideration of the size, position, etc. of the elements of the input circuit device of the LSI chip used in the embodiment of the present invention, and includes a symbol indicating that it is an input circuit. Xin 'in the figure indicates the width of the block. Figure 7
(B) is a circuit block diagram in consideration of the size, position, etc. of the elements of the output circuit device of the LSI chip used in the embodiment of the present invention, and includes a symbol indicating that it is an output circuit. Xout 'in the figure indicates the width of the block.
7 (c) and 7 (d) show the power supply line 5 and power supply terminals 43, 4 of the LSI chip, which are used in the embodiment of the present invention.
4 is a block diagram of a portion for connecting 4 in FIG. Also, X in the figure
pwr 'indicates the width of the block.

On the other hand, when an LSI chip is designed by an automatic layout program, the connection relationship of individual blocks used in the LSI chip design is described by a connection description language that can be processed by the automatic layout program at the circuit design stage. .. At the stage of circuit design, it is not necessary to separately describe the input / output circuit and the terminal, and the input / output circuit and the terminal may be automatically divided when the pattern level is designed by the automatic layout program. That is, in the automatic layout library, input / output circuit blocks are prepared in a two-level structure of a circuit level and a pattern level, the circuit level blocks are used for the circuit design, and the pattern level blocks are used for the pattern design. To use. This conceptual diagram is shown in FIG. FIG. 13 is a conceptual diagram in the case of the output circuit block. The circuit level is composed of only the output circuit 3, and the pattern level is composed of the output circuit 3, the output terminal 42 and the signal line 6. Output circuit 3
The output terminal 42 and the output terminal 42 are connected by the signal line 6.

In FIG. 1, the terminals are arranged according to the optimum arrangement information determined by the relationship between the lead frame and the chip, and the input circuit 2 and the input terminal 41, the output circuit 3 and the output terminal 42, the power supply line 5 and the power supply terminal 5 are arranged. 43 and 44 are connected by the automatically generated signal line 6 when the connection description is expanded from the circuit level to the pattern level by the automatic layout program. The width of each block such as the input / output circuit described in the embodiments of the prior art is not determined by the area occupied by the input / output circuit, but depends on the size and positional relationship of the terminals.

On the other hand, in the present invention, as shown in FIG. 10, each of the input circuit 2 and the input terminal 41, the output circuit 3 and the output terminal 42, the power supply line 5 and the power supply terminal 43 or 44 is automatically formed as a separate block. Since it is prepared in the layout library, the block width of each of the input circuit, the output circuit, and the power supply line is not limited by the size and the arrangement interval of the terminals, and the block width should be remarkably smaller than the conventional one. Xin '<Xin, Xout'<Xout,
Xpwr '<Xpwr can be realized. Using the block of FIG. 7, an LSI chip having 12 terminals on each side is shown in FIG.
Is shown in. As shown in the figure, the width Xin ', Xout', Xpwr 'of each block is, for example, 0.25 mm.
If the following can be achieved, the total block width per side will be 0.25 mm × 12 = 3 mm or less. On the other hand, when the above-mentioned conventional one is used as the internal circuit 1, the width Xb and the height Yb of the internal circuit are both 3 mm. The size of this internal circuit is almost equal to the total block width per side of the terminal block formed on the four sides of the chip, and therefore the problem of dead space described in the prior art is solved. To be done. Further, it is possible to arrange the terminals at the corners of the chip.

Next, another embodiment will be described with reference to FIG. The drawing is a plan view of a chip in which a semiconductor integrated circuit device according to an embodiment of the present invention is formed. The chip 10 includes an input circuit 2 and an input terminal 41, an output circuit 3 and an output terminal 42V.
The DD power supply terminal 43, the GND power supply terminal 44, and the internal circuit 1 including functional circuits such as logic are formed. The terminal row 4 in which these terminals are arranged is formed on four sides of the chip 1. Each power supply line 5 passes through the input circuit 2 and the output circuit 3. In the previous embodiment, the effect that the dead space is eliminated by making the widths of the terminal row and the internal circuit approximately the same can be expected.
The four corners of chip 10 have not been improved. In this embodiment, terminals, for example, the input terminals 41 are arranged also in the chip corner, which cannot be arranged by the conventional technique. This is made possible by the present invention by dividing the block into a terminal block and a circuit block. Of course, you may arrange terminals other than the input terminal,
It is also possible to place them in the other three corners at the same time.

Next, another embodiment will be described with reference to FIG. The drawing is a plan view of a chip in which a semiconductor integrated circuit device according to an embodiment of the present invention is formed. The chip 10 includes an input circuit 2 and an input terminal 41, an output circuit 3 and an output terminal 42V.
The DD power supply terminal 43, the GND power supply terminal 44, and the internal circuit 1 including functional circuits such as logic are formed. The terminal row 4 in which these terminals are arranged is formed on four sides of the chip 1. Each power supply line 5 passes through the input circuit 2 and the output circuit 3. In this embodiment, two input terminals 41 (B) and one input circuit 2 are connected, and two input circuits 2 are connected in parallel to one input terminal 41 (C). The number of input terminals or input circuits is not limited to two and may be three or more. Further, the present invention is not limited to input circuits and can be applied to output circuits. With such a connecting method, an input circuit or an output circuit with high driving force can be formed.

Next, another embodiment will be described with reference to FIG. The drawing is a plan view of a chip in which a semiconductor integrated circuit device according to an embodiment of the present invention is formed. The chip 10 includes an input circuit 2 and an input terminal 41, an output circuit 3 and an output terminal 42V.
The DD power supply terminal 43, the GND power supply terminal 44, and the internal circuit 1 including functional circuits such as logic are formed. The terminal row 4 in which these terminals are arranged is formed on four sides of the chip 1. In this embodiment, one of the input circuits or the output circuits arranged between the terminal array 4 and the internal circuit 1 is used.
The parts are not connected to the terminals, but are connected in series and connected to the internal circuit, for example, like a pair (D) of the input circuit and the output circuit shown in the figure. In this way, the pair of the input circuit and the output circuit D can be handled as a part of the internal circuit, and the contents of the integrated circuit can be enriched and the chip can be effectively utilized.

Next, another embodiment will be described with reference to FIG. The drawing is a plan view of a chip in which a semiconductor integrated circuit device according to an embodiment of the present invention is formed. The chip 10 includes an input circuit 2 and an input terminal 41, an output circuit 3 and an output terminal 42V.
The DD power supply terminal 43, the GND power supply terminal 44, and the internal circuit 1 including functional circuits such as logic are formed. The terminal row 4 in which these terminals are arranged is formed on four sides of the chip 1. As mentioned above, the corner of the chip
Is an area where it is difficult to connect the input circuit and the output circuit to the internal circuit. Therefore, in this embodiment, the input circuit (E) is formed in the chip corner in a relatively free shape. Since it is difficult to directly connect the input circuit E and the internal circuit 1, the input circuit E is connected in series with an adjacent input circuit, and is connected to the internal circuit via the adjacent input circuit.
The two connected input circuits act as one input circuit. The input terminal connected to the input circuit E can also be formed as a corner. In this way, the signal can be extracted from the corner section.

Next, another embodiment will be described with reference to FIG. The drawing is a plan view of a chip in which a semiconductor integrated circuit device according to an embodiment of the present invention is formed. The chip 10 includes an input circuit 2 and an input terminal 41, an output circuit 3 and an output terminal 42V.
The DD power supply terminal 43, the GND power supply terminal 44, and the internal circuit 1 including functional circuits such as logic are formed. The terminal row 4 in which these terminals are arranged is formed on four sides of the chip 1. Regarding the width of the wiring connecting the input circuit / output circuit and the terminal, it is preferable that the wiring has a narrower degree of freedom in terms of layout, which is useful for high integration.
However, in the case of a power supply line, an output circuit that outputs a large current, and the like, it is not preferable to make it too thin, because the purpose cannot be achieved. In the present invention, the width of the wiring between the output circuit and the output terminal (G) and between the power supply line 5 and the GND power supply terminal (F) is made larger than that of the other wiring to correspond to the output. This can be done by dividing the blocks into circuit blocks and terminal blocks.

[0024]

The input circuit and the input terminal of the LSI chip, the output circuit and the output terminal, and the power supply line and the power supply terminal are respectively formed as separate blocks, so that the input circuit, the output circuit, and
The block width of each power supply line is not limited by the size and arrangement interval of the terminals, and the minimum width can be designed. If the input circuit, output circuit, and power supply line blocks designed with these minimum widths are prepared as a library for automatic layout, the dead space described in the problems of the conventional technology can be reduced by the automatic layout program. It can be eliminated or minimized. Further, it is possible to arrange the terminals at the corners of the chip.

[Brief description of drawings]

FIG. 1 is a plan view of an LSI chip according to an embodiment of the present invention.

FIG. 2 is a plan view of an LSI chip according to an embodiment of the present invention.

FIG. 3 is a plan view of an LSI chip according to an embodiment of the present invention.

FIG. 4 is a plan view of an LSI chip according to an embodiment of the present invention.

FIG. 5 is a plan view of an LSI chip according to an embodiment of the present invention.

FIG. 6 is a plan view of an LSI chip according to an embodiment of the present invention.

FIG. 7 is a plan view of each block of an LSI chip used in an embodiment of the present invention.

FIG. 8 is a plan view of an LSI chip according to an embodiment of the present invention.

FIG. 9 is a plan view of a conventional LSI chip.

FIG. 10 is a plan view of each block of a conventional LSI chip.

FIG. 11 is a plan view of the connection between the LSI chip and the lead frame.

12 is an enlarged plan view of a portion A in FIG.

[Explanation of symbols]

 1 Internal Circuit 2 Input Circuit 3 Output Circuit 4 Terminal Line 5 Power Line 6 Signal Line 10, 11 Chip 12 Lead Frame 13 Bonding Wire 14 Terminal 15 Lead Frame Fishing Pin 16 Lead Frame Chip Mounted part

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[Procedure amendment]

[Submission date] April 1, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0016

[Correction method] Change

[Correction content]

On the other hand, when the LSI chip is designed by the automatic layout program, the connection relation of each block used for the LSI chip design is described by the connection description language that can be processed by the automatic layout program at the circuit design stage. .. At the stage of circuit design, it is not necessary to separately describe the input / output circuit and the terminal, and the input / output circuit and the terminal may be automatically divided when the pattern level is designed by the automatic layout program. That is, in the automatic layout library, input / output circuit blocks are prepared in a two-level structure of a circuit level and a pattern level, the circuit level blocks are used for the circuit design, and the pattern level blocks are used for the pattern design. To use. This conceptual diagram is shown in FIG. FIG. 8 is a conceptual diagram in the case of the output circuit block. The circuit level is composed of only the output circuit 3, and the pattern level is the output circuit 3 and the output terminal 4.
2 and the signal line 6. The output circuit 3 and the output terminal 42 are connected by the signal line 6.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0017

[Correction method] Change

[Correction content]

In FIG. 1, the terminals are arranged according to the optimum arrangement information determined by the positional relationship between the lead frame and the chip, and the input circuit 2 and the input terminal 41, the output circuit 3 and the output terminal 42, the power supply line 5 and the power supply terminal 5 are arranged. 43 and 44 are connected by the automatically generated signal line 6 when the connection description is expanded from the circuit level to the pattern level by the automatic layout program. The width of each block such as the input / output circuit described in the embodiments of the prior art is not determined by the area occupied by the input / output circuit, but depends on the size and positional relationship of the terminals.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0018

[Correction method] Change

[Correction content]

On the other hand, in the present invention, as shown in FIG. 7, each of the input circuit 2 and the input terminal 41, the output circuit 3 and the output terminal 42, the power supply line 5 and the power supply terminal 43 or 44 is automatically formed as a separate block. Since it is prepared in the layout library, the block width of each of the input circuit, the output circuit and the power supply line is not limited by the size and the arrangement interval of the terminals, and the block width can be remarkably reduced as compared with the conventional one, that is, Xin '. <Xin, Xout '<Xout, Xpw
r ′ <Xpwr can be realized. Using the blocks in Figure 7,
The LSI chip having 12 terminals arranged on each side is shown in FIG. As shown, the width X of each block
If in ', Xout', and Xpwr 'can be set to 0.25 mm or less, the total block width per side is
0.25 mm × 12 = 3 mm or less. On the other hand, when the above-mentioned conventional one is used for the internal circuit 1, both the width Xb and the height Yb of the internal circuit are 3 mm. The size of the internal circuit is almost equal to the total block width per side of the terminal block formed on the four sides of the chip, and therefore the problem of dead space described in the prior art is solved. To be done. Further, it is possible to arrange the terminals at the corners of the chip.

[Procedure amendment 4]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 10

[Correction method] Change

[Correction content]

[Figure 10]

Claims (8)

[Claims] 1. A means for forming each circuit block of an input circuit, an output circuit, a peripheral circuit of an input / output circuit and an internal circuit and a block of a power supply line, and each terminal of an input terminal, an output terminal, an input / output terminal and a power supply terminal. Means for forming a block, means for arranging and wiring the peripheral circuit, the internal circuit, and the power supply line on a semiconductor substrate by using a predetermined block among the circuit blocks and the block of the power supply line, Means for arranging necessary terminals at an optimum position around the internal circuit of the semiconductor substrate by using a predetermined block in the terminal block, and forming the terminals arranged on the semiconductor substrate on the semiconductor substrate And a means for connecting to the peripheral circuit, the internal circuit, and the power supply line that have been created. 2. The method for automatically designing a semiconductor integrated circuit device according to claim 1, wherein the terminal of the terminal block is a pad formed in a peripheral portion of the semiconductor substrate. 3. The method for automatically designing a semiconductor integrated circuit device according to claim 2, wherein the pad is also formed on a corner of the semiconductor substrate. 4. The method for automatically designing a semiconductor integrated circuit device according to claim 2, wherein a plurality of circuits in the peripheral circuit are connected to one pad. 5. The method for automatically designing a semiconductor integrated circuit device according to claim 2, wherein the plurality of pads are connected to one circuit of the peripheral circuits. 6. A predetermined plurality of circuits of the peripheral circuit are not connected to the pad, and a plurality of circuits not connected to the pad are connected to each other and used as a part of the internal circuit. The method for automatically designing a semiconductor integrated circuit device according to claim 2. 7. The input circuit or the output circuit is also formed in a corner of the semiconductor substrate, and the input circuit or the output circuit is connected to the adjacent input circuit or the output circuit so as to connect the adjacent input circuit or the output circuit. 3. The method for automatically designing a semiconductor integrated circuit device according to claim 1 or 2, wherein the internal circuit is connected via a circuit or an output circuit. 8. The method for automatically designing a semiconductor integrated circuit device according to claim 2, wherein a width of a wiring connecting the pad and a predetermined circuit of the peripheral circuit is made larger than a width of another wiring. ..