JPH05334388A - Automatic generation system for hardware description - Google Patents

Abstract

PURPOSE:To automatically generate the hardware description by using conversion rule data which are dynamically applicable to the number of pins of a logic component when a hardware description language showing the logic function of a circuit is generated from a circuit diagram representing a logic circuit. CONSTITUTION:A logical connection extraction part 41 reads circuit diagram data 31 out of a data storage device 3 through an arithmetic processor 2. When there are the circuit diagram data 31, logic components are recognized, the number of pins is counted, and connections of the circuit are extracted from the read circuit diagram data 31. A description generation part 41 reads the conversion rule data 32 out of the data storage device 3. Then, the hardware description corresponding to the number of pins of the logic components and the hardware description language of the extracted circuit connections are generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hardware description automatic generation system for automatically generating a hardware description of a logic circuit using conversion rule data.

[0002]

2. Description of the Related Art In the conventional hardware description generation method,
It was necessary to manually generate the conversion rule data corresponding to the number of pins of the logic component.

[0003]

In this conventional hardware description generation method, conversion rule data corresponding to the number of pins of a logical component is generated, so conversion rule data corresponding to the number of logical components is required. There is a problem that the number of data becomes huge and a lot of man-hours are required to generate the conversion rule data.

[0004]

According to the automatic hardware description generation method of the present invention, the number of pins of a logic component is determined when a hardware description language representing a logical function of a circuit is generated from a circuit diagram representing the logic circuit. The feature is that the hardware description language is automatically generated using the conversion rule data that can be dynamically supported.

Then, the logic connection information is converted into a hardware description language by using a logic connection extraction unit for extracting the logic connection of the logic circuit and the conversion rule data capable of dynamically corresponding to the number of pins of the logic component. A hardware description generation device having a description generation unit is provided.

Further, an input / output device may be provided, and the hardware description language generated by the hardware description generation device may be displayed on the display unit of the input / output device.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1 is a block diagram showing an embodiment of a hardware description automatic generation system of the present invention, FIG. 2 is a flow chart showing an operation procedure of the hardware description generation device in FIG. 1, and FIG. 3 is an example of conversion rule data in FIG. In the figure showing
It is an example of conversion rule data of a bit counter. FIG. 4 is a diagram showing an example of the hardware description language generated using the conversion rule data shown in FIG. 3, and is an example of the hardware description language generated from the 2-bit counter and the 4-bit counter, respectively.

As shown in FIG. 1, this embodiment comprises an input / output device 1, an arithmetic processing device 2, a data storage device 3 and a hardware description generation device 4, and is composed of hardware or software. There is. The data storage device 3 stores circuit diagram data 31 of a logic circuit diagram, conversion rule data 32 that can dynamically correspond to the number of pins of a logic component, and hardware description data 33. The hardware description generation device 4 is composed of a logical connection extraction unit 41 and a description generation unit 42.

Next, the operation of the hardware description generation apparatus of this embodiment will be described with reference to FIGS. First, the logical connection extraction unit 41 reads the circuit diagram data 31 from the data storage device 3 via the arithmetic processing unit 2 (step S10). If there is no circuit diagram data, the process proceeds to reading conversion rule data (S13). If there is circuit diagram data 31, the logic component is recognized from this circuit diagram data 31, and the number of pins is further counted (S11) and read. The circuit connection is extracted from the circuit diagram data 31 (S12).

Next, the description generation section 42 reads the conversion rule data 32 as shown in FIG. 3 from the data storage device 3 (S13). Here, the conversion rule data corresponding to the logical component is searched and read. Next, a hardware description corresponding to the number of pins of the logical component and a hardware description language of the extracted circuit connection are generated (S14).

The generated hardware description data 33 is stored in the arithmetic processing unit 3, and the arithmetic processing unit 2 further reads this hardware description data 33 and outputs it to the input / output unit 1.
, And the hardware description language as shown in FIG. 4 is displayed.

[0012]

As described above, the automatic hardware description generation method of the present invention reduces the number of conversion rule data by using the conversion rule data which can dynamically correspond to the number of pins of the logic parts of the circuit. This has the effect of reducing the man-hours for generating conversion rule data.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a hardware description automatic generation system of the present invention.

FIG. 2 is a flowchart showing an operation procedure of the hardware description generation device in FIG.

3 is a diagram showing an example of conversion rule data in FIG.

4 is a diagram showing an example of a hardware description language generated using the conversion rule data shown in FIG.

[Explanation of symbols]

 1 Input / output device 2 Arithmetic processing device 3 Data storage device 4 Hardware description generation device 31 Circuit diagram data 32 Conversion rule data 33 Hardware description data 41 Logical connection extraction unit 42 Description generation unit

Claims (3)

[Claims] 1. When generating a hardware description language that represents a logical function of a circuit from a circuit diagram that represents a logic circuit, the hardware description language is defined by using conversion rule data that can dynamically correspond to the number of pins of a logical component. A hardware description automatic generation method characterized by automatic generation. 2. The logical connection information is converted into a hardware description language by using a logical connection extraction unit that extracts a logical connection of the logical circuit and the conversion rule data that can dynamically correspond to the number of pins of the logical component. The hardware description automatic generation system according to claim 1, further comprising a hardware description generation device having a description generation unit. 3. The automatic hardware description according to claim 2, further comprising an input / output device, wherein the hardware description language generated by the hardware description generation device is displayed on a display unit of the input / output device. Generation method.