JPH05334238A - Bus size conversion circuit - Google Patents

Abstract

PURPOSE:To provide a bus size conversion circuit in which a soft corresponding to a hard whose bus size is different from the soft can be allowed to have an interchangeability by providing a peripheral circuit in an MPU which is not equipped with a dynamic bus-sizing function. CONSTITUTION:This circuit is equipped with a data latch buffer 11 which latches the first small bus size data 16 K times (K is an integer), and converts the data into the second normal bus size data 15, and a control part 13 which prepares a memory control signal for controlling the latch operation. The control part 13 prepares a buffer control signal 18 and a memory control signal 19 K times in response to an execution cycle start signal 17 outputted by an MPU 10. The first small bus size data 16 are latched K times, and converted into the second normal bus size data 15 by the execution cycle start signal 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer peripheral circuit.

[0002]

2. Description of the Related Art A commercially available MPU (Micro Processor)
Unit) includes those with and without the dynamic bus sizing function. For example, the MC68030 from Motorola has it, but the MC68040 does not.

M without dynamic bus sizing function
The PU cannot execute access to a data bus having an unspecified size. To run
It was necessary to change the source software for bit access according to the data bus width of the device.

[0004]

As described above, the MPU in which access to data having different bus sizes is conventionally prohibited is not compatible with software compatible with MPUs having different bus sizes. The source software had to be changed to run this software.

An object of the present invention is to provide a bus size conversion circuit which converts a smaller bus size data into a bus size data of a prescribed size by a simple MPU peripheral circuit and does not need to change the source software. It is in.

[0006]

According to the present invention, there is provided a bus size conversion circuit for converting data of a first bus size into second data having a bus size K times (K is an integer) the first bus size. And a control unit that generates the memory control signal K times in response to the execution cycle start signal output from the MPU, and stores the first data K times in response to the memory control signal and converts the first data into second data. And a buffer for conversion.

[0007]

In response to one execution cycle signal output from the MPU, the control unit generates and outputs the memory control signal K times. In response to the memory control signal, the data of the small first bus size is latched K times to form the second data of the specified size.

[0008]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows an embodiment of the dynamic bus sizing circuit of the present invention, and shows a functional block diagram of the dynamic bus sizing for a 16-bit memory. The dynamic bus sizing function refers to a function of performing an execution cycle in four or two times when a 32-bit access is made from the MPU to a device having an 8-bit or 16-bit data bus.

The dynamic bus sizing circuit is an MC
68040MPU10, data latch buffer 1
1, an I / O control memory 12 and a control unit 13. The data bus 15 of the MC68040MPU 10 is connected 16 to the output terminal of the data latch buffer 11 and the input terminal of the data latch buffer 11 to the output terminal of the I / O control memory 12. The control signal 17 of the MPU 10 is sent to the input terminal of the control unit 13, and the control unit 1
The buffer control signal 18 of the output signals that have passed 3
Is connected to the data latch buffer 11, and the memory control signal 19 is connected to the I / O control memory 12.

The data latch buffer 11 holds 16 bits / data output from the I / O control memory 12 for every 2 data, and makes 32 bits / data. The I / O control memory 12 is provided for timing with the access of the MPU 10. The control unit 13 uses the MPU 1
This is a unit for generating a control signal for organizing data into 32 bits / data in synchronization with the control signal 17 of 0. The form of the control signal generated by the control unit 13 is shown in FIG.

The timing chart of FIG. 2 shows the forms of the input signal 17 and the output signals 18 and 19 of the control unit 13. The inverted TS signal 21 in the figure is an access signal output from the MPU 10 to the memory 12. Also, inversion T
The A signal 22 is a response signal to the inverted TS signal 21. The control unit 13 receives the 1 inverted TS signal 21 output from the MPU 10, outputs the memory control signal to the I / O control memory 12 twice, and outputs the inverted TS signal 21 to the I / O control memory 12 after the inverted TS signal 21 is generated. The access is executed twice and the inverted TA signal 22 is output to the MPU 10. The I / O control memory 12 receives two accesses from the control unit 13 and outputs two 16 bits / data in response to the two accesses. Two 16 output from the I / O control memory 12
The bit / data is latched by the data latch buffer 11. The two 16 bits / data latched by the data latch buffer 11 are read by the MPU 10 as one 32 bits / data.

Through the above processing, 32-bit access can be performed to a device having a 16-bit data bus width without changing software.
For a device having a data bus width of 8 bits / data, the same result as above can be obtained by accessing the I / O control memory four times with respect to the inverted TS signal 21 of the MPU.

[0013]

By providing the bus size conversion circuit of the present invention as a peripheral circuit of the MPU, a function equivalent to that of the MPU having a dynamic bus sizing function is produced. With this function, software compatible with MPUs having different bus sizes can be made compatible with each other.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing a circuit configuration of a bus size conversion circuit of the present invention.

FIG. 2 is a time chart diagram showing the operation of FIG.

[Explanation of symbols]

 10 MPU 11 Data Latch Buffer 12 I / O Control Memory 13 Controller

Claims (1)

[Claims] 1. A bus size conversion circuit for converting data of a first bus size into second data having a bus size K times (K is an integer) the first bus size, wherein M is a bus size conversion circuit.
A control unit for generating a memory control signal K times in response to an execution cycle start signal output from the PU, and the first data for the K data in response to the memory control signal.
A bus size conversion circuit comprising: a buffer that stores the data twice and converts the data into second data.