JPH053305A - Semiconductor storage - Google Patents

Abstract

PURPOSE:To provide a non-volatile memory enabling high speed and easy rewriting of data and suitable for high integration. CONSTITUTION:A memory cell M is composed by connecting one electrode E1 of a ferroelectric capacitor Z1 to a bit line BL via an NMOS transistor N1 the gate of the NMOS transistor N1 to a word line WL, and the other electrode E2 of the ferroelectric capacitor Z1 to a drive line DL. The drive line DL is connected to the word line WL via a delay circuit. Thus, unlike in the case of EPROMs, data can be rewritten only by controlling the electric potential of the bit line BL and the word line WL. Moreover, the memory cell, which is composed of a transistor and a ferroelectric capacitor, is downside.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a nonvolatile memory using a ferroelectric capacitor.

[0002]

2. Description of the Related Art A semiconductor memory device includes a volatile memory capable of storing information only while power is on,
There is a non-volatile memory that can store information even after the power is turned off, and a volatile memory is an SRAM.
(Static Random Access Memory) and DRAM (Dynamic Random Access Memory)
AM), and the non-volatile memory is a mask ROM (M
ask Read Only Memory), PROM (Programmable RO
M), EPROM (ErasablePROM), EEPROM (Elec
trically Erasable and Programmable ROM) etc.

Among non-volatile memories, EPROM
Is a ROM in which the stored contents can be rewritten as many times as the RAM, and the floating gate is formed between the control gate and the channel.
A FET (MOS field effect transistor) is generally used, which irradiates ultraviolet rays to discharge the electric charge in the floating gate to erase the stored contents and to apply a high voltage between the control gate and the drain. Writing is performed by utilizing the fact that hot electrons generated by the breakdown phenomenon at the time of remaining remain in the floating gate.

Further, the EEPROM is a ROM whose stored contents can be electrically rewritten, and has an advantage that the contents can be erased without being irradiated with ultraviolet rays.

[0005]

However, for writing and erasing information in the floating gate type MOS-FET, a time on the order of ms and a high electric field on the order of 10 ⁷ V / cm are required, and Since the writing time of information in the EEPROM is much longer than that of a normal DRAM or the like, the conventional nonvolatile memory realizes writing and erasing of data in the same cycle like a normal SRAM or DRAM. I couldn't.

The present invention has been made by paying attention to the unsolved problem of the conventional technique, and can easily write and read data in a short time like a conventional SRAM or DRAM. An object of the present invention is to provide a nonvolatile memory that can be used.

[0007]

In order to achieve the above object, in a semiconductor memory device according to the present invention, one electrode of a ferroelectric capacitor is connected to a bit line via a pass transistor and the pass transistor is connected. Is connected to a word line, the other electrode of the ferroelectric capacitor is connected to a drive line, and the drive line is activated after a predetermined time has elapsed since the word line was selected. Was established.

[0008]

When the data is written, the potential of the bit line becomes high level or low level according to the data to be written, and when the word line is selected and the pass transistor is turned on, the potential of the bit line is changed to the ferroelectric capacitor. Is supplied to one of the electrodes.

Immediately after the pass transistor is turned on, the drive line control means does not raise the drive line, so a low level potential is supplied to the other electrode of the ferroelectric capacitor. At this time, if the potential of the bit line is low level, no potential difference occurs between both electrodes of the ferroelectric capacitor, but if the potential of the bit line is high level, the potential difference between both electrodes of the ferroelectric capacitor is Occurs, and a predetermined charge is accumulated in the ferroelectric capacitor.

Then, when a predetermined time elapses after the word line is selected, the drive line control means raises the drive line, so that the potential of the other electrode of the ferroelectric capacitor becomes high level. At this time, if the potential of the bit line is at a low level, a potential difference occurs between both electrodes of the ferroelectric capacitor, so that a predetermined charge is accumulated in the ferroelectric capacitor and the potential of the bit line is at a high level. If so, the potential difference between both electrodes of the ferroelectric capacitor becomes zero, but since the polarization of the ferroelectric substance draws a hysteresis (hysteresis) curve with respect to the alternating electric field, even if the potential difference becomes zero, the predetermined electric charge remains. Maintain the accumulated state.

After that, the selection of the word line is released,
Even if the drive line goes to a low level, as described above, the ferroelectric draws a hysteresis curve with respect to the AC electric field, so that the ferroelectric capacitor accumulates electric charges according to the potential of the bit line. Become. Then, the charge finally stored in the ferroelectric capacitor is determined according to the potential of the bit line, which means that the information is stored in the ferroelectric capacitor, and even if the power is turned off, the ferroelectric capacitor is stored. Since the electric charge accumulated in the body capacitor is stored for a long time (usually 10 years or more), it functions as a non-volatile memory.

On the other hand, at the time of reading data, when the word line is selected and the pass transistor is turned on, one electrode of the ferroelectric capacitor is connected to the bit line. At this time, the bit line is precharged to a low-level potential, and the drive line control means does not raise the drive line until a predetermined time elapses after the pass transistor is turned on. The potential of the other electrode of the capacitor is at a low level, and there is no potential difference between both electrodes of the ferroelectric capacitor.

Then, after a lapse of a predetermined time from the selection of the word line, the drive line control means raises the drive line, so that the potential of the other electrode of the ferroelectric capacitor becomes high level and both of the ferroelectric capacitors are driven. Although there is a potential difference between the electrodes, one electrode of the ferroelectric capacitor is connected to the bit line, so the potential of the bit line changes according to the charge accumulated in the ferroelectric capacitor. The information stored in the ferroelectric capacitor has been transferred to the bit line.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 6 are views showing an embodiment of the present invention. First, the configuration will be described. FIG. 1 is a circuit diagram showing an overall configuration of a semiconductor memory device to which the present invention is applied.
(N + 1) ^two storage cells M ₀₀ ~M _NN well as arranged in a matrix, corresponding to the memory cell M ₀₀ ~M _NN arranged in a matrix, the row direction (N + 1) Book The word lines WL _{0 to} WL _N and (N + 1) drive lines DL _{0 to} DL _N are (N +) in the column direction.
1) The bit lines BL _{0 to} BL _N are arranged.

Each memory cell M _{00 to} M _NN has an NMOS transistor (N-channel MOS transistor) N ₁ as a pass transistor and a ferroelectric capacitor Z ₁ as shown in the enlarged view of FIG. One electrode E ₁ of the dielectric capacitor Z ₁ is connected to the NMOS transistor N _1.
1 is connected to the bit line BL, the other electrode E ₂ of the ferroelectric capacitor Z ₁ is connected to the drive line DL, and the gate of the NMOS transistor N ₁ is connected to the word line WL.

Here, the ferroelectric capacitor Z ₁ is shown in FIG.
As shown in, when a voltage is gradually applied in the positive direction from the state where there is no charge and the applied voltage between the electrodes E ₁ and E ₂ is zero (point A), the polarization arranged in the applied electric field is suddenly increased. To a certain value or more, the charge increases relatively smoothly, and a curve AB is drawn. Since the polarization of the ferroelectric substance draws a hysteresis (hysteresis) curve with respect to the AC electric field, the voltage is gradually lowered from the state of the point B and the electrodes E ₁ and E _{2 are}
The electric charge does not become zero even if the potential difference between them is zero, and the state of the remanent polarization point C is taken.

To make the charge zero, it is necessary to apply a voltage in the negative direction, and when the voltage in the negative direction is further increased, the charge also increases in the opposite direction to draw a curve B-C-D, and D
If the voltage difference is gradually raised from the state of the point to make the potential difference between the electrodes E ₁ and E ₂ zero, the state of the remanent polarization point E is taken, and if the voltage is further increased, the curve D-E-B is drawn. become.

That is, since the ferroelectric capacitor Z ₁ takes one of the states of the remanent polarization point C or E when the applied voltage is set to zero after applying the voltage, 1-bit information is obtained depending on these two states. Can be stored, and since the information is stored for a very long time (usually 10 years or more), it can be used as a non-volatile memory. Returning to FIG. 1, the word lines WL _{0 to} WL _N are connected to the row decoders RD _{0 to} RD _N , respectively.

Then, the row decoders RD _{0 to} RD
_N is an AND circuit to which one of the Y address signals Y _{0 to} Y _N and the precharge signal P _r are input, and Y
Since only one of the address signals Y _{0 to} Y _N is selected at the same time, only one of the row decoders RD _{0 to} RD _N is selected at the same time and the word lines WL _{0 to} W connected to it.
Launch L _N.

The drive lines DL _{0 to} DL _N are
Word line WL connected to the same memory cells M _{00 to} M _NN
It is connected to _{0 to} WL _N via a delay circuit 1 as a drive line control means. Therefore, the drive lines DL _{0 to} DL _N rise after a predetermined time determined by the delay circuit 1 has passed since the word lines WL _{0 to} WL _N were selected by the row decoders RD _{0 to} RD _N.

On the other hand, the bit lines BL _{0 to} BL _N are grounded via the NMOS transistor N ₂ for precharging and connected to the data input line D _IN via the bit line driver 2 consisting of a two-stage inverter. Has been done. Each bit line driver 2, ..., 2, have undergone output of the column decoder CD ₀ ~CD _N, bit data on the data input line D _IN only when the corresponding column decoder CD ₀ ~CD _N is selected Line BL ₀ ~
Supply to BL _N.

Then, those column decoders CD _{0 to} C
D _N is an AND circuit to which one of the X address signals X _{0 to} X _N and the read / write signal RW are input,
Similar to the Y address signals Y _{0 to} Y _N , the X address signal X ₀
Since to X _N are also selected only one simultaneously, only one column decoder CD ₀ ~CD _N simultaneously is selected, one of the bit line driver 2 and the corresponding drive. Therefore, the data on the data input line D _IN is simultaneously supplied to only one of the bit lines BL _{0 to} BL _N.

The bit lines BL _{0 to} BL _N are also connected to the sense amplifier 3, and the data on the bit lines BL _{0 to} BL _N amplified by the sense amplifier 3 is output via the driver 4 to the data output line. Supplied on D _OUT .
Here, in this embodiment, a so-called current mirror circuit is used as the sense amplifier 3. Specifically, as shown in FIG. 4, the NMOS transistor N ₃ where the potential of the bit line BL is supplied directly, the NMOS transistor N ₄ the potential of the bit line BL is supplied via the inverter 3a, NMOS transistors a PMOS transistor (P-channel MOS transistor) P ₁ connected to the power supply side of the N _3, a PMOS transistor P _2, which is connected to the power source side of the NMOS transistor N _4, they P
It has a PMOS transistor P ₃ interposed between the MOS transistors P ₁ and P ₂ and the power supply V _CC, and the potential between the NMOS transistor N ₃ and the PMOS transistor P ₁ is supplied to the gates of the PMOS transistors P ₁ and P _2. Was
NMOS transistor N ₄ and PMOS transistor P
The potential between ₂ is supplied to the driver 4 as the output of the sense amplifier 3.

As shown in FIG. 1, one of the X address signals X _{0 to} X _N and the precharge signal P _r passed through the delay circuit 6 are input to the gate of the PMOS transistor P ₃ . The output of the AND circuit 5 is supplied via the inverter 3b. The driver 4 is not receiving the output of the column decoder CD ₀ ~CD _N, when the corresponding column decoder CD ₀ ~CD _N is selected only,
The output of the sense amplifier 3 is supplied to the data output line D _OUT .

Therefore, only one data among the bit lines BL _{0 to} BL _N is supplied to the data output line D _OUT at the same time. Next, the operation of this embodiment will be described.
FIG. 5 is a waveform diagram at the time of writing the data of the logical value “1” to the memory cell M _00. First, the write operation will be described with reference to FIG.

That is, in order to perform the write operation, after the read / write signal RW is raised, the X address signals X ₀ to
Of X _N , the X address signal X ₀ corresponding to the memory cell M ₀₀ to be written is raised. Then, the column decoder CD ₀ is selected and the bit line driver 2 becomes drivable.

On the other hand, the precharge signal P _r is raised,
, 5 is set to a high level, but the other input of the AND circuits 5, ..., 5 is one of the X address signals X _{0 to} X _N. , Only the output of the AND circuit 5 to which the address signal X ₀ is supplied becomes high level. Then, the AND circuit 5, ..., 5
Is supplied to the gate of the NMOS transistor N ₂ for precharging which is interposed between the bit lines BL _{0 to} BL _N and the ground, the bit line BL ₀ and the ground are electrically connected to each other. Bit line BL ₀ that was confirmed
Will once stabilize to a low level. The bit line BL ₁
~ _N bit of the bit lines BL ₁ ~ since the NMOS transistor N ₂ interposed between BL _N and ground is off.
BL _N remains floating.

After a sufficient time has elapsed for the bit line BL ₀ to stabilize at a low level, the data input line D _IN
To a high level. When the data of the logical value "0" is stored, the data input line D _IN may be set to the low level at this time. Then, because there is already a bit line driver 2 has a driving state, the potential of the data input line D _IN is supplied to the bit lines BL _0, bit lines BL ₀ goes high.

Next, of the Y address signals Y _{0 to} Y _N , the Y address signal Y corresponding to the memory cell M ₀₀ to be written.
Start up ₀ . Then, since the precharge signal P _r has already risen at this time, the row decoders RD _{0 to} R
Of the D _N , the row decoder RD ₀ is selected and the word line WL ₀ connected to it is raised.

When the word line WL ₀ rises, the NMOS transistors N _{1 of} the memory cells M _{00 to} M _0N connected to it are turned on, and the potentials of the bit lines BL _{0 to} BL _N are changed to those memory cells M _{00 to} M _{00. 0N} ferroelectric capacitor Z
It is supplied to one electrode E _{1 1.} Incidentally, the bit lines BL ₁ to BL _N not selected because they maintain a floating state as described above, NMOS transistor N ₁ is also turned on, there is no effect on the ferroelectric capacitor Z _1.

However, the selected bit line BL
_Since the potential of ₀ is high level due to the data input line D _IN , the potential of _one electrode E ₁ of the ferroelectric capacitor Z ₁ of the memory cell M ₀₀ is high level. At this time, since the drive line DL ₀ is connected to the word line WL ₀ via the delay circuit 1, the potential of the other electrode E ₂ is at a low level, and therefore, the potential between both electrodes E ₁ and E ₂ is low. A potential difference is generated in the ferroelectric capacitor Z ₁ , and the ferroelectric capacitor Z ₁ assumes the state of point D in FIG.

When the drive line DL ₀ rises after a lapse of a predetermined time determined by the delay circuit 1, the potential of the other electrode E ₂ of the ferroelectric capacitor Z ₁ also becomes high level, and both electrodes E ₁ and E _{2 are connected.} The potential difference between them becomes zero, and the ferroelectric capacitor Z ₁ assumes the state of point E in FIG. When the data of the logical value “0” is stored, a potential difference is generated at the time when the drive line DL ₀ rises, the state at the point of FIG. 3B is taken, and then the row decoder RD ₀ is turned off, so that the potential difference again occurs. Is zero, the ferroelectric capacitor Z ₁ adopts the state of point C in FIG.

As described above, at the time of writing data, the ferroelectric capacitor Z ₁ adopts the state of the point of FIG. 3E when the written data is the logical value "1", and the written data is the logical value "0". For example, since the state at point C in FIG. 3 is adopted, 1-bit information is stored as a result, and this state is retained for a long time (usually 10 years or more), so that it substantially functions as a non-volatile memory.

FIG. 6 is a waveform diagram at the time of reading the data stored in the memory cell M _00. The operation at the time of reading the data will be described with reference to FIG. Note that the memory cell M ₀₀ in this, it is assumed that data of a logical value "1" is stored, therefore, the ferroelectric capacitor Z ₁ of the memory cell M ₀₀ is take the state shown in FIG. 3E point There is. That is, also in the case of performing the read operation, like the case of performing the write operation, after the read / write signal RW is raised, it corresponds to the memory cell M ₀₀ to be read out of the X address signals X _{0 to} X _N. The X address signal X ₀ is raised.

Then, the column decoder CD ₀ is selected, and the driver 4 to which the output is supplied is in the drivable state. On the other hand, the precharge signal P _r is raised to bring one input of the AND circuits 5, ..., 5 to a high level, and the other input of the AND circuits 5, ..., 5 is supplied with the X address signals X _{0 to} X _N. Therefore, in this case, only the output of the AND circuit 5 to which the address signal X ₀ is supplied becomes high level.

The output of the AND circuit 5 is inverted by the inverter 3b and supplied to the PMOS transistor P ₃ of the sense amplifier 3, so that each sense amplifier 3 ,.
Of the sense amplifier 3 connected to the bit line BL ₀
Only activated. Further, the outputs of the AND circuits 5, ..., 5 are also supplied to the gate of the precharge NMOS transistor N ₂ interposed between the bit lines BL _{0 to} BL _N and the ground, so that the bit line BL _0. The bit line BL ₀ , which has been indefinite, is electrically connected between the ground and the ground.
Will once stabilize to a low level. The bit line BL ₁
~ _N bit of the bit lines BL ₁ ~ since the NMOS transistor N ₂ interposed between BL _N and ground is off.
BL _N remains floating.

Next, among the Y address signal Y ₀ to Y _N, raises the Y address signal Y ₀ corresponding to storage cell M ₀₀ for reading data. Then, since the precharge signal P _r has already risen at this time, the row decoder R
The row decoder RD ₀ is selected from D _{0 to} RD _N , and the word line WL ₀ connected to it is raised.

When the word line WL ₀ rises, the NMOS transistors N _{1 of} the memory cells M _{00 to} M _0N connected to it are turned on, and among these memory cells M _{00 to} M _0N ,
The potential of _one electrode E ₁ of the ferroelectric capacitor Z ₁ of the memory cell M ₀₀ connected to the precharged bit line BL ₀ becomes low level. Incidentally, the bit lines BL ₁ to BL _N not selected because they maintain a floating state as described above, NMOS transistor N ₁ is also turned on, there is no effect on the ferroelectric capacitor Z _1.

At this time, since the drive line DL ₀ is connected to the word line WL ₀ via the delay circuit 1, the potential of the other electrode E ₂ is at a low level, so that the electrodes E ₁ and E between both electrodes are low. There is no potential difference between the _two , and the ferroelectric capacitor Z ₁ maintains the state at point E in FIG. Then, after a lapse of a predetermined time determined by the delay circuit 1, the drive line D
When L ₀ rises, the potential of the other electrode E ₂ of the ferroelectric capacitor Z ₁ becomes high level, and both electrodes E ₁ and E ₂
A potential difference occurs between them, and the ferroelectric capacitor Z ₁ shifts from the state at point E to the state at point B in FIG.
_{Since 0} is precharged to a low level, a relatively large potential change (several hundred mV) occurs in the bit line BL ₀ with a change in charge of the ferroelectric capacitor Z ₁ .

[0040] In the case where the data is stored logic value "0" in the ferroelectric capacitor Z ₁ is at the time when the driveline DL ₀ rises, the ferroelectric capacitor Z ₁ is in Figure 3C point state From the point B to the state,
The bit line BL ₀ has a relatively small potential change ( _equation 10).
mV) occurs. Then, the potential of the bit line BL ₀ is supplied to the sense amplifier 3, but if the potential of the bit line BL ₀ is at a high level, the potential is directly supplied N.
Since the MOS transistor N ₃ is turned on and the potential on the drain side thereof becomes low level, the PMOS transistor P 3
₂ turns on. Then, since the potential of the bit line BL ₀ is inverted by the inverter 3a and the supplied NMOS transistor N ₄ is turned off, the PMOS transistor P
The potential between ₂ and the NMOS transistor N ₄ stabilizes at a high level, and this becomes the output of the sense amplifier 3.

On the contrary, when the potential of the bit line BL ₀ is low level, the NMOS transistor N ₃ is turned off,
Since the drain side potential becomes high level, the PMOS
Transistor P ₂ turns off. Then, since the NMOS transistor N ₄ is turned on, the potential between the PMOS transistor P ₂ and the NMOS transistor N ₄ is stabilized at a low level, and this becomes the output of the sense amplifier 3.

That is, the potential change of the bit line BL ₀ is amplified by the sense amplifier 3 and supplied to the data output line D _OUT through the driver 4. Therefore, by reading the potential of the data output line D _OUT , Whether the data stored in the memory cell M ₀₀ has the logical value “1”,
It can be detected whether the logical value is "0". As described above, according to the configuration of the present embodiment, since the characteristic of the ferroelectric capacitor Z ₁ capable of accumulating charges for a long time is utilized, it substantially functions as a non-volatile memory, and moreover, rewrites data. , like ordinary DRAM and SRAM, etc. bit lines BL ₀ to BL _N and the word lines WL ₀ to WL _N
Conventional EPROM because it can be done only by controlling the potential of
It can be performed easily and at high speed, unlike EEPROMs and EEPROMs.

Further, each of the memory cells M _{00 to} M _NN is replaced by one N
Since it is composed of the MOS transistor N ₁ and one ferroelectric capacitor Z ₁ , it is very small and suitable for high integration. Further, as is clear from comparison between FIG. 5 and FIG. 6, the control at the time of writing data and the control at the time of reading data are almost the same, so that it is necessary to provide a new control circuit or the like. There is also the advantage of not having it.

In this embodiment, the bit line BL
_{Since the} precharge NMOS transistor N ₂ is turned on / off by the output of the AND circuits 5, ..., 5 provided individually for each _{0 to} BL _N, bit lines other than the selected bit line are pre-selected. Since the floating state is maintained without being charged, even if the NMOS transistor N ₁ is turned on and the drive line DL rises, the ferroelectric capacitor Z ₁ of the unselected memory cell is not affected at all.

This means that for the ferroelectric capacitor Z ₁ whose function deteriorates according to the number of times the history curve as shown in FIG. 3 is drawn, unnecessary access will be eliminated, and therefore the life is expected to be greatly extended. It is possible and leads to improvement of reliability.

[0046]

As described above, according to the present invention,
Since the data can be stored by utilizing the characteristics of the ferroelectric capacitor, it functions as a non-volatile memory, and the data can be rewritten easily and at high speed.
Since it is composed of one transistor and one ferroelectric capacitor, it is suitable for high integration.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an overall configuration of an embodiment of the present invention.

FIG. 2 is an enlarged view of a memory cell.

FIG. 3 is a graph showing polarization characteristics of a ferroelectric substance.

FIG. 4 is a circuit diagram showing an example of a sense amplifier.

FIG. 5 is a waveform diagram at the time of writing data.

FIG. 6 is a waveform diagram at the time of reading data.

[Explanation of symbols]

1 Delay Circuit (Drive Line Control Means) M _{00 to} M _NN Storage Cell BL _{0 to} BL _N Bit Line WL _{0 to} WL _N Word Line DL _{0 to} DL _N Drive Line Z ₁ Ferroelectric Capacitor N ₁ NMOS Transistor (Pass Transistor) )

Claims (1)

Claim: What is claimed is: 1. One electrode of a ferroelectric capacitor is connected to a bit line via a pass transistor, and the gate of the pass transistor is connected to a word line. A semiconductor memory device comprising drive line control means for connecting the other electrode to a drive line, and for raising the drive line after a predetermined time has elapsed since the word line was selected.