JPH05327784A - Integrated circuit for bus interface - Google Patents

Abstract

PURPOSE:To improve the communication quality and to facilitate the maintenance by detecting an abnormal state of a communication path by a result of decision of potential of a low potential side and a high potential side of a twist pair cable. CONSTITUTION:A voltage between terminals A, B, a voltage between a reference voltage ref2 in the vicinity of a ground potential and the terminal B, and a voltage between a voltage ref3 in the vicinity of a power supply voltage and the terminal A are detected by comparators 11, 12 and 13, respectively, and in a logic synthesizing circuit 14, logic of a signal of a bus is decided from three outputs. In a fault diagnostic circuit 16, based thereon, an abnormal state of a communication path is detected and diagnosed and in accordance with a result of diagnosis, an output circuit is adjusted so that the potential of the communication path becomes normal. In such a way, by providing a fault diagnostic function in a bus interface circuit, the communication quality is improved, and the maintenance can be facilitated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit for a serial interface, and more particularly to a failure diagnosis function of a communication path of a serial interface.

[0002]

2. Description of the Related Art In a conventional integrated circuit for a bus interface, the logic level is determined by the magnitude of the potential difference between twisted pair cables. In such a serial bus system, in order to secure communication quality,
Specifications are defined in software.

In terms of software, it is required that the error correction code and acknowledge response do not malfunction from the viewpoint of hardware, even if a defective open terminal unit is connected.

[0004] This is extremely difficult when a failure occurs, in order to extract the problem of the communication path and to identify the defective unit, it is necessary to observe the potential of the twisted pair cable while actually communicating. is there.

[0005]

In this conventional integrated circuit for a bus interface, when the communication is normally performed, the S / N ratio at the time of communication is deteriorated and which part of the communication path is defective. Can't know. In addition, there is a problem that it is difficult to analyze the failure when the communication becomes abnormal.

An object of the present invention is to provide an integrated circuit for a bus interface that facilitates improvement and maintenance of communication quality.

[0007]

In order to achieve the above object, an integrated circuit for a bus interface according to the present invention is a serial bus system which uses a two-wire cable whose both ends are terminated by resistors as a communication path. In the integrated circuit for interface, a first comparator which receives the first and second terminals connected to the two-wire type cable and a second comparator which receives the reference voltage near the ground potential and the second terminal as an input A comparator, a third comparator that receives a reference voltage near the power supply voltage and the first terminal as inputs, a logic synthesis circuit that determines a bus signal from the outputs of the three comparators, and a receiving circuit that receives the bus signal. And a failure diagnosis circuit that detects an abnormality in the communication path from the outputs of the three comparators.

Further, when a communication abnormality is detected, the output circuit is adjusted so that the bus potential becomes a normal value.

[0009]

The potential of the low potential side (B terminal) and the potential of the high potential side (A terminal) of the twisted pair cable are determined, and the abnormality of the communication path is detected from the determination result.

[0010]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.

In the figure, a first conducting wire A connected to V _DD via two terminating resistors R _A1 and R _A2 and a second conducting wire B grounding the two terminating resistors R _B1 and R _B2. The integrated circuit 1 for bus interface of the present invention is connected to the twisted pair cable thus constructed.

According to the present invention, a first comparator 11 having two terminals A and B connected to a twisted pair cable as inputs, a reference potential ref2 near the ground potential, and a terminal B are provided.
To the second comparator 12 that _receives
A third comparator 13 that receives the reference voltage ref3 and the terminal A in the vicinity, and the three comparators 11 and 1
Inputting the outputs of 2 and 13, a logic synthesizing circuit 14 for determining the logic of the bus signal, and separating the data from the bus signal,
It is provided with a receiving circuit 15 for outputting to an internal logic, and a failure diagnosing circuit 16 for inputting outputs of three comparators and detecting an abnormality of a communication path from a combination thereof.

It should be noted that FIG. 1 shows only an input circuit, and an output circuit integrated on the same semiconductor substrate and connected to terminals A and B is omitted.

Now, when the potential difference between the terminals A and B is less than 1 V, defining the logic level as H, the comparator 11 should give an offset of -1 V to the non-inverting input side connecting the terminal B.

Further, r on the inverting input side of the comparator 12
If ef2 is 0.5V, the potential of terminal B is 1 / 2V _DD
Since it is −0.5 V or more, the output of the comparator 12 becomes H.

Ref on the non-inverting input side of the comparator 13
3 is V _DD -0.5V, the potential of terminal A is 1/2
Since it is less than V _DD +0.5 V, the output of the comparator 13 becomes H. Therefore, the three comparators 11, 1
The outputs of 2 and 13 are all H.

Assuming that the terminating resistor R _{A1 of} which one end is connected to V _DD in one of the communication paths is short-circuited and the terminal A is short-circuited to V _DD , the output of the comparator 13 becomes L. Further, the potential difference between the terminals A and B becomes 1 V or more, and the output of the comparator 11 also becomes L.

In the case of this malfunction, the logic synthesis circuit 14
H is output to the receiving circuit 15, and the failure diagnosis circuit 16 determines that there is a short circuit failure.

A GND short-circuit defect on the other communication path can be similarly determined.

In the above-mentioned example, only the short-circuit defect was detected, but an example of open defect detection will be shown below.

Ref2 = 0.5 V, ref3 = V _DD −
The outputs of the comparators 11 to 13 when the voltage is 0.5 V are all H even when the terminal A is open, and cannot be distinguished from those in the normal state. Therefore, ref2 = 1 / 2V _DD + 0.5V,
When changing to ref3 = 1 / 2V _DD −0.5V, the outputs of the comparators 11, 12, and 13 are H, L, and L at the normal time.
On the other hand, when terminal A is open, H, L, H
Becomes

Therefore, according to the flow shown in FIG. 2, the logic synthesis circuit 14 outputs the data L or H to the reception circuit 15,
The failure diagnosis circuit 16 determines an open or short defect.

Thus, when the abnormality of the communication path is detected, when it is the signal output by itself, and when there is a defect that one of the terminating resistors is open, the output current is reduced and the potential of the communication path is reduced. The output circuit can be adjusted to have a normal value.

A short circuit defect between the terminals A and GND and between the terminals B and VDD is always judged as the data H, and therefore is detected by a mismatch with its own output.

[0025]

As described above, the present invention has the effect that the communication quality can be easily improved and maintained because the bus interface circuit has the failure diagnosis function.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is an operation flow.

[Explanation of symbols]

1 Interface IC 11, 12, 13 Comparator 14 Logic Synthesis Circuit 15 Reception Circuit 16 Fault Diagnosis Circuit R _A1 , R _A2 , R _B1 , R _B2 Resistance

Claims (2)

[Claims] 1. An integrated circuit for an interface of a serial bus system in which a communication line is a two-wire type cable whose both ends are terminated with resistors, and first and second terminals connected to the two-wire type cable are provided. A first comparator that receives the input and a second comparator that receives the reference voltage near the ground potential and the second terminal
Comparator, and a third terminal that receives the reference voltage near the power supply voltage and the first terminal as input
, A logic synthesizing circuit that determines a bus signal from the outputs of the three comparators, a receiving circuit that receives the bus signal, and a failure diagnosis circuit that detects an abnormality of the communication path from the outputs of the three comparators. An integrated circuit for a bus interface characterized by having. 2. The integrated circuit for a bus interface according to claim 1, wherein the output circuit is adjusted so that the potential of the bus becomes a normal value when a communication abnormality is detected.