JP2000088907A - Load diagnosing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a load diagnosing circuit capable of alleviating a load of software processing. SOLUTION: A driving circuit 12 having a mirror MOSTr 17 for connecting a power MOSTr 15 to a gate terminal and connecting the MOSTr 15 and a source terminal to a ground and a switch MOSTr 13 for constituting a current mirror circuit for driving a load by the MOSTr 15 if a drain terminal and the gate terminal of the MOSTr 15 are short-circuited between the MOSTr 15 and the MOSTr 17 is constituted. Further, a predetermined current is supplied from a current source circuit 19 to the drain terminal of the MOSTr 17 to input a drain voltage of the MOSTr 17 to one end and to input a drive signal to the other end, and an AND of both the input signals is output from an AND gate 25.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention
The present invention relates to a load diagnostic circuit capable of detecting a load abnormality.

[0002]

2. Description of the Related Art Conventionally, as a load diagnosis circuit for detecting disconnection even when driving a load, Japanese Patent Application Laid-Open No. 7-1013 shown in FIG.
No. 29, "Inductance load diagnostic circuit" has been reported.

[0003] When a load is driven, the CPU 101
When the drive input signal output from the switch is set to the "H" level and the disconnection state of the relay load is diagnosed, the drive input signal is set to the "L" level for a predetermined time t which does not hinder the contact drive by holding the relay contact. I try to switch.

When this drive input signal is switched to "L" level, a power MOS transistor (hereinafter referred to as "power MOSTr") 109 changes from an on state to an off state, and as shown in FIG. t
During the rise, the voltage integrated by the integration circuit 113 is generated at the monitor output. In particular, when the load has an inductance component such as the relay 111, a surge voltage (a) is generated in the solenoid coil by electromagnetic induction, so that a remarkable voltage as an integrated value appears as a monitor output signal.

On the other hand, when the load is driven, the wiring connected to the relay 111 from the output terminal of the load diagnostic circuit 103 and the relay 1 are connected.
When the solenoid coil 11 is disconnected, as shown in FIG. 7, even if the power MOS Tr is turned off for a predetermined time t, the drain voltage of the power MOS Tr 109 does not increase. b) is output.

Accordingly, when the drive input signal is set to the "L" level for a predetermined time t, the CPU 101 performs A / D conversion of the voltage level appearing at the monitor output and monitors the voltage.
The disconnection of the relay load can be detected.

[0007]

However, the predetermined time t which does not hinder the driving of the relay load, that is, the time during which the load is kept in the non-driving state at the time of diagnosis, is equal to the load by the solenoid coil provided on the relay 111 and the contact. Since it depends on the characteristics and the voltage level generated in the integration circuit 113 also changes, it is necessary to individually perform software processing in consideration of the operation characteristics of a relay or the like that actually becomes a load.

Further, it is necessary to output an off-pulse used for diagnosis periodically for a predetermined time t when driving the load, and furthermore, to output an output signal from the integrating circuit 113 to the A
Since it is necessary to input data from the / D port and monitor the data after A / D conversion, there is a problem that the load of software processing increases.

[0009] The present invention has been made in view of the above,
It is an object of the present invention to provide a load diagnosis circuit that can reduce a load imposed by software processing.

[0010]

According to the first aspect of the present invention,
In order to solve the above-mentioned problem, in a load diagnosis circuit that drives a first transistor connected to a load in accordance with a drive signal input from the outside and diagnoses a connection state of the load, A second transistor connecting the gate terminals together, connecting the first transistor and the source terminal to the ground, and short-circuiting the drain terminal and the gate terminal of the first transistor according to the drive signal. A drive circuit comprising: a third transistor that drives the load by the first transistor and forms a current mirror circuit between the first and second transistors; and a drain terminal of the second transistor. And a current source circuit for supplying a predetermined current to the first transistor and a drain voltage of the second transistor. An AND circuit for inputting a drive signal to the other end and outputting a logical product of both input signals, wherein the AND circuit is configured to drive the load by a drain voltage of the second transistor when the load is driven by the drive signal. The gist of the present invention is to diagnose the connection state.

According to a second aspect of the present invention, in order to solve the above-mentioned problem, a first transistor connected to a load is driven in accordance with a drive signal input from the outside, and a connection state of the load is diagnosed. In a load diagnosis circuit, a second transistor that connects the first transistor to a gate terminal and connects the first transistor and a source terminal to the ground; and a first transistor that responds to the drive signal. A third transistor that drives the load by the first transistor when the drain terminal and the gate terminal are short-circuited and forms a current mirror circuit between the first and second transistors. A drive circuit, a current-voltage conversion circuit that converts a voltage value proportional to a current value flowing through a drain terminal of the second transistor, A reference voltage generation circuit that generates a first reference voltage lower than the source voltage and generates a second reference voltage lower than the first reference voltage; and a voltage value output from the current-voltage conversion circuit is a first voltage. And a voltage comparison circuit that compares which voltage range is represented by the second reference voltage, and a comparison result output from the voltage comparison circuit is input to one end, and the drive signal is input to the other end, An AND circuit that outputs an AND of both input signals, wherein the AND circuit diagnoses a connection state of the load based on a comparison result output from the voltage comparison circuit when the load is driven by the drive signal. Is the gist.

According to a third aspect of the present invention, in order to solve the above-mentioned problem, the voltage comparison circuit is configured such that a voltage value output from the current-voltage conversion circuit is between a first reference voltage and a second reference voltage. In this case, the gist is to output a comparison result indicating that the connection state of the load is normal.

According to a fourth aspect of the present invention, in order to solve the above-mentioned problem, the voltage comparison circuit includes a voltage range in which a voltage value output from the current-voltage conversion circuit is higher than a first reference voltage or a second voltage range. When the load is in a voltage range lower than the reference voltage, the gist is to output a comparison result indicating that the load is in a short-circuit state or a disconnection state.

[0014]

According to the first aspect of the present invention, the first transistor and the gate terminal are connected to each other, and the first transistor and the source terminal are connected to the ground.
When the drain terminal and the gate terminal of the first transistor are short-circuited in accordance with the drive signal and the drive signal, the first transistor drives the load,
And a third transistor which forms a current mirror circuit between the second transistor and the second transistor. Further, a predetermined current is supplied from the current source circuit to the drain terminal of the second transistor, and the drain voltage of the second transistor is input to one end, and the drive signal is input to the other end to calculate the logical product of both input signals. Output from the AND circuit. Here, when the load is driven by the drive signal, the connection state of the load is diagnosed based on the drain voltage of the second transistor, and the diagnosis result is output from the AND circuit. Therefore, the normal state or the disconnected state is diagnosed as the connection state of the load. For example, C that outputs a drive signal
When this diagnosis result is output to the PU, the connection state of the load can be immediately diagnosed when the load is driven, and the load of software processing as in the related art can be reduced.

According to the second aspect of the present invention, the second transistor connects the first transistor to the gate terminal, connects the first transistor and the source terminal to the ground, Accordingly, when the drain terminal and the gate terminal of the first transistor are short-circuited, a load is driven by the first transistor and a third transistor forming a current mirror circuit between the first and second transistors And a driving circuit having the following. Further, the current-voltage conversion circuit converts the current value into a voltage value proportional to the current value flowing through the drain terminal of the second transistor, generates a first reference voltage lower than the power supply voltage, and generates a first reference voltage lower than the first reference voltage. A low second reference voltage is generated by a reference voltage generation circuit, and a voltage comparison circuit compares a voltage value output from the current-voltage conversion circuit with a voltage range represented by the first and second reference voltages. And
The comparison result output from the voltage comparison circuit is input to one end, and the drive signal is input to the other end to output the logical product of both input signals from the logical product circuit. here,
When the load is driven by the drive signal, the connection state of the load is diagnosed based on the comparison result output from the voltage comparison circuit, and the diagnosis result is output from the AND circuit. For example, the diagnosis result is output to the CPU that outputs the drive signal. In this case, the connection state of the load can be diagnosed immediately at the time of driving the load, and the load of the conventional software processing can be reduced.

According to the third aspect of the present invention, in the voltage comparison circuit, the voltage value output from the current-to-voltage conversion circuit falls within a voltage range between the first reference voltage and the second reference voltage. In some cases, since a comparison result indicating that the connection state of the load is normal is output, it is possible to immediately diagnose that the connection state of the load is normal when the load is driven.

According to the fourth aspect of the present invention, the voltage comparison circuit is configured such that the voltage value output from the current-to-voltage conversion circuit is higher than the first reference voltage or lower than the second reference voltage. When the load is in the low voltage range, a comparison result indicating that the load is in the short-circuit state or the disconnection state is output, so that it is possible to immediately diagnose that the connection state of the load is abnormal when the load is driven.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a diagram showing a system configuration of a load diagnosis circuit according to a first embodiment of the present invention.

The CPU 1 outputs a drive input signal of "H" level from the output port to the load diagnosis circuit 3 to drive the relay 5 serving as a load, and outputs a monitor output signal output from the load diagnosis circuit 3. Is input through the input port and monitored to diagnose the disconnection state of the relay.

When a drive input signal of “H” level is input from the output port of the CPU 1, the load diagnosis circuit 3 connects one end of a solenoid coil provided on the relay 5 to G.
It is driven to the ND level, diagnoses the connection state with the relay 5, and outputs it to the CPU 1 as a monitor output signal. The relay 5 has a solenoid coil having one end connected to the power supply VB, excites according to a drive output signal output from the load diagnosis circuit 3, and closes a relay contact according to excitation of the solenoid coil.

Here, the configuration of the load diagnosis circuit 3 shown in FIG. 1 will be described in detail. The input buffer 11 is a CPU
1, a drive input signal output from an output port provided in the switch MOSTr13 and a gate terminal of the switch MOSTr13 and A
A drive input signal is output to the input b of the ND gate 25.

The switch MOSTr13 has its drain terminal connected to the drain terminal of the power MOSTr15, its source terminal connected to the gate terminal of the power MOSTr15, and receives an "H" level drive input signal from the input buffer 11. When input is made, it turns on.

The power MOS 15 is connected to one end of a solenoid coil provided on the relay 5 serving as an external load and a switch M.
The drain terminal of OS13 is connected to its own drain terminal, its own source terminal is grounded to GND, and its own gate terminal is connected to the source terminal of switch MOS13, the gate terminal of mirror MOSTr17 and the pull-down grounded to GND. One end of the resistor R1 is connected.

The mirror MOS Tr 17 has a gate terminal connected to the source terminal of the switch MOS 13 and a power MOS transistor.
The gate terminal of Tr15 is connected to one end of a pull-down resistor R1 grounded to GND, and its drain terminal is connected to the source terminal of MOSTr21 constituting the current source circuit 19 and the input a of AND gate 25, The source terminal is grounded to GND.

When the switch MOSTr13 is turned on, the mirror MOSTr17 and the power MOST17 are turned on.
A so-called current mirror circuit is formed with r15. Therefore, the power MOST is connected to the mirror MOSTr17.
A current of mirror ratio times the current flowing in r15 flows. Here, the mirror ratio is set so that the current flowing through the mirror MOS Tr 17 becomes sufficiently larger than the current from the current source circuit 19 when the power MOS Tr 15 is turned on. When the current mirror circuit is configured by MOSTr, the mirror ratio is
Is proportional to the relationship between the channel width W and the channel length L (hereinafter referred to as W / L ratio). Normally, when designing a current mirror circuit, it is general that the channel length L is fixed and the current ratio is set by the channel width W.

A drive circuit 12 for driving a load is constituted by the power MOS Tr 15 forming the first transistor, the mirror MOS Tr 17 forming the second transistor, and the switch MOS Tr 13 forming the third transistor. It is.

In the current source circuit 19, the MOSTrs 21 and
3 is connected to the power supply VCC, both gate terminals are connected to the source terminal of the MOSTr 23 and one end of the resistor R2, and the other end of the resistor R2 is connected to GND.
Is connected to the so-called current mirror circuit. Here, when a reference current flows from the drain terminal of the MOS Tr23 used for bias to GND via the resistor R2, the gate potential corresponding to the reference current is set to the MOS potential.
The voltage is also applied to the transistor Tr21, and is automatically biased so that the drain current of the MOSTr23 becomes substantially equal to the reference current. A voltage corresponding to the condition for flowing the reference current to the drain terminal is generated between the gate and the source of the MOSTr23. Since this voltage is also applied to the gate terminal of the MOSTr 21 serving as a current source and biases the MOSTr 21,
The MOSTr21 having the same characteristics as the Tr23 is biased under the same conditions, and a current having the same value as the reference current flows through the drain terminal of the MOSTr21, thereby exhibiting a constant current characteristic.

The AND 25 is a so-called AND circuit. The input a is connected to the source terminal of the MOSTr 21 and the mirror MO.
The input b is connected to the output terminal of the input buffer 11, and the output c is output to the input port provided in the CPU 1 as a monitor output signal.

Next, the operation of the load diagnosis circuit 3 will be described with reference to the timing chart shown in FIG. First, the operation when the load connected to the load diagnosis circuit is in a normal state will be described.

As shown in FIG. 2A, when the drive input signal output from the CPU 1 is at the "L" level, the load diagnosis circuit 3 switches the switch M via the input buffer 11.
The “L” level is input to the gate terminal of the OSTr13, and the switch MOSTr13 is in an off state. Therefore, the gate potentials of the power MOS Tr15 and the mirror MOS Tr17 are fixed at the GND level via the pull-down resistor R1.

Accordingly, the power MOS Tr 15 is turned off, and no drive current flows through the solenoid coil of the relay 5 serving as a load. Similarly, the mirror MOSTr17
Is also in the off state, the MO constituting the current source circuit 19 is
From the source terminal of the STr 21 to the input a of the AND gate 25
To the "H" level. At this time, AND gate 2
Since the "L" level is input to the input b of No. 5,
The output c of the ND gate 25 becomes "L" level.

On the other hand, as shown in FIG. 2B, when the drive input signal input to the load diagnostic circuit 3 is at "H" level, the switch MOSTr1 is input via the input buffer 11.
The “H” level is input to the gate terminal of No. 3, and the switch MOSTr13 is turned on.

As a result, the drain terminal and the gate terminal of the power MOS Tr 15 are short-circuited, and
r15 is turned on. When the power MOS Tr15 is turned on, the drain voltage of the power MOS Tr15 decreases.
Is balanced by a voltage that can maintain the ON state of the power supply. On the other hand, when the switch MOSTr13 is on, a current mirror circuit is formed between the power MOSTr15 and the mirror MOSTr17. Accordingly, a current having a mirror ratio times the current flowing through the power MOS Tr 15 flows through the mirror MOS Tr 17. Then, the current flowing through the mirror MOS Tr 17 causes the AND gate 25 to operate.
Is input at the "L" level. Since an “H” level is input to the input b of the AND gate 25,
The output c of the AND gate 25 becomes "L" level.

As described above, the load diagnosis circuit 3 outputs the "L" level from the AND gate 25 when the load is in the normal state regardless of the driving / non-driving state, and the CPU 1 may determine that the load is in the normal state. Is detected.

Next, the operation when the load connected to the load diagnostic circuit is disconnected will be described. In addition,
As the disconnection state of the load, disconnection of a solenoid coil provided in the relay 5 or disconnection of wiring connecting the relay 5 and the load diagnosis circuit 3 is assumed.

As shown in FIG. 2D, when the drive input signal output from the CPU 1 is at the "L" level, the load diagnosis circuit 3 operates in the same manner as in the normal state. c becomes the “L” level.

On the other hand, as shown in FIG. 2C, when the drive input signal input to the load diagnosis circuit 3 is at "H" level, the switch MOSTr1 is input via the input buffer 11.
The “H” level is input to the gate terminal of No. 3, and the switch MOSTr13 is turned on. However, since the load is disconnected, the drain terminals of the power MOSTr15 and the switch MOSTr13 are in an open state and no voltage is applied.

Accordingly, the gate potential of the power MOS Tr15 is fixed at substantially the GND level by the pull-down resistor R1, and the power MOS Tr15 remains off. That is, in this circuit configuration, when no voltage is applied to the drain terminal of the power MOS Tr15, the power M
OSTr15 is turned off. Therefore, for example, FIG.
As shown in (c), even if the load is disconnected during the driving of the load, the power MOSTr is immediately turned off.
Similarly, the mirror MOS Tr 17 is turned off when the load is disconnected. As a result, the “H” level is input to the input “a” of the AND gate 25 by the current source circuit 19 and the “H” level is also input to the input “b”.
5 outputs "H" level.

As described above, the load diagnosis circuit 3 sets the monitor output to "H" level as a load diagnosis result when the load is disconnected at the time of driving the load, so that the CPU 1 detects that the load is disconnected. be able to.

Next, an application range of the load diagnosis circuit 3 according to the first embodiment of the present invention will be described with reference to FIG. According to the present invention, when the power MOS Tr15 is turned on, the switch MOS Tr13 is turned on and the power M
The drain voltage of the OSTr 15 is applied to the gate terminal. Therefore, the drain voltage Vds when the power MOS Tr15 is in the ON state becomes equal to the power MOS Tr15.
Cannot be lower than the sum of the threshold voltage Vth and the saturation voltage Vds between the drain and source of the switch MOSTr13.

On the other hand, the voltage applied to the solenoid coil provided on the relay 15 serving as a load is the battery voltage V
This is a difference voltage between B and the drain voltage Vds of the power MOS Tr15. Therefore, as shown in FIG. 3, the minimum operating voltage of the load is equal to the battery voltage VB and the power MOS Tr15.
Is applicable only to a load that is lower than the difference voltage from the drain voltage Vds.

[0042]

VB− (Vth + Vds)> minimum operating voltage of load In general, the threshold voltage Vth of the power MOS Tr15
Is 1 to 2 V, the drain-source saturation voltage of the switch MOSTr 13 is about 0.3 V, and the power MO
It is considered that the drain voltage Vds of the STr15 becomes about 3V.

Therefore, considering the operation when the battery voltage is 9 V, the minimum operating voltage of the load is 6 V. For this reason,
The drive current of the solenoid coil provided on the relay 5 is 1
It can be said that the circuit is most suitable for a load of about A.

(Second Embodiment) FIG. 4 is a diagram showing a system configuration of a load diagnosis circuit according to a second embodiment of the present invention. In the second embodiment, a current-voltage conversion circuit 35, a window comparator 37, and an inverter 51 are provided instead of the current source circuit 19 of the first embodiment shown in FIG.

The current-voltage conversion circuit 35 is a MOSTr4
1, 43 and a resistor R2, and a mirror MOS
The same current value as the current flowing through Tr17 is applied to MOSTr4.
By flowing from 3 to the resistor R2, the voltage value VA proportional to the value of the current flowing to the MOSTr 43 can be converted by the resistor R2.

The window comparator 37 has a power supply VCC.
A reference voltage generating unit in which a resistor R3, a resistor R4, and a resistor R5 are connected in series, and a voltage comparing unit including a pull-up resistor R6 and comparators 45 and 47 connected in a wired AND connection. ing.

The window comparator 37 divides the power supply voltage VCC by resistance to obtain two reference voltages.

## EQU2 ## Vref1 = VCC × (R4 + R5) / (R3 + R
4 + R5) Vref2 = VCC × R5 / (R3 + R4 + R5)

The output resistance R2 of the current / voltage conversion circuit 35 is connected to the input (−) of the comparator 45, and the input (+)
Is connected to the reference voltage Vref1. On the other hand, comparator 4
7 is the output resistance R of the current-voltage conversion circuit 35 at the input (+).
2 is connected, and the reference voltage Vref2 is connected to the input (−). The output element inside each comparator is an open collector, and is wired AND-connected together with the pull-up resistor R6.
When the L level is output, the window comparator 37
Is at "L" level.

Therefore, in the window comparator 37,
The relationship between the input voltage VA and the output voltage level Vw is

## EQU3 ## When VA> Vref1, VA <Vref2: Vw = “L” level (1) When Vref2 <VA <Vref1: Vw = “H” level (2)

The inverter 51 is a logic circuit that inverts the input logic level and outputs the inverted logic level. The inverter 51 inverts the logic level output from the window comparator 37 and outputs the inverted logic level to the input a of the AND gate 25.

Next, the operation of the load diagnosis circuit 33 will be described with reference to the timing chart shown in FIG. First, the operation when the load connected to the load diagnosis circuit 33 is in a normal state will be described.

As shown in FIG. 5A, when the drive input signal output from the CPU 1 is at the "L" level, the "L" level is input to the gate terminal of the switch MOSTr13 via the input buffer 11. Switch MOSTr
13 is in the off state. Therefore, the power MOS Tr1
5 and the gate potential of the mirror MOSTr17 are fixed to a substantially GND level by the pull-down resistor R1. Accordingly, the power MOS Tr 15 is turned off, and no current flows through the relay 5 serving as a load. Similarly, mirror MO
STr17 is also in the off state. At this time, no current flows through the MOSTr 41 of the current-voltage conversion circuit 35, and the voltage generated at the resistor R2 is substantially at the GND level.

Therefore, the input voltage of the window comparator 37 is

## EQU4 ## Since VA <Vref2, the output Vw of the window comparator is "L".
Level, and the AND gate 25
The "a" level is input to the input a. At this time, AN
Since "L" level is input to the input b of the D gate 15, the output c of the AND gate 25 becomes "L" level.

On the other hand, as shown in FIG. 5B, when the drive input signal input to the load diagnosis circuit is at "H" level, the switch MOSTr13 is input via the input buffer 11.
"H" level is input to the gate terminal of the switch M.
OSTr13 is turned on. Therefore, the power MO
Since the drain terminal and the gate terminal of the STr15 are short-circuited, the power MOSTr15 is turned on. Power M
When the OSTr15 is turned on, the power MOSTr1
Although the drain voltage of the power MOS5 decreases, the balance is made with a voltage capable of holding the ON state of the power MOS Tr15 as described later. On the other hand, when the switch MOSTr13 is ON, the power MOS
A current mirror circuit is formed with the STr 15.

Accordingly, a current that is twice the mirror ratio of the current flowing through the power MOS Tr 15 flows through the mirror MOS Tr 17. As a result, a current flows through the MOSTr 41 included in the current-voltage conversion circuit 35 to GND via the mirror MOSTr 17. The same current value as the current flowing through the mirror MOSTr17 is supplied from the MOSTr43 to the resistor R
2, the voltage value VA proportional to the current value flowing through the MOSTr 43 is converted by the resistor R2.

The input voltage of the window comparator 37 is

## EQU5 ## Vref2 <VA <Vref1. Here, the voltage VA generated in the resistor R2 when the load is normal is equal to or higher than the reference voltage Vref2, and
It is assumed that the resistance values of R3, R4, and R5 used in the reference voltage generator of the window comparator 37 are set to be equal to or less than ref1.

As a result, the output voltage Vw from the window comparator 37 becomes "H" level. Therefore, the input “a” of the AND gate 25 from the inverter 51 is “L”.
The level is entered. On the other hand, the input b of the AND gate 25
Of the AND gate 25 is at the "L" level.

As described above, the load diagnosis circuit 3 sets the monitor output to the "L" level as a load diagnosis result regardless of drive / non-drive when the load is normal, so that the CPU 1 detects that the load is normal. can do.

Next, the operation when the load connected to the load diagnostic circuit is disconnected will be described. In addition,
As the disconnection state of the load, a disconnection of a solenoid coil provided in the relay 5, a disconnection of a wiring connecting the relay 5 and the load diagnosis circuit 33, and the like are assumed.

The drive input signal output from the CPU 1 is "
In the case of L level, the same load diagnostic circuit 3 as in the normal state
3 operates, the output c of the AND gate 25 becomes “L”.
Level.

On the other hand, as shown in FIG. 5C, when the drive input signal input to the load diagnosis circuit 33 is at "H" level, the switch MOSTr13 is turned on. However, the power MOST
No voltage is applied to the drain terminal of r15. Accordingly, the gate potential of the power MOS Tr15 is fixed at substantially the GND level by the pull-down resistor R1, so that the power MOS Tr15 remains off. Therefore, even if the load is disconnected during the driving of the load, the power M
OSTr15 is turned off. Similarly, mirror MOS
Tr17 is also turned off when the load is disconnected.

When no current flows through the mirror MOSTr17, no current flows through the MOSTr41 of the current-voltage conversion circuit 35, and the voltage generated at the resistor R2 is substantially at the GND level.

Therefore, the input voltage of the window comparator 37 is

## EQU6 ## Since VA <Vref2, the output Vw of the window comparator becomes "L".
Since the level is output, the “H” level is input to the input “a” of the AND gate 25 by the inverter 51. Since the drive input signal is at "H" level, "H" level is also input to the input b of the AND gate 25, and the AND gate 25 outputs "H" level.

As described above, when the load is disconnected during driving of the load, the load diagnosis circuit 33 sets the monitor output to the "H" level as a load diagnosis result, so that the CPU 1 detects that the load is disconnected. be able to.

Next, the operation when the load connected to the load diagnosis circuit is short-circuited will be described. In addition,
As a short-circuit state of the load, for example, a short-circuit of a solenoid coil provided in the relay 5 is assumed.

The drive input signal output from the CPU 1 is "
In the case of the "L" level, the circuit operation is the same as in the normal state, so that the output of the AND gate 25 becomes the "L" level.

On the other hand, as shown in FIG. 5D, when the drive input signal input to the load diagnostic circuit 33 is at "H" level, the switch MOSTr13 is turned on.
An excessive current flows through the power MOS Tr 15 due to the short circuit of the load. Mirror MOS in proportion to this excessive current
A larger current flows in Tr17 than in normal operation. Since the same current value as the current flowing in the mirror MOSTr17 flows from the MOSTr43 to the resistor R2,
The voltage value VA proportional to the current value flowing through the STr 43 is converted by the resistor R2.

Input voltage VA of window comparator 37
Is

## EQU7 ## Since the threshold value of the window comparator 37 is set so that VA> Vref1, the output V
w becomes “L” level, and
"H" level is input to the input a of the gate 25. Since the drive input signal is at the “H” level, the “H” level is also input to the input b of the AND gate 25, and A
The ND gate 25 outputs "H" level.

As described above, when the load is short-circuited at the time of driving the load, the load diagnosis circuit 33 sets the monitor output to the "H" level as a load diagnosis result, so that the CPU 1 detects that the load is short-circuited. be able to.

[Brief description of the drawings]

FIG. 1 is a diagram showing a system configuration of a load diagnosis circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining an operation of a load diagnosis circuit 3;

FIG. 3 is a diagram for explaining an application range of a load diagnosis circuit 3;

FIG. 4 is a diagram illustrating a system configuration of a load diagnostic circuit according to a second embodiment of the present invention.

FIG. 5 is a timing chart for explaining an operation of the load diagnosis circuit 33;

FIG. 6 is a diagram showing a system configuration of a conventional load diagnosis circuit.

FIG. 7 is a timing chart for explaining the operation of a conventional load diagnosis circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 3,33 Load diagnostic circuit 5 Relay 11 Input buffer 12 Drive circuit 13 Switch MOSTr 15 Power MOSTr 17 Mirror MOSTr 19 Current source circuit 21,23,41,43 MOSTr 25 AND gate 35 Current voltage conversion circuit 37 Window comparator 45, 47 Comparator 51 Inverter

Claims (4)

[Claims] 1. According to a driving signal inputted from the outside,
A load diagnosis circuit for driving a first transistor connected to a load and diagnosing a connection state of the load, comprising: connecting the first transistor to a gate terminal;
A second transistor that connects the first transistor and the source terminal to ground, and a first transistor that, when the drain terminal and the gate terminal of the first transistor are short-circuited in response to the drive signal, A drive circuit that drives the load and includes a third transistor that forms a current mirror circuit between the first and second transistors; and a current that supplies a predetermined current to a drain terminal of the second transistor. A source circuit; and an AND circuit that inputs the drain voltage of the second transistor to one end, inputs the drive signal to the other end, and outputs a logical product of both input signals. At the time of driving the load by the driving signal,
A load diagnosis circuit for diagnosing a connection state of the load based on a drain voltage of the second transistor. 2. According to a drive signal input from the outside,
A load diagnosis circuit for driving a first transistor connected to a load and diagnosing a connection state of the load, comprising: connecting the first transistor to a gate terminal;
A second transistor that connects the first transistor and the source terminal to ground, and a first transistor that, when the drain terminal and the gate terminal of the first transistor are short-circuited in response to the drive signal, A drive circuit that drives the load and has a third transistor that forms a current mirror circuit between the first and second transistors; and a current value that is proportional to a current value flowing through a drain terminal of the second transistor. A current-voltage conversion circuit that converts the voltage into a voltage value, and a first reference voltage that is lower than the power supply voltage.
A reference voltage generation circuit for generating a second reference voltage lower than the first reference voltage; and a voltage range in which the voltage value output from the current-to-voltage conversion circuit is any of the first and second reference voltages. A voltage comparison circuit for comparing whether or not the input signal is present, and an AND circuit for inputting the comparison result output from the voltage comparison circuit to one end, inputting the drive signal to the other end, and outputting a logical AND of both input signals. Wherein the AND circuit is configured to drive the load by the drive signal,
A load diagnosis circuit for diagnosing a connection state of the load based on a comparison result output from the voltage comparison circuit. 3. The voltage comparison circuit according to claim 1, wherein the voltage value output from the current-to-voltage conversion circuit is within a voltage range between a first reference voltage and a second reference voltage. 3. The load diagnosis circuit according to claim 2, wherein a comparison result indicating that the state is normal is output. 4. The voltage comparison circuit, wherein a voltage value output from the current-voltage conversion circuit is in a voltage range higher than a first reference voltage or in a voltage range lower than a second reference voltage. 3. The load diagnostic circuit according to claim 2, wherein a comparison result indicating that the load is in a short-circuit state or a disconnection state is output.