JPH05327661A - Demodulator for spread spectrum communication - Google Patents

Abstract

PURPOSE:To demodulate an SS signal subject to offset polyphase modulation with simple and inexpensive configuration. CONSTITUTION:A pattern of an interdigital electrode equivalent to the same PN code as a modulation signal is formed in a SAW matched filter 21 receiving an SS signal. A correlation peak output from the matched filter 21 is detected at an arithmetic operation circuit 22 through the arithmetic operation with a correlation peak output delayed from a delay circuit 23 by one period T. An identification recovery circuit 24 uses a timing pulse from a timing pulse generating circuit 25 to identify and recover an output from the arithmetic operation circuit 22. For example, a correlation peak is obtained from the SS signal subject to offset four phase modulation while being deviated by a half period of the PN code corresponding to each phase, then a digital information signal is simply demodulated without complicated signal processing reverse to the modulation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an offset multiphase phase modulation of four or more phases generated by modulating a predetermined PN code as a spread code with an information signal and further modulating a carrier wave with the modulated signal. The present invention relates to a demodulator for spread spectrum communication, which receives the spread spectrum signal as an input signal and demodulates the information signal based on the input signal.

[0002]

2. Description of the Related Art In recent years, a spread spectrum (hereinafter referred to as SS) communication method that is resistant to noise and excellent in confidentiality has started to be noticed, and the transmission / reception device thereof has been developed accordingly.

Generally, in the SS communication system, an SS signal which is a transmission signal is obtained by first-modulating a predetermined code sequence having a predetermined high bit rate with an information signal, and thereafter,
The carrier is secondarily modulated with the modulated signal to generate a spread spectrum signal in a wide frequency band.

In this case, the above code sequence includes, for example,
Pseudo Random Noise (hereinafter abbreviated as PN) code sequence or Gold code sequence, and the like, and SS modulation include direct modulation (Direct Sequense, hereinafter abbreviated as DS) or frequency hopping (Frequency Hopp).
ing, FH method) and the like.

In such an SS communication system, for example, when the SS modulation is performed by the DS system using the PN code sequence, the demodulation device for demodulating the SS signal in the receiver performs the SS modulation in the transmitter. PN used at the time
Using the same PN code as the code, the received SS signal is
It is configured so as to be extracted as an information bit signal when it matches the N code pattern.

Since the PN code is composed of a large number of chips (called chips to distinguish it from bits of information), the correlation between different PN codes becomes very small, and therefore the received signal is modulated. By multiplying the same PN code as that used at the time, it is possible to extract only the components of the correlated transmission signal.

The SS signal thus SS-modulated by the predetermined code has a frequency band that is considerably wider than the frequency band in the normal communication system, and therefore interference in a general narrow frequency range is caused. In addition to being strong against a noise signal of interference, the power spectrum density is low and the signal concealment is excellent, so that it is difficult to be intercepted.

In addition, S using a predetermined code such as a PN code
Since it is a system that performs S modulation and SS demodulation, the concept of frequency allocation to avoid interference unlike the normal communication system is eliminated, and the problem of insufficient frequency allocation due to an increase in communication stations is solved. It has the advantage that it is used for military communication, satellite communication, etc. by utilizing such characteristics.

Recently, in such spread spectrum communication as well, it is desired to improve the data transmission rate due to the increase in communication demand. However, increasing the chip rate as the amount of chip transmission per unit time,
Alternatively, shortening the PN code length has been difficult to realize because of the following problems.

That is, when the chip rate is high, SS
Since the occupied bandwidth of the signal becomes wide, it cannot be applied in wireless communication where the occupied bandwidth is severely limited,
Further, if the PN code length is shortened, the performance of the code is deteriorated and the data transmission accuracy is deteriorated.

Therefore, in order to increase the amount of data transmission,
The two-phase phase modulation method (BPSK (Binary-pha)
se-shift keying)) to the SS signal generated by multi-phase modulation, for example, 4-phase modulation (QPSK)
S generated by (Quadriphase-shift keying) method
It has been considered to increase the amount of information data transmitted by transmitting and receiving using the S signal.

In this case, for example, an SS signal according to the offset quadrature phase modulation method (OQPSK (Offset QPSK) method) is generally generated by the configuration shown by functional blocks in FIG.

That is, in FIG. 4, when the digital information signal D to be transmitted is input, the distribution circuit 1 inputs the digital information signal d1 of odd-numbered bit data and the digital information signal d2 of even-numbered bit data. As
The digital information signal d1 is input to the first spread spectrum modulation circuit 2, and the digital information signal d2 is input to the second spread spectrum modulation circuit 4 via the delay circuit 3.

The PN code generation circuit 5 inputs a predetermined PN code for spread spectrum to the first spread spectrum modulation circuit 2 and also to the second spread spectrum modulation circuit 4 via the delay circuit 6. .. The PN code has a period corresponding to a predetermined number of chips as one period T, and the delay circuits 3 and 6 use the period T as a reference for a half period (T / T).
The signal delayed by 2) is output.

The first and second spread spectrum modulation circuits 2 and 4 respectively apply the PN code to the digital information signal d.
The signals are output as SS modulation signals p1 and p2 by being modulated by 1 and d2, and are input to the information modulation circuits 7 and 8, respectively.

The carrier wave generating circuit 9 outputs a carrier wave having a predetermined frequency. The carrier wave generating circuit 9 inputs the output carrier wave into the information modulating circuit 7 and, through the phase shift circuit 10, the information modulating circuit 8 as well.
To enter. In this case, the phase shift circuit 10 shifts the phase of the carrier wave by π / 2 and outputs it.

The information modulation circuits 7 and 8 respectively modulate the carrier wave with the SS modulation signals p1 and p2 to form SS signals S1 and S2, which are input to the synthesis circuit 11. The synthesizing circuit 11 synthesizes the input SS signals S1 and S2 and outputs it as a four-phase phase-modulated SS signal A.

Next, the relationship between the SS signals S1 and S2 and the digital information signal D will be described. That is, the digital information signal D is the logic signal "1" as shown in FIG.
Or, it is a binary digital signal of "0".
For example, the digital information signal D is "1101110010".
Then, in the distribution circuit 1, the digital information signal D is distributed to odd-numbered data and even-numbered data and sequentially output as digital information signals d1 and d2.

As a result, the digital information signal d1 becomes "1".
0101 ”and the digital information signal d2 becomes“ 1110 ”.
"0", and at this time, 1-bit digital information is output so as to correspond to the time of one cycle T. Further, the digital information signal d2 is transmitted by the delay circuit 3 to a half cycle T.
The offset signal delayed by / 2 is given to the arithmetic circuit 4.

In the arithmetic circuits 2 and 4, a PN code of a predetermined number of chips is two-phase modulated with 1-bit information of each of the digital information signals d1 and d2. Subsequently, the carrier wave is modulated with the two-phase modulated signal to form SS signals S1 and S2, each of which has a phase of π / 2 with respect to the carrier wave.
Only the phase is shifted, and the signal is synthesized as the SS signal A.

In the case of receiving the SS signal A which is thus quadrature-phase-modulated in this way, conventionally, for example, a demodulating device shown by a functional block in FIG. 6 has been considered.

That is, the first and second phase detection circuits 12
Reference numerals 13 and 13 detect the input SS signal A separately from the SS signals S1 and S2, and perform differential detection. The delay circuit 14 receives the SS signal A,
The signal delayed by one cycle T is given to the first phase detection circuit 12 and also given to the second phase detection circuit 13 via the phase shift circuit 15.

In the phase detection circuits 12 and 13,
By delay-detecting the SS signal A, a signal in which the PN code is modulated with the digital information signal D is output. The outputs of the phase detection circuits 12 and 13 are respectively the first
And to the second identification and reproduction circuits 16 and 17.

The first discriminating / reproducing circuit 16 discriminates and reproduces the digital information d1 by the timing pulse generated from the timing pulse generating circuit 18 based on the SS signal A, and outputs it. The second identification reproduction circuit 17 receives the timing pulse delayed by the half cycle T / 2 from the timing pulse generation circuit 18 via the delay circuit 19, performs identification reproduction of the digital information d2, and outputs it.

The synthesizing circuit 20 synthesizes the output signals from the first and second discriminating and reproducing circuits 16 and 17 and demodulates them into a digital information signal D for output.

Therefore, in such a spread spectrum signal demodulating device, the digital information signal D is demodulated by performing a process which is substantially the reverse of the modulation process performed in the modulating device.

[0027]

However, with the structure as described above, it is possible to double the transmission amount of the digital information signal D, but when actually constructing such a demodulating device, Since a method using an IC (integrated circuit) or the like is generally used, a large-scale circuit for executing correlation processing for demodulating an SS signal is required, and
Since the processing speed of the IC is insufficient, there is a problem that the entire configuration becomes considerably complicated and large, and the cost becomes high.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a demodulator for spread spectrum communication capable of increasing the transmission amount of a digital information signal with a simple and inexpensive structure. ..

[0029]

According to the present invention, a predetermined PN code (pseudo noise code) as a spread code is modulated by an information signal, and a carrier wave is further modulated by the modulated signal. A demodulator for spread spectrum communication that uses an offset multi-phase phase-modulated spread spectrum signal of n times (n is an integer of 2 or more) phases as an input signal and demodulates the information signal based on this input signal When the spread spectrum signal is input, the spread spectrum signal and the PN code are composed of a surface acoustic wave element having an interdigital electrode pattern in which a reference signal for one period of the PN code is written. A matched filter that outputs a correlation peak each time the cycle of P and the output of the correlation peak from this matched filter
A delay circuit composed of a surface acoustic wave element for delaying by one cycle of N code, an arithmetic circuit for calculating the product of the output of the correlation peak from the matched filter and the output of the delay circuit, and the output of this arithmetic circuit A timing pulse generating circuit that generates a timing pulse corresponding to the correlation peak based on the above, and a positive / negative determination is sequentially made in accordance with the output from the arithmetic circuit to the timing pulse from the timing pulse generating circuit to reproduce the information signal It is characterized in that it is provided with an identification reproduction circuit.

[0030]

According to the demodulator for spread spectrum communication of the present invention, since the reference signal for one period of the PN code when the spread spectrum signal is generated is written in the interdigital electrode of the matched filter, it is input. A correlation peak is output for each cycle of the spread spectrum signal subjected to offset multi-phase phase modulation. At this time, since the spread spectrum signal is offset in multiple phases, the number of correlation peaks corresponding to the number of phases is sequentially output while the signal for one cycle is input.

These correlation peak outputs are detected by calculating the product of the delayed correlation peak outputs in the arithmetic circuit, and given to the discrimination and reproduction circuit. At this time,
Since the spread spectrum signal that has been modulated in the multi-phase is offset, the correlation peaks are sequentially output in the order of digital information. In the discrimination reproduction circuit, the peak output given in the combined state is demodulated into the original digital information signal by discrimination reproduction by the timing pulse at that time.

As a result, the multi-phase phase-modulated spread spectrum signal can be automatically demodulated into a digital information signal without performing complicated processing such as delay processing with a simple circuit configuration, so that it is inexpensive. And it can be miniaturized.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

First, the SS signal A as an input signal to the demodulation device in this embodiment is an S signal using the direct spread method.
The S signal has the main specifications as shown in Table 1. Further, here, an offset quadrature phase modulation method (OQPSK method) is adopted as the modulation method.

[0035]

[Table 1] In addition, such an OQPSK SS signal A is shown in FIG.
It is generated by the modulator having the general structure as shown in FIG. 2 and outputs the SS signal A for the digital information signal D (see FIG. 5) to be transmitted. Incidentally, FIG.
Since the description of the modulator shown in 1 has been given in the section of the conventional example, it is omitted here.

Although the unit of the digital information signal D is generally called a bit, a PN code as a spread code is often called a chip, and therefore, it is called a chip also here. ..

Next, the demodulation device according to the present invention is shown in FIG.
Or, it demonstrates with reference to FIG.

In FIG. 1 showing the overall block configuration,
The SAW matched filter 21 is a surface acoustic wave element (SA
W-element), in which a cross finger electrode pattern corresponding to the same PN code as that at the time of modulation is written, and offset 4-phase modulation (OQPS
K) SS signal A is input.

The output terminal of the SAW matched filter 21 is connected to the input terminal of the arithmetic circuit 22 and the input terminal of the delay circuit 23. Delay circuit 23
Has its output terminal connected to the arithmetic circuit 22 and delays the input signal by one cycle T of the PN code and outputs the delayed signal.

The arithmetic circuit 22 detects by calculating the product of the delayed signal given from the delay circuit 23 and the signal inputted from the SAW matched filter 21, and the output terminal thereof is the identification reproduction circuit 24 and It is connected to each input terminal of the timing pulse generation circuit 25.

The timing pulse generating circuit 25 generates a timing pulse corresponding to the cycle T in accordance with the signal input from the arithmetic circuit 22, and its output terminal is connected to the discrimination reproducing circuit 24. The identification reproduction circuit 24 is
Identification is performed according to the data based on the signal supplied from the arithmetic circuit 22, and the digital information signal D is reproduced based on the timing pulse supplied from the timing pulse generation circuit 25.

Referring to FIG. 2 showing the appearance of the SAW matched filter 21, interdigital electrodes 27 and 28 having a comb shape are formed on the upper surface of the piezoelectric substrate 26 made of, for example, a single crystal such as quartz as an input terminal and an output terminal, respectively. Has been done. In this case, the interdigital electrode 28 as an output terminal
Are arranged and formed so as to match the bit pattern for one cycle of the PN code used for modulation.

By the way, in general, the performance of the demodulator for spread spectrum communication is represented by the ability to improve the SN ratio, that is, the processing gain. Therefore, in this case, the processing gain of the demodulator is determined by the compression gain of the SAW matched filter 21. It will be. Therefore, if the compression gain is increased, the performance is improved, but the cost is also increased accordingly. Therefore, in actuality, the compression gain is designed to be increased while considering the cost.

That is, for example, in the SAW matched filter 21, the piezoelectric substrate 26 made of crystal as described above is used in order to satisfy the high accuracy requirement. The code length is 8 μs considering the cost of materials and manufacturing yield.
ec, and the SAW matched filter 2 at this time
The length of 1 is 30 mm, for example.

The higher the carrier frequency, the more advantageous it is in terms of insertion loss, but it is preferable to set it to 100 to 150 MHz from the viewpoint of manufacturing. In this case, as shown in Table 1, It is set to 144 MHz. The chip rate is preferably about 10% of the carrier frequency, and therefore 16M chips / sec. As a result, the code length becomes 127 chips, the compression gain becomes 21 dB, and the data transmission rate becomes 126 kbit / sec. In this case, the PN code uses a general M sequence (tap [7, 1]).

Next, the operation of this embodiment will be described.

First, when the SS signal A (see FIG. 3 (a)) modulated as shown in Table 1 is input to the SAW matched filter 21, the peak of the correlation is obtained every one cycle T of the PN code. (See FIG. 3B) is output. in this case,
The information modulation is performed by inverting the polarity of the PN code for one cycle T for one bit of the digital information signal D (cycle t = T / 2). It can be considered that the phase of the minute carrier is 0 phase or π phase. Since the signals are modulated in four phases in the offset state, the signals for one period of the PN code are overlapped with being delayed by the half period T / 2.

In the arithmetic circuit 22, the product of the correlation peak in the next cycle is calculated based on the previous correlation peak delayed by one cycle T provided from the delay circuit 23, and the differential detection is performed to obtain a positive or negative value. A negative peak can be obtained. At this time, as described above, the digital information signal D
Is synthesized as the SS signal A in a state in which it is divided into the digital information signals d1 and d2 and shifted by a half period (T / 2) of the period T of the PN code, so these peaks are the same as the original digital information. According to the value of the signal D, the cycle t (= T /
It is sequentially reproduced in 2).

The output after the delay detection is input to the discrimination / reproduction circuit 24. In the discrimination / reproduction circuit 24, a timing pulse is given from the timing pulse generation circuit 25 every period T / 2. Therefore, the peak output from the arithmetic circuit 22 can be identified and reproduced according to this, so that the original digital information signal D can be demodulated.

The inventor has confirmed that the SS communication demodulator according to the above-described embodiment has excellent characteristics in the following points.

That is, it was confirmed that a value close to the theoretical value was obtained as the measurement result of BER (Bit Error Rate) in the presence of thermal noise. In addition, the characteristics of interference waves against interference signals such as CW signals and other SS signals are investigated, and DU ratios (required signal to unnecessary signal ratio, Desired-to-Undes
It was confirmed that ired Signal Ratio) was error-free up to -3 dB. Furthermore, it was confirmed that code division multiplexing is possible.

According to this embodiment, the SAW matched filter 21 is used to detect the correlation peak of the SS signal A that has been subjected to the offset four-phase phase modulation, and the arithmetic circuit 22 and the discrimination / reproduction circuit 24 digitally detect the correlation peak. Information signal D
Since the reproduction is performed, it is not necessary to perform the demodulation by performing the reverse procedure of performing the modulation processing in the modulator, and therefore, the SS signal A that has been subjected to the offset four-phase phase modulation with a simple and inexpensive structure is used. Can be demodulated.

In the above embodiment, the case of demodulating the 4-phase phase-modulated SS signal A has been described.
The present invention is not limited to this, and can be applied to the case of demodulating an SS signal that is n times as many as 2 (n is an integer of 2 or more) phases or more and is subjected to offset polyphase modulation.

[0054]

As described above, according to the demodulator for spread spectrum communication of the present invention, an offset multiphase phase-modulated spectrum that is n times as many as 2 (n is an integer of 2 or more) phases to be input. With respect to the spread signal, the correlation peak is detected by the matched filter, and the digital information is demodulated through the arithmetic circuit and the identification / reproduction circuit. Therefore, there is an excellent effect that demodulation can be performed with a simple and inexpensive structure.

[Brief description of drawings]

FIG. 1 is a functional block configuration diagram showing an embodiment of the present invention.

FIG. 2 is an external perspective view of a SAW matched filter.

FIG. 3 is a waveform diagram showing an SS signal and its correlation peak output.

FIG. 4 is a functional block configuration diagram of a general modulator.

FIG. 5 is an explanatory diagram of a digital information signal.

FIG. 6 is a view corresponding to FIG. 1 showing a conventional example.

[Explanation of symbols]

1 is a distribution circuit, 2 and 4 are spread spectrum modulation circuits, 5 is a PN code generation circuit, 7 and 8 are information modulation circuits, 9 is a carrier wave generation circuit, 11 is a synthesis circuit, 21 is a SAW matched filter (matched filter), 22 is an arithmetic circuit, 23 is a delay circuit, 24 is an identification reproducing circuit, and 25 is a timing pulse generating circuit.

Claims (1)

[Claims] 1. N times 2 (n is 2 or more) generated by modulating a predetermined PN code (pseudo noise code) as a spread code with an information signal and further modulating a carrier wave with the modulated signal. The input signal is a spread-spectrum signal that is offset multi-phase phase modulated with more than one phase)
In the demodulation of the information signal based on the input signal, when the spread spectrum signal is input, the surface spread wave element is composed of an interdigital electrode pattern in which a reference signal for one period of the PN code is written. A matched filter that outputs a correlation peak each time the spread spectrum signal and the PN code match in cycle, and a surface acoustic wave element that delays the output of the correlation peak from the matched filter by one cycle of the PN code. And a calculation circuit for calculating the product of the output of the correlation peak from the matched filter and the output of the delay circuit, and a timing pulse corresponding to the correlation peak is generated based on the output of the calculation circuit. A timing pulse generating circuit, and a timing pulse generating circuit for outputting the output from the arithmetic circuit. Spread spectrum communication demodulation device characterized by performing successively positive and negative determination in accordance with the Guparusu equipped and identification reproducing circuit for reproducing the information signal.