JPH05326599A - Manufacture of resin-sealed-type semiconductor device - Google Patents

Manufacture of resin-sealed-type semiconductor device

Info

Publication number
JPH05326599A
JPH05326599A JP4327077A JP32707792A JPH05326599A JP H05326599 A JPH05326599 A JP H05326599A JP 4327077 A JP4327077 A JP 4327077A JP 32707792 A JP32707792 A JP 32707792A JP H05326599 A JPH05326599 A JP H05326599A
Authority
JP
Japan
Prior art keywords
resin
surface side
die
die pad
main surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4327077A
Other languages
Japanese (ja)
Inventor
Kenji Motai
建志 甕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP4327077A priority Critical patent/JPH05326599A/en
Priority to US08/035,781 priority patent/US5368805A/en
Priority to EP93104773A priority patent/EP0562556A1/en
Publication of JPH05326599A publication Critical patent/JPH05326599A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge

Landscapes

  • Moulds For Moulding Plastics Or The Like (AREA)
  • Injection Moulding Of Plastics Or The Like (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE:To provide the manufacture of molding a resin package by preventing the occurrence of defects such as a weld mark, a pin hole, etc., in the thin sealing resin layer on the rear side of a lead frame, aiming at a TO external shape of resin-sealed-type semiconductor device. CONSTITUTION:Molding is performed, setting the temperature of the surface of the bottom force 7 arranged on the main surface side of the lead frame from +5 to +15 deg.C higher than the temperature (170 deg.C) of the surface of the upper mold arranged on the rear side, when inserting an assembly, where a semiconductor chip 2 is mounted on the die pad main surface side of a lead frame 1 and further a bonding wire is applied between the semiconductor chip 1 and a lead 1b, into a transfer mold, and sealing it with resin. Hereby, the viscosity of the injected resin flowing in on the rear side lowers, and the fluidity increases, and the a thin resin layer can be formed surely without shortage of charge on the rear side where the cross section of the passage inside the cavity is narrow.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、TO220,TO3P
などのパッケージ外形を対象とした樹脂封止形半導体装
置の製造方法に関する。
The present invention relates to TO220, TO3P
The present invention relates to a method for manufacturing a resin-encapsulated semiconductor device, which is intended for package outer shapes such as.

【0002】[0002]

【従来の技術】まず、本発明の実施対象となる樹脂封止
形半導体装置の構造を図2に、その回路組立体を図3に
示す。図において、1は半導体装置の組立に用いるリー
ドフレーム、2は放熱板を兼ねたリードフレーム1のダ
イパッド1aの主面側にマウントした半導体チップ、3
は半導体チップ2とリードフレーム1のリード1bとの
間を接続したボンディングワイヤ、4は前記の回路組立
体を樹脂封止してモールド成形された樹脂パッケージで
ある。かかる半導体装置は、図2のようにヒートシンク
5に装着して使用されることから、ダイパッド1aとヒ
ートシンク5との間の伝熱抵抗をできるだけ低く抑える
ために、ダイパッド1aの裏面側を覆っている樹脂パッ
ケージ4の樹脂層厚みdを主面側の樹脂層厚みより極端
に薄く、例えば0.5mm程度にして形成するようにしてい
る。
2. Description of the Related Art First, FIG. 2 shows the structure of a resin-encapsulated semiconductor device to which the present invention is applied, and FIG. 3 shows its circuit assembly. In the figure, 1 is a lead frame used for assembling a semiconductor device, 2 is a semiconductor chip mounted on the main surface side of the die pad 1a of the lead frame 1 also serving as a heat sink, 3
Is a bonding wire connecting between the semiconductor chip 2 and the lead 1b of the lead frame 1, and 4 is a resin package molded by resin-sealing the circuit assembly. Since such a semiconductor device is used by being mounted on the heat sink 5 as shown in FIG. 2, the back surface side of the die pad 1a is covered in order to suppress the heat transfer resistance between the die pad 1a and the heat sink 5 as low as possible. The resin layer 4 is formed so that the resin layer thickness d of the resin package 4 is extremely thinner than the resin layer thickness on the main surface side, for example, about 0.5 mm.

【0003】また、前記樹脂パッケージ4のモールド法
には、一般にトランスファ成形法が採用されている。こ
のトランスファ成形法は、図3に示したリードフレーム
の組立体をあらかじめ所定温度に加熱しておいた成形金
型の上型と下金型との間に挟んで金型のキャビティにイ
ンサートし、金型のゲートを通じて注型樹脂を加圧注入
して成形する。なお、従来では注型樹脂にエポキシ系樹
脂を採用した場合には、成形金型の表面温度を170℃
に固定して成形を行っている。
Further, a transfer molding method is generally adopted as a molding method for the resin package 4. In this transfer molding method, the lead frame assembly shown in FIG. 3 is sandwiched between an upper die and a lower die of a molding die that has been heated to a predetermined temperature, and the lead frame assembly is inserted into a cavity of the die, Molding is performed by injecting a casting resin under pressure through the gate of the mold. In the past, when epoxy resin was used as the casting resin, the surface temperature of the molding die was 170 ° C.
It is fixed to and molded.

【0004】[0004]

【発明が解決しようとする課題】ところで、トランスフ
ァ成形用金型を用いて図2のような樹脂パッケージ4を
成形する場合には、ダイパッド1aの裏面側ではダイパ
ッドと金型のキャビティ壁面との間の断面が主面側に比
べて極端に狭いため、同じ成形圧力の下では主面側に比
べて樹脂の流れが悪くなり、金型のゲートから注入した
注型樹脂が流路断面の大きな主面側から速く充填される
ようになる。この結果、ダイパッドの裏面側に樹脂の充
填不足が生じ、この部分にピンホール,ウェルドマーク
などの成形の欠陥が生じる 図4はこの様子を示したものであり、ダイパッド1aの
主面側に配した上型6と裏面側に配した下型7に対し、
左側端のゲート8を通じて注型樹脂を注入すると、注型
樹脂は流路断面の大きな主面側から先に充填されて行
き、流路断面の狭い裏面側での樹脂の充填進行が遅れる
ようになる。このために、ゲート8から直接裏面側に流
入する注型樹脂の流れと、主面側を流動して右側の終端
より裏面側に回り込んで来た注型樹脂の流れとの融合が
旨く行われず、その接合部分にウェルドマーク,ピンホ
ールなどの欠陥が発生する。しかも肉薄な裏面側に前記
のようなウェルドマーク,ピンホールなどの欠陥が発生
すると樹脂パッケージの強度が低下して亀裂,割れなど
を引き起こす原因となる。
By the way, when molding the resin package 4 as shown in FIG. 2 by using the transfer molding die, on the back surface side of the die pad 1a, the space between the die pad and the cavity wall surface of the die is formed. Since the cross section of the resin is extremely narrow compared to the main surface side, the resin flow becomes worse under the same molding pressure than the main surface side, and the casting resin injected from the mold gate has a large flow path cross section. It will be filled faster from the surface side. As a result, the resin is insufficiently filled on the back surface side of the die pad, and molding defects such as pinholes and weld marks occur at this portion. FIG. 4 shows this state, and it is arranged on the main surface side of the die pad 1a. For the upper mold 6 and the lower mold 7 arranged on the back side,
When the casting resin is injected through the gate 8 at the left end, the casting resin is filled from the side of the main surface having the larger flow passage cross section first, and the progress of the filling of the resin on the back side of the narrow passage cross section is delayed. Become. For this reason, the flow of the casting resin flowing directly from the gate 8 to the back surface side and the flow of the casting resin flowing along the main surface side and wrapping around from the right end to the back surface side are performed well. As a result, defects such as weld marks and pinholes occur at the joint. In addition, if defects such as the above-mentioned weld marks and pinholes occur on the thin back surface side, the strength of the resin package is lowered, causing cracks and cracks.

【0005】そこで、従来では金型のキャビティ内でダ
イパッドの主面側への樹脂の流れをセーブするオリフィ
スなどの制御部材を金型,あるいはリードフレーム側に
設けるなどして、ダイパッドの裏面側にも注型樹脂が十
分に流れ込むようにした方法が特開平2−29003
2,特開平3−94432号公報などで公知である。し
かしながら、これらの方法は、金型が複雑になるなどコ
ストアップとなるほか、適用するパッケージ外形も制約
されるなどの問題が残る。
Therefore, conventionally, a control member such as an orifice for saving the flow of the resin to the main surface side of the die pad in the cavity of the die is provided on the die or the lead frame side so that it is provided on the back side of the die pad. A method in which the casting resin is sufficiently flowed in is also disclosed in JP-A-2-29003.
2, known from Japanese Patent Laid-Open No. 3-94432. However, these methods have a problem that the cost is increased due to a complicated die and the package outer shape to be applied is restricted.

【0006】本発明は上記の点にかんがみなされたもの
であり、その目的は頭記したTO外形の樹脂封止型半導
体装置を対象に、金型に樹脂の流れを変えるような特別
な制御部材を組み込むことなしに、リードフレームの裏
面側に肉薄な封止樹脂層を確実に成形できるようにした
樹脂封止形半導体装置の製造方法を提供することにあ
る。
The present invention has been made in view of the above points, and its purpose is to provide a special control member for changing the flow of resin into a mold for the above-mentioned TO-shaped resin-sealed semiconductor device. It is an object of the present invention to provide a method of manufacturing a resin-encapsulated semiconductor device, which can surely form a thin encapsulating resin layer on the back surface side of a lead frame without incorporating the above.

【0007】[0007]

【課題を解決するための手段】上記目的は、本発明によ
り、ダイパッドの裏面側に配した成形金型の表面温度
を、ダイパッドの主面側に配した成形金型の表面温度よ
りも高く設定して形成することにより達成される。ま
た、前記方法においては、ダイパッドの裏面側に配した
成形金型の表面温度を、ダイパッドの主面側に配した成
形金型の表面温度より+5〜+10℃高く設定するのが
よく、具体的数値として主面側の成形金型表面温度を1
70℃に固定し、裏面側の成形金型表面温度を175〜
185℃に設定するのが好ましい。
According to the present invention, the surface temperature of a molding die arranged on the back side of a die pad is set higher than the surface temperature of a molding die arranged on the main surface side of the die pad. It is achieved by forming. Further, in the above method, the surface temperature of the molding die arranged on the back surface side of the die pad is preferably set to +5 to + 10 ° C. higher than the surface temperature of the molding die arranged on the main surface side of the die pad. As a numerical value, the surface temperature of the main mold is 1
Fix the surface temperature of the molding die on the back side to 175-175
It is preferably set to 185 ° C.

【0008】[0008]

【作用】上記の方法において、トランスファモールド法
により成形金型のゲートを通じてキャビティに注入され
た注型樹脂(エポキシ系樹脂)は、金型にインサートさ
れたリードフレームを境にその主面側と裏面側の二手に
別れて流れる。ここで、ダイパッドの裏面側に配した成
形金型(下型)の表面温度を、主面側に配した成形金型
(上型)の表面温度よりも+5〜+15℃の範囲で高く
設定することにより、ダイパッドの裏面側に流れ込んだ
注型樹脂は主面側を流れる樹脂よりも粘度が低まって流
動性が増す。これにより、注型樹脂は主面側よりも先に
裏面側から充填されて行き、肉薄な裏面側にウェルドマ
ーク,ピンホールなどの欠陥が発生しなくなる。
In the above method, the casting resin (epoxy resin) injected into the cavity through the gate of the molding die by the transfer molding method has the main surface side and the back surface with the lead frame inserted in the die as a boundary. It flows in two hands on the side. Here, the surface temperature of the molding die (lower die) arranged on the back surface side of the die pad is set higher than the surface temperature of the molding die (upper die) arranged on the main surface side within a range of +5 to + 15 ° C. As a result, the casting resin that has flowed into the back surface side of the die pad has a lower viscosity than the resin that flows into the main surface side, increasing the fluidity. As a result, the casting resin is filled from the back surface side before the main surface side, and defects such as weld marks and pinholes do not occur on the thin back surface side.

【0009】なお、発明者等が行った実験によれば、前
記した成形金型表面温度差を+15℃以上,つまり上型
の表面温度を170℃として下型の表面温度を185℃
よりも高くすると、ゲートを通じて裏面側に流入した注
型樹脂は高温の下型(表面温度が185℃よりも高い)
に触れために、逆に樹脂の硬化が急速に進んで粘度が高
まる現象が現れ、結果として従来の方法と同様に肉薄な
裏面側にウェルドマーク,ピンホールなどの欠陥が発生
することが確認されている。
According to an experiment conducted by the inventors, the surface temperature difference of the molding die is not less than + 15 ° C., that is, the surface temperature of the upper mold is 170 ° C. and the surface temperature of the lower mold is 185 ° C.
When the temperature is higher than the above, the casting resin that has flowed into the back side through the gate is a high temperature lower mold (the surface temperature is higher than 185 ° C).
On the contrary, it was confirmed that the resin hardening rapidly progresses and the viscosity increases, resulting in defects such as weld marks and pinholes on the thin back surface as in the conventional method. ing.

【0010】[0010]

【実施例】図1は本発明の実施例によるトランスファモ
ールド法による半導体装置の樹脂封止工程を表す図であ
り、図において、6はダイパッド1aの主面側に配した
トランスファ形成用金型の上型、7は裏面側に配した下
型、8はゲート、9は金型のキャビティであり、さらに
10は上型6の加熱ヒータ、11は下型7の加熱ヒータ
を示す。
FIG. 1 is a diagram showing a resin encapsulation process of a semiconductor device by a transfer molding method according to an embodiment of the present invention. In FIG. 1, reference numeral 6 denotes a transfer forming die arranged on the main surface side of a die pad 1a. An upper die, 7 is a lower die disposed on the back surface side, 8 is a gate, 9 is a mold cavity, 10 is a heater for the upper die 6, and 11 is a heater for the lower die 7.

【0011】ここで、前記の形成金型に対して図3に示
したリードフレームの組立体は、半導体チップ2をマウ
ントしたダイパッド1aの主面を上に向けて金型にイン
サートされる。そして、ゲート8を通じてキャビティ9
にエポキシ系の注型樹脂(例えば、日東電工(株)の商
品名MP−4000シリーズ,信越化学工業(株)の商
品名KMC−120シリーズ等)を加圧注入することに
より、図2に示した樹脂パッケージ4が成形される。
Here, the lead frame assembly shown in FIG. 3 with respect to the forming die is inserted into the die with the main surface of the die pad 1a on which the semiconductor chip 2 is mounted facing upward. And the cavity 9 through the gate 8
As shown in FIG. 2, epoxy-based casting resin (eg, Nitto Denko's trade name MP-4000 series, Shin-Etsu Chemical Co.'s trade name KMC-120 series, etc.) is injected under pressure. The resin package 4 is molded.

【0012】ここで、ヒータ10,11の加熱温度を調
整して、あらかじめ上型6の金型温度を170℃、下型
7の表面温度を上型の表面温度よりも温度差にして+5
〜+15℃高い175〜185℃の範囲に設定して成形
を行うことにより、ゲート8よりキャビティ9内に流れ
込んだ注型樹脂は二手に別れてリードフレーム1を境に
ダイパッド1aの主面(上面)側と裏面(下面)側に進
む。この場合に、上型6と下型7の表面温度差を前記条
件に設定しておくことにより、裏面側に流れ込んだ注型
樹脂は主面側に流れる樹脂の粘度よりも低まって流動性
が増す。したがって、ダイパッド1aの主面側の肉厚部
分よりも先に裏面側の肉薄部分が隅々まで充填されるよ
うになり、この結果として肉薄な裏面側にウェルドマー
ク,ピンホールなどの発生を抑えて成形欠陥のない樹脂
パッケージが得られる。
Here, the heating temperature of the heaters 10 and 11 is adjusted so that the mold temperature of the upper mold 6 is 170 ° C. and the surface temperature of the lower mold 7 is a temperature difference of +5 from the surface temperature of the upper mold in advance.
By setting in the range of 175 to 185 ° C., which is higher than + 15 ° C., and performing molding, the casting resin that has flowed into the cavity 9 from the gate 8 is divided into two hands and the main surface (upper surface of the die pad 1 a with the lead frame 1 as a boundary is separated. ) Side and the back side (bottom surface) side. In this case, by setting the surface temperature difference between the upper mold 6 and the lower mold 7 to the above condition, the casting resin that has flowed into the back surface side becomes lower in viscosity than the resin that flows into the main surface side, and the fluidity is reduced. Will increase. Therefore, the thin portion on the back surface side is filled in every corner before the thick portion on the main surface side of the die pad 1a, and as a result, the occurrence of weld marks, pinholes, etc. on the thin back surface side is suppressed. As a result, a resin package having no molding defect can be obtained.

【0013】図5は上型6の表面温度を170℃に固定
し、下型7の表面温度を様々に変えて行った実験結果を
表すものであり、横軸は下型と上型との表面温度差を表
し、縦軸はダイパッド1aを境にその主面側,裏面側に
流れる注型樹脂の相対的な充填速さを表している。この
図から判るように、金型の表面温度差が+5℃以下の領
域Aでは二手に分かれて主面側と裏面側に流れる樹脂の
流動性が殆ど変わらず、かつ裏面側の流路断面が狭いた
めに、相対的に主面側から先に充填される。これに対し
て、金型の表面温度差を+5〜+15℃の範囲に調整し
た領域Bでは、下面側に流れ込んだ注型樹脂の粘度が低
まって流動性が高まるようになるため、注型樹脂は裏面
側から先に充填されて行く。したがって、この場合には
肉薄な裏面側にウェルドマーク,ピンホールなどの欠陥
が発生しなくなる。一方、金型の表面温度差を+15℃
より高くした領域Cになると、裏面側に流入した注型樹
脂は下型7の表面温度が高過ぎるために、逆に樹脂の硬
化が急速に進行して粘度が高くなり、この結果として前
記のA領域と同様に裏面側にウェルドマーク,ピンホー
ルなどの欠陥が発生し易くなる。
FIG. 5 shows the results of an experiment conducted by fixing the surface temperature of the upper mold 6 to 170 ° C. and changing the surface temperature of the lower mold 7 variously. The horizontal axis represents the lower mold and the upper mold. The surface temperature difference is represented, and the vertical axis represents the relative filling speed of the casting resin flowing on the main surface side and the back surface side of the die pad 1a. As can be seen from this figure, in the region A where the surface temperature difference of the mold is + 5 ° C. or less, the fluidity of the resin that flows into the main surface side and the back surface side hardly changes and the flow path cross section on the back surface side is almost the same. Since it is narrow, it is relatively filled first from the main surface side. On the other hand, in the region B where the surface temperature difference of the mold is adjusted within the range of +5 to + 15 ° C., the viscosity of the casting resin that has flowed into the lower surface side decreases and the fluidity increases, so The resin is filled from the back side first. Therefore, in this case, defects such as weld marks and pinholes do not occur on the thin back surface side. On the other hand, the surface temperature difference of the mold is + 15 ℃
In the higher region C, the surface temperature of the lower mold 7 of the casting resin that has flowed into the back surface is too high, so that the curing of the resin progresses rapidly and the viscosity becomes high. Similar to the area A, defects such as weld marks and pinholes are likely to occur on the back surface side.

【0014】[0014]

【発明の効果】以上述べたように、本発明による半導体
装置の製造方法によれば、トランスファ成形金型のキャ
ビティ内部,或いはリードフレームの組立体に樹脂流れ
の制御部材を組み込むなどの面倒な手段を講じることな
く、単に上型と下型の金型表面温度を所定の温度条件に
合わせて個別に調節することで、樹脂充填不足に起因す
るウェルドマーク,ピンホールなどの成形欠陥が樹脂層
が肉薄なリードフレームの裏面側に生じるのを確実に防
止して高品質な樹脂パッケージを成形することができ
る。
As described above, according to the method for manufacturing a semiconductor device of the present invention, a troublesome means such as incorporating a resin flow control member inside the cavity of the transfer molding die or in the lead frame assembly. By simply adjusting the mold surface temperature of the upper and lower molds individually according to the prescribed temperature conditions without taking the steps, molding defects such as weld marks and pinholes caused by insufficient resin filling will not occur in the resin layer. It is possible to surely prevent the thin lead frame from being generated on the back surface side and mold a high quality resin package.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例による半導体装置の樹脂封止工
程,および金型内における注型樹脂の流れ状態を表す図
FIG. 1 is a diagram showing a resin sealing process of a semiconductor device according to an embodiment of the present invention and a flow state of a casting resin in a mold.

【図2】本発明の実施対象となる樹脂封止形半導体装置
の構成断面図
FIG. 2 is a configuration cross-sectional view of a resin-encapsulated semiconductor device to which the present invention is applied.

【図3】図2におけるリードフレーム組立体の斜視図FIG. 3 is a perspective view of the lead frame assembly in FIG.

【図4】従来のモールド成形法による金型内の注型樹脂
の流れ状態を表す図
FIG. 4 is a diagram showing a flow state of a casting resin in a mold by a conventional molding method.

【図5】上型と下型の金型表面温度差と注型樹脂の充填
速さとの関係を表す特性図
FIG. 5 is a characteristic diagram showing the relationship between the mold surface temperature difference between the upper mold and the lower mold and the filling speed of the casting resin.

【符号の説明】[Explanation of symbols]

1 リードフレーム 1a ダイパッド 1b リード 2 半導体チップ 3 ボンディングワイヤ 4 樹脂パッケージ 6 成形金型の上型 7 成形金型の下型 8 ゲート 9 キャビティ 10 金型加熱ヒータ 11 金型加熱ヒータ 1 Lead Frame 1a Die Pad 1b Lead 2 Semiconductor Chip 3 Bonding Wire 4 Resin Package 6 Upper Mold 7 Mold Lower Mold 8 Gate 9 Cavity 10 Mold Heater 11 Mold Heater

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】リードフレームのダイパッド主面側に半導
体チップをマウントし、かつ半導体チップとリードとの
間にワイヤボンディングを施した組立体を成形金型にイ
ンサートしてトランスファモールドした樹脂封止形半導
体装置の製造方法であり、封止樹脂層の厚みをダイパッ
ドの裏面側で肉薄に成形したものにおいて、ダイパッド
の裏面側に配した成形金型の表面温度を、ダイパッドの
主面側に配した成形金型の表面温度よりも高く設定して
形成することを特徴とすることを特徴とする樹脂封止形
半導体装置の製造方法。
1. A resin-sealed type in which a semiconductor chip is mounted on a die pad main surface side of a lead frame, and an assembly in which wire bonding is performed between the semiconductor chip and the lead is inserted into a molding die and transfer molded. In the method for manufacturing a semiconductor device, in which the thickness of the sealing resin layer is thinly formed on the back surface side of the die pad, the surface temperature of the molding die arranged on the back surface side of the die pad is arranged on the main surface side of the die pad. A method of manufacturing a resin-encapsulated semiconductor device, which is characterized in that it is formed at a temperature higher than the surface temperature of a molding die.
【請求項2】請求項1記載の製造方法において、ダイパ
ッドの裏面側に配した成形金型の表面温度を、ダイパッ
ドの主面側に配した成形金型の表面温度より+5〜+1
0℃高く設定したことを特徴とする樹脂封止形半導体装
置の製造方法。
2. The manufacturing method according to claim 1, wherein the surface temperature of the molding die arranged on the back surface side of the die pad is +5 to +1 than the surface temperature of the molding die arranged on the main surface side of the die pad.
A method of manufacturing a resin-encapsulated semiconductor device, characterized in that the temperature is set to be 0 ° C. higher.
【請求項3】請求項1記載の製造方法において、ダイパ
ッドの主面側に配した成形金型の表面温度を170℃に
固定し、裏面側に配した成形金型の表面温度を175〜
185℃に設定したことを特徴とする樹脂封止形半導体
装置の製造方法。
3. The manufacturing method according to claim 1, wherein the surface temperature of the molding die arranged on the main surface side of the die pad is fixed at 170 ° C., and the surface temperature of the molding die arranged on the back surface side is 175 to 175.
A method of manufacturing a resin-encapsulated semiconductor device, which is set at 185 ° C.
JP4327077A 1992-03-24 1992-12-08 Manufacture of resin-sealed-type semiconductor device Pending JPH05326599A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP4327077A JPH05326599A (en) 1992-03-24 1992-12-08 Manufacture of resin-sealed-type semiconductor device
US08/035,781 US5368805A (en) 1992-03-24 1993-03-23 Method for producing resin sealed type semiconductor device
EP93104773A EP0562556A1 (en) 1992-03-24 1993-03-23 Method for producing resin sealed type semiconductor device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP4-65408 1992-03-24
JP6540892 1992-03-24
JP4327077A JPH05326599A (en) 1992-03-24 1992-12-08 Manufacture of resin-sealed-type semiconductor device

Publications (1)

Publication Number Publication Date
JPH05326599A true JPH05326599A (en) 1993-12-10

Family

ID=13286180

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4327077A Pending JPH05326599A (en) 1992-03-24 1992-12-08 Manufacture of resin-sealed-type semiconductor device

Country Status (1)

Country Link
JP (1) JPH05326599A (en)

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