JPH05325584A - Multistage shift register - Google Patents

Abstract

PURPOSE:To reduce the power consumption of the multistage shift register. CONSTITUTION:The multistage shift register SR which is activated on the basis of a shift clock signal SCLK to input serial input data in order and also shift the inputted serial input data, bit by bit is divided into plural areas E1-En. The shift register SR having the areas E1-En where the serial input data are shifted according to the counted value of pulses of the shift clock signal SCLK is equipped with a control circuit 6 which supplies the shift clock signal SCLK to the shift register SR in order.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multistage shift register used for driving a dot matrix type liquid crystal display or the like.

In recent years, a dot matrix type liquid crystal display has been used in word processors, portable personal computers and the like, and this liquid crystal driver is driven by using a multistage shift register. Since the number of stages of the shift register increases as the number of dots of the liquid crystal display increases, it is required to reduce the power consumption of the multi-stage shift register.

[0003]

2. Description of the Related Art A conventional display control circuit for driving a dot matrix type liquid crystal display will be described with reference to FIG. 4, in which n-bit shift registers SRn to SR0.
Are connected in series, the shift clock signal SCLK is input to each shift register SRn to SR0, and the serial input data SI is input to the first stage shift register SRn in synchronization with the shift clock signal SCLK.

The output signals Dn to D0 of the shift registers SRn to SR0 are input to the n-bit latch circuit 1, and when the load signal L is input to the n-bit latch circuit 1, the output signals of the shift registers SRn to SR0 are input. Dn ~ D
0 is latched, serial-parallel conversion is performed, and the latched data LDn to LD1 are output to the n-segment drive circuit 2.

The n-segment drive circuit 2 outputs n-bit output signals OUTn-OUT0 based on the latch data LDn-LD1 of the n-bit latch circuit 1, and n-segment liquid crystal based on the output signals OUTn-OUT0. Is driven.

The operation of such a display control circuit will be described with reference to FIG. 5. When the shift clock signal SCLK is input to the shift registers SRn to SR0, the data input to the first-stage shift register SRn as serial input data SI. D0 to Dn are sequentially shifted.

Then, the n-bit serial input data is input to the input terminal SI, and the first-stage shift register SRn
The load signal L is input to the n-bit latch circuit 1 in a state in which the data Dn is stored in and the data D0 is stored in the final-stage shift register SR0. Then, the n-bit latch circuit 1 latches the stored data Dn to D0 of each shift register SRn to SR0 and latches the latched data LDn.
~ LD0 is output to the n segment drive circuit 2.

[0008]

In the above display control circuit, n-bit serial input data is input to the input terminal SI.
To the shift registers SRn to SR0, the shift clock signal SCLK is always input to the shift registers SRn to SR0 and maintained in the ON state.

When the number of dots of the liquid crystal display increases, the number of bits of serial input data also increases, and the number of stages of the shift register increases. Therefore, there is a problem that the power consumption increases as the number of dots of the liquid crystal display increases.

An object of the present invention is to provide a multistage shift register which can reduce power consumption regardless of an increase in the number of bits.

[0011]

FIG. 1 illustrates the principle of the present invention. That is, the serial input data is activated based on the shift clock signal SCLK and the serial input data is input to the input terminal SI.
To the plurality of regions E1 to En for sequentially inputting serial input data to each other and shifting the input serial input data bit by bit, serial input data is generated based on the count of the number of pulses of the shift clock signal SCLK. A control circuit 6 for sequentially supplying the shift clock signal SCLK to the shift registers SR in the shifted areas E1 to En is provided.

Further, as shown in FIG. 2, the control circuit counts the number of pulses of the shift clock signal SCLK and outputs a plurality of output signals Q0 to Q2 in sequence based on the counted number, and the control counter 4. A shift clock signal SCL based on the output signals Q0 to Q2 of the counter 4
AND circuit 3 for sequentially outputting K to each of the areas E2 to E4
a to 3c.

[0013]

When the serial input data SI is shifted, the shift register SR in each of the areas E1 to En is sequentially activated by the shift clock signal SCLK input by the control circuit 6.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment embodying the present invention will now be described with reference to FIG.
And FIG. 3 will be described. The same components as those of the conventional example will be described with the same reference numerals.

FIG. 2 shows a 320-bit shift register SR.
319 to SR0, each shift register SR
319 to SR0 are equally divided into four areas E1 to E4 by 80 bits.

The shift clock signal SCLK is directly input to the shift registers SR319 to SR240 forming the first area E1, and the first-stage shift register SR31 is provided.
Serial input data is input to the input terminal SI of 9.
The shift clock signal SCLK is also input to the AND circuit 3a and the control counter 4.

The control counter 4 counts the shift clock signal SCLK and outputs output signals Q0, Q1, Q2.
Is output. That is, the control counter 4 outputs the L-level output signals Q0, Q1, and Q2 until the 80-pulse shift clock signal SCLK is counted, and when the 80-pulse shift clock signal SCLK is counted, the output signal Q0 is set to the H-level, When the 160-pulse shift clock signal SCLK is counted, the output signal Q1 is set to the H level together with the output signal Q0, and when the 240-pulse shift clock signal SCLK is counted, the output signals Q0 and Q1 are output.
At the same time, the output signal Q2 is set to H level.

A reset signal RST is sent to the control counter 4.
The load signal L and the reset signal R are input to the OR circuit 5 that outputs the OR signal. When at least one of the load signal L and the reset signal R becomes H level, the OR circuit 5
Outputs an H-level reset signal RST to the control counter 4, and the count operation of the control counter 4 is reset based on the reset signal RST.

The shift clock signal SCLK and the output signal Q0 of the control counter 4 are input to the AND circuit 3a. Therefore, the control counter 4 counts the shift clock signal SCLK of 80 pulses and outputs the output signal Q0.
After H becomes H level, the shift clock signal SCLK is output from the AND circuit 3a.

The shift clock signal SCLK output from the AND circuit 3a is output to the shift registers SR239 to SR160 forming the second area E2 and also input to one input terminal of the AND circuit 3b.

The output signal Q1 is input to the other input terminal of the AND circuit 3b. Therefore, after the control counter 4 counts the 160-pulse shift clock signal SCLK and the output signal Q1 becomes H level, AN
The shift clock signal SCLK is output from the D circuit 3b.

The shift clock signal SCLK output from the AND circuit 3b is output to the shift registers SR159 to SR80 forming the third area E3 and also input to one input terminal of the AND circuit 3c.

The output signal Q2 is input to the other input terminal of the AND circuit 3c. Therefore, after the control counter 4 counts the 240-pulse shift clock signal SCLK and the output signal Q2 becomes H level,
The shift clock signal SCLK is output from the D circuit 3c.

The shift clock signal SCLK output from the AND circuit 3c is output to the shift registers SR79 to SR0 forming the fourth area E4. The output signals D319 to D0 of the shift registers SR319 to SR0 are output to the n-bit latch circuit as in the conventional example.

In the multi-stage shift register configured as described above, first, the load signal L or the reset signal R of H level is input and the count number of the control counter 4 is reset.

The shift clock signal SCLK is applied to the control counter 4 and the shift register SR in the first area E1.
319 to SR240, and serial input data is sequentially input to the input terminal SI of the first-stage shift register SR319. Then, the control counter 4 counts the number of pulses of the shift clock signal SCLK, and the serial input data is sequentially shifted to the shift registers SR319 to SR240.

At this time, the shift clock signal SCLK is not input to the shift registers SR239 to SR0 of the second area E2 to the fourth area E4, so that the shift register SR239 is not input.
239 to SR0 are inactive and do not consume power.

When the control counter 4 counts the 80-pulse shift clock signal SCLK in this state, the control counter 4 outputs the H level output signal Q0 to the AND circuit 3a.
Output to.

Then, the shift clock signal SCLK is applied to the shift registers SR319 of the first and second areas E1 and E2.
The serial input data SI input to SR160 and shifted to the shift register SR240 is shifted to the shift register S.
R239 to SR160 are sequentially shifted.

At this time, the shift clock signal SCLK is not input to the third and fourth shift registers SR159 to SR0, and the shift registers SR159 to SR0 are inactive and do not consume power.

When the control counter 4 counts the 160-pulse shift clock signal SCLK in this state, the control counter 4 outputs the H level output signal Q1 to the AND circuit 3.
output to b.

Then, the shift clock signal SCLK is applied to the shift registers SR in the first to third areas E1, E2 and E3.
Serial input data input to 319 to SR80 and shifted to the shift register SR160 is shifted to the shift register SR.
159 to SR80 are sequentially shifted.

At this time, the shift clock signal SCLK is not input to the shift registers SR79 to SR0 in the fourth area E4, and the shift registers SR79 to SR0 are inactive and do not consume power.

When the control counter 4 counts the 240-pulse shift clock signal SCLK in this state, the control counter 4 outputs the H level output signal Q2 to the AND circuit 3.
output to c.

Then, the shift clock signal SCLK is input to the shift registers SR319 to SR0 of all the areas E1 to E4, and the serial input data SI shifted to the shift register SR80 is sequentially shifted to the shift registers SR79 to SR0.

As described above, in this multistage shift register, the multistage shift registers SR319 to SR0 are divided into four regions, and the shift clock signal SCLK is supplied only to the shift registers in the regions where the serial input data is shifted. The shift registers in the areas are sequentially activated.

Therefore, it is possible to reduce unnecessary power consumption in the subsequent shift register and reduce the power consumption of this multi-stage shift register, so that the power consumption is increased even if the number of bits of the shift register is increased. Can be prevented.

Although the 320-bit shift register is divided into four regions in the above embodiment, the power consumption can be further reduced by dividing into a larger number of regions, and the number of bits of the shift register can be reduced. It is also easy to change the number of divisions.

[0039]

As described in detail above, the present invention exerts an excellent effect of providing a multistage shift register capable of reducing power consumption regardless of an increase in the number of bits.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing an embodiment of the present invention.

FIG. 3 is a timing waveform chart showing the operation of the embodiment.

FIG. 4 is a block diagram showing a conventional example.

FIG. 5 is a timing waveform chart showing the operation of the conventional example.

[Explanation of symbols]

 6 control circuit SR shift register SCLK shift clock signal SI input terminal E1-En area

Claims (2)

[Claims] 1. A multi-stage shift register that is activated based on a shift clock signal (SCLK) to sequentially input serial input data and shift the input serial input data bit by bit, the multi-stage shift register comprising: Register (SR) is set to multiple areas (E1
To En), the shift clock signal (SCL
A control circuit (6) for sequentially supplying the shift clock signal (SCLK) to the shift register (SR) in the area (E1 to En) where the serial input data is shifted based on the counting of the pulse number of (K). Is a multi-stage shift register. 2. The control circuit comprises a shift clock signal (S
CLK) counting the number of pulses and sequentially outputting a plurality of output signals (Q0 to Q2) based on the counted number, and an output signal (Q) of the control counter.
Shift clock signal (SCLK) based on 0 to Q2)
2. The multi-stage shift register according to claim 1, wherein the multi-stage shift register is configured by AND circuits (3a to 3c) that sequentially output to each of the areas (E2 to E4).