JPH0740096B2 - Drive - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving device having a plurality of stages of driver ICs. In particular, the present invention relates to a driving device using a driver IC for fetching data by enable control when a flat panel display is line-sequentially driven, including a dot matrix type liquid crystal display driver.

[0002]

2. Description of the Related Art Conventional dot matrix type liquid crystal displays generally have a system configuration in which shift register built-in drivers as shown in FIG. 1 are connected in cascade.
X _{1 to} X _{N in} FIG. 1 are drivers on the segment side of the LCD panel, and these drivers are for latching shift registers that are serial data transfer paths and shift data serial-parallel converted by the shift registers. A latch circuit and a conversion circuit for converting the latch data into a display drive signal by voltage conversion are integrated into one chip. The shift register built into this driver is 1980/8 /
As described in detail in “Nikkei Electronics“ Liquid crystal display that has begun to take hold in the market ”, the standard CM
It has the same function as the OS logic IC CD4094B.
That is, in FIG. 1, shift data is sequentially shifted from the D type flip-flop (hereinafter referred to as FF) of the data input terminal 4 to the D type FF of the output terminal side by the shift clock applied to the shift lock input terminal 5. It is of a basic type. Therefore, if a plurality of these drivers are connected in cascade, data will be sequentially transferred from the upper driver, that is, the driver X ₁ on the LCD controller 3 side to the lower driver X _N.

[0003]

In the dot matrix display, since each drive output of the driver corresponds to each electrode in the XY directions forming the matrix, if the display internal capacity increases, it is necessary. The number of drivers to be used increases.

On the other hand, since the dot matrix type liquid crystal display does not have a panel memory function, it is necessary to refresh all the dots within one frame period (generally around 60 Hz) like a CRT. This means that, from the controller side, as the display capacity increases, the data corresponding to the number of display dots must be transferred to the driver at a high speed within a fixed time. For example, in order to drive a panel of 640 dots × 128 dots, a shift clock of about 5 MHz is required. At this time, since all the drivers for driving the panel operate with the shift clock of 5 MHz, the current consumption due to the data transfer has reached a dozen mA. In the case of increasing the capacity of a liquid crystal display having a thin and low power consumption, the increase in the power consumption has been a serious problem.

The present invention solves the drawbacks of the prior art.
By separating the data transfer path from the data fetch enable signal (enable signal), the data holding means can be increased in capacity and suppressed in power consumption without impairing the expandability of the driver and the board mounting efficiency. It is to provide a driving device using a data transfer method.

[0006]

A drive device of the present invention divides a display device into a plurality of areas, and displays display data corresponding to each area from a data line through which display data of the plurality of areas is transmitted. In a drive device having a data holding means for sequentially storing in accordance with a first clock and comprising a plurality of driver ICs for supplying the display data to each of the areas, the driver IC performs a storage operation of the data holding means. A second enable signal input terminal for inputting an enable signal to be controlled, the enable signal input from the enable signal input terminal, and a second input from outside the driver IC.
A logical means for generating an internal enable signal for storing the display data in the data holding means on the basis of a clock, and the enable signal input from the enable signal input terminal in accordance with the second clock. Driver I
C enable signal input terminal for outputting to the enable signal input terminal.

[0007]

EXAMPLES The present invention will be described in detail below based on examples.

FIG. 2 is a connection diagram of an embodiment of the shift register which is the holding means of the present invention. FF _{1 of} FIG.
FF _m is m D-type FFs and constitutes the main body of the shift register. FIG. 3 shows a timing chart when the shift registers shown in FIG. 2 are connected in cascade. The FF 10 of FIG. 2 is a D-type FF, and the data input D 7 has the enable signal EI output from the controller, the clock input CK 8 has the enable clock ECL, and one input 5 of the AND gate 9. To the shift clock XCL, and the shift data XD input 4 receives the shift data XD. As shown in FIG. 3, since the enable signal EI is at the high level at the rising edge of the enable clock ECL, FF1
The output Q of 0 will be kept at the high level until the next enable clock ECL rises. Since the output Q of the FF10 is connected to one input terminal of the AND gate 9, the shift clock XCL is the output Q of the FF10.
Shift register (FF _{1 to} F
F _m ). This means that when the controller outputs such that one cycle of the enable clock ECL corresponds to one cycle of the shift clock XCL for m clocks in FIG. 3, the shift register (FF ₁
~ FF _m ) means that the shift data XD input to the shift data XD input 4 can be taken in in m states.

Next, if the output Q of the FF 10 changes to low level, the shift clock XCL is not applied to the shift register, and the shift operation is stopped. On the other hand, FF1
Since the output Q of 0 is connected to the enable output terminal 11, when the shift registers shown in FIG. 2 are cascade-connected, the enable signal input terminal of the next stage is delayed by one enable clock period. The enable output signal EO ₁ will be input. FIG. 4 shows a drive circuit configuration of a large display capacity liquid crystal panel in which a plurality of shift registers are cascade-connected in this manner. Figure 4
, X ₁ ... X _n are segment drivers of the LCD panel having the shift register shown in FIG. In FIG. 4, the enable signal E is sent from the controller for each frame.
If I is sent to the driver X ₁ , each driver will take in the shift data XD one after another. This is shown in the timing chart of FIG. Want to note here is from the controller, even if continuous data on serially are sent to the driver, if grasped a certain point in time, among the X driver X ₁ to X _n, only X
Only the driver is driven by the shift clock XCL. Therefore, compared to the case where all X drivers are driven by the shift clock as in the conventional method, according to the method of the present application, the current consumed by the X drivers is about 1 /
can be reduced to n. In the embodiment, the data is input to the register from one bus. However, if the data is input from a 4- or 8-bit parallel bus, the shift clock frequency is 1/4 or 1/8. Can be lowered.

[0010]

As described above, according to the present invention, there is an effect that the operation of the data holding means is stopped during an unnecessary period, and the current consumption can be greatly reduced. Further, since the present invention can be realized by adding a few terminals related to the enable signal to the conventional method, the capacity can be increased without impairing the expandability of the driver and the board mounting efficiency. Further, since the output of the enable signal to the enable terminal of the driver IC at the next stage is based on the second clock input from outside the driver IC, the power consumption of the data holding means can be minimized. is there.

[Brief description of drawings]

FIG. 1 is a connection diagram when a liquid crystal display is driven by a driver IC using a conventional shift register data transmission method.

FIG. 2 is a connection diagram of a data transmission system using a shift register showing an embodiment of the present invention.

FIG. 3 is a diagram specifically showing a timing chart of input / output signals in the embodiment of the invention.

FIG. 4 is a connection diagram for driving a liquid crystal display body by cascading driver ICs incorporating a data transmission system by a shift register according to an embodiment of the present invention by an enable chain system.

[Explanation of symbols]

1 ... Liquid crystal panel 2 ... Y (common) driver 3 ... LCD controller 4 ... Shift register data input terminal 5 ... Shift clock input terminal for shifting data 6 ... For latching shift data Latch pulse input terminal 7 ... Enable data input terminal 8 ... Enable clock input terminal for transferring enable data 9 ... AND gate 10 ... D type FF 11 ... Enable signal output terminal XCL ... Shift data Shift clock input signal for transfer EI ... Enable data input signal ECL ... Clock input signal for transfer of EI EO ₁ ... Enable output signal and enable output signal of driver ICX ₁ EO ₂ ...... For driver ICX ₂ Enable output signal EO _n・ ・ ・ Rice of driver ICX _n Cable output signal

Claims (1)

[Claims] 1. A data holding device in which a display device is divided into a plurality of areas, and display data corresponding to each of the areas is sequentially stored from a data line through which the display data of the plurality of areas is transmitted according to a first clock. A driving device having a plurality of driver ICs for supplying the display data to each area, wherein the driver IC receives an enable signal for controlling a storage operation of the data holding unit. A second signal input from outside the driver IC and the enable signal input from the enable signal input terminal;
A logical means for generating an internal enable signal for storing the display data in the data holding means on the basis of a clock, and the enable signal input from the enable signal input terminal in accordance with the second clock. Driver I
A driving device having an enable signal output terminal for outputting to the enable signal input terminal of C.