JPH05325539A - Memory control circuit and initializing method therefor - Google Patents

Abstract

PURPOSE:To effectively uitilize a memory address space by forming the chain of each FIFO memory circuit with a reading out address register as a starting point and a writing address register a finishing point. CONSTITUTION:One FIFO memory is constituted of writing address registers WAR 111 to 113 and reading address registers RAR 121 to 123. Data is stored in a common memory 101. When a writing FIFO specified signal is inputted to a WAR selector 110, it is written in an address NA indicated by an idle address FIFO 103 by a next address memory 102. Then, an address where data is first entered is indicated by the RAR and an address where the last written data is stored is indicated by the WAR, and constituting the chain of addresses. At the time of initialization, the content of the FIFO 103 and the value of a counter 104 are cleared and a counter output is outputted as an unused address NA. Thus, the effective utilization of the memory is realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control circuit for commonly using one memory to form a plurality of FIFO circuits.

[0002]

2. Description of the Related Art As an example of a memory control circuit for forming a plurality of FIFO circuits from one memory, Japanese Patent Application No.
There are 3448.

FIG. 5 shows a conventional memory control circuit, and FIG. 6 shows a configuration of a next address memory and a common memory used in the conventional memory control circuit. FIG. 7 is a diagram for explaining the address chain. The operation of the conventional FIFO circuit including the common memory and the memory control circuit will be described below with reference to FIGS.

First, the write operation will be described. Of the write address registers (WAR) 511 to 514, the one designated by the HD designating the FIFO circuit for writing the data is selected by the WAR selector 502 and output from the WAR selector as the write address WA. At the same time, the unused address output from the empty address FIFO 505 is set to the WAR selector 502.
Write to the write address register selected by. At this time, the unused address NAo is also written from the control circuit 5 to the next address memory 30 (FIG. 6) as the next address. By this operation, as shown in FIG.
Each write address register WAR511 to 514 stores an address at which data is to be written next, the next address is also written to the next address memory 30, and the address chain is updated every time data is written to the memory. Is becoming From the reading side, when one data is read from the memory, the address of the data to be read next (next address) can be read at the same time from that address.

Next, the read operation will be described. Of the outputs of the read address registers (RAR) 531 to 534, the RAR output corresponding to the FIFO circuit containing the next read data indicated by the CNT signal is RA
Selected by the R selector 503. Then, the data is read from the address output from the control circuit 5 as the read address RA. At the same time, R
The AR decoder 504 uses the gate 5 based on the instruction from the CNT.
Next address memory 30 which opens 41 to 544 and inputs from NAi to the RAR corresponding to the data to be read next
Write the next address read from. By this operation, every time data is read from the memory, the address of the data to be read next can be stored in the RAR. When the read address is output from the RAR selector 503, the data at that address is read and the address becomes unused. The unused address is
It is written in the empty address FIFO 505 and used again as a write address.

The WAR and RAR numbers corresponding to the FIFO circuit match when there is no data to be read in the FIFO. If there is data to be read, they will not match. The mismatch detection circuits (UM) 551 to 554 are UM
The presence of read data is notified through the selector 506. And a FIFO that does not contain data to be read
When data is read from the O circuit, the fact that there is no data is notified and the RAR value is controlled so that it cannot be changed.

FIG. 6 shows the configuration of the next address memory 30 and the common memory (31 to 35). The write address is input to the input WA of the memory, and the 2-port RAM 30
1 gives the address of the data to be written. The read address is input to the input RA of the memory and the 2-port R
The address of the data to be read is given to the AM 301. A bit indicating the validity of the input is attached to each of the inputs WA and RA. If the bit does not indicate the validity, the write operation or the read operation is not performed.

[0008]

When the FIFO circuit is constructed by using the conventional memory control circuit, there are the following problems.

The write address register is composed of F
There are as many IFO circuits as there are. The next write address is held respectively. This has the following problems in terms of effective use of memory.

For example, assume that the common memory has a capacity capable of storing 512 pieces of data and that 32 FIFO circuits are formed using the common memory. Then, 32 addresses out of 512 are reserved for storing the data when the data arrives next time, and are retained in the write address register even though the data is not written. That is, although there is a capacity to store 512 pieces of data, the capacity that can actually be used is 480 (= (512-3
2)), which means that the memory is not effectively used.

Next, the problems at the initial stage will be described. In the conventional write address management method, even when initialization is completed,
The write register must store an address to write data next. So, for example, F
The write address register must have a unique value at the time of initialization, for example, by making the number corresponding to the IFO number the register initial value. If the same memory control circuit is used, when the number of FIFO circuits to be configured changes, the address value is assigned to the unused FIFO memory circuit. Then, the initial address value assigned at the time of initialization is wasted by [the maximum value of the number of FIFOs that can be configured by the control circuit-the actual required number], and the address space cannot be effectively used.

Further, the empty address FIFO requires a circuit for storing an address which is not used at initialization.

It is an object of the present invention to solve the above problems and to provide a memory control circuit capable of effectively utilizing a memory address space.

[0014]

[Means for Solving the Problems] Writing and reading to and from one common memory is controlled, and a plurality of FIFOs (Firs) are controlled.
t In First Out) Stores a set of two types of registers (write address register and read address register) corresponding to the FIFO memory circuit to be configured and a free address not used in the common memory to configure the memory circuit. A memory control circuit comprising an empty address FIFO and an address memory for forming a chain of addresses of the number of FIFO memory circuits using a set of the registers, wherein when writing data to the FIFO memory circuit, the empty address FIFO The address value output from the FIFO is written to the address memory of the address indicated by the write address register corresponding to the FIFO memory circuit for writing data and to the write address register, and simultaneously to the common memory. Data is the free address When writing to an address output from the IFO and reading data from the FIFO memory circuit, the read address is output from the read address register corresponding to the FIFO memory circuit from which the data is read to the common memory and the address memory, The vacant address FIFO inputs the read address, simultaneously writes data to the common memory, and writes the next address read from the address memory to the read address register, thereby using the address memory, the write address register, and the read address register. An address chain is constructed with the read address register as the starting point and the write address register as the ending point.

[0015]

The address of the data to be written next is centrally managed by the circuit configuration and the address chain configuration method described above. Centralized management can eliminate reserved memory space even though it is not used.

By using the counter output as an empty address at the time of initialization, initialization of the empty address memory can be simplified, and at the same time, the memory space can be effectively used without depending on the number of FIFO memories to be configured.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an F using the memory control circuit of this embodiment.
2 to 4 are explanatory views for explaining the operation of the present embodiment, respectively.

In FIG. 1, 101 is a common memory for storing data, 102 is an address memory for forming an address chain, 103 is an empty address FIFO for storing unused addresses, and 104 is a counter for generating a write address at initialization. , 111 to 113 are write address registers (WA) corresponding to the FIFO memory circuit.
R) and 110 input the write FIFO designating signal to W
A write address register (WAR) selector that controls AR, 121 to 123 are read address registers (RAR) corresponding to the FIFO memory circuit, and 120 is a read address register (RAR) selector that inputs a read FIFO designating signal and controls RAR. Is. There are as many WAR and RAR register pairs as there are FIFO memory circuits.

The operation of the memory control circuit will be described below with reference to FIGS. First, a method of forming an address chain using the address memory 102, the write address register (WAR) and the read address register (RAR) will be described with reference to FIG.

One FIFO memory is composed of one set of WAR, RAR and address memory 102. The data is stored in the common memory 101.

RAR points to the address in which the data first entered. In FIG. 2, RAR indicates address 01. Data (# 1) is stored in address 01 of the common memory. On the other hand, the address 01 of the address memory 102 stores the address (03) of the address where the next data (data # 2) of the data # 1 is stored. 05 is stored in the address 03 of the next address memory. For WAR,
It indicates the address (address 05) where the last written data (# 3) is stored. Thus, RAR
And a WAR are combined to form a chain of addresses.

Next, the operation for writing data will be described with reference to FIG.
Will be explained. When writing data, the next data (# 4) is written to the address NA indicated by the empty address FIFO 103. At the same time, the address data of the address memory pointed to by WAR is rewritten to NA (07 in FIG. 2), and NA is set so that WAR itself also points to address 07. By this operation, the chain extends from the address 05 to the address 07.

Next, the operation for reading data will be described with reference to FIG. When reading data, RA
The data (# 1) is read from the address of the common memory indicated by R. After reading the data # 1, the address data (03) of the address memory pointed to by the RAR is set in the RAR.

A hardware configuration for realizing the above method will be described below with reference to FIG. The write data arrives together with a signal (write FIFO designating signal) indicating the FIFO memory circuit to write the data. Write FIF
The O designation signal is input to the WAR selector 110 and analyzes which FIFO the write data is written into. For the write FIFO, the WAR selector 110 assigns the empty address NA to the corresponding write address register (W
AR). At the same time, NA is written in the address of the address memory 102 indicated by WAR, and write data is written in the address indicated by NA. The method of creating the address chain is as described above with reference to FIGS.

On the other hand, when reading data, which FI
When a signal instructing whether to read data from the FO memory circuit (read FIFO specifying signal) is input, the data is read from the corresponding FIFO memory circuit. RAR selector 120 to which read FIFO designation signal is input
Analyzes from which FIFO memory circuit the data is read, and the corresponding read address register (RAR)
The selection signal is output to. The selected RAR is R
The address value stored in the AR is output to the common memory 101. In the common memory 101, the data at the address not designated by the RAR is output as read data. At the same time, the data in the address memory 102 indicated by the address value output by the RAR is stored in the RAR,
Set a new starting point for the address chain. Also, R
Since the read data is output from the address value output by the AR, it becomes an unused address. Therefore, this unused address value is the free address FI.
It is stored in the FO 103.

A FIFO memory circuit is constituted by the above write operation and read operation. When one data is stored in the FIFO memory circuit, RAR and WAR have the same value. Furthermore, the data is 1
When the data is read out one by one and the number of data stored in the corresponding FIFO memory circuit becomes 0, both registers (WAR and RAR) store a symbol that does not indicate any address. For example, "0" is used as the "symbol that does not indicate any address". If the value stored in WAR and RAR is non-zero, it indicates an address value,
If it is 0, it does not indicate address 0, but that there is no data in the corresponding FIFO memory circuit.

Although there are as many WAR and RAR register sets as there are FIFO memory circuits configured by the common memory, in this embodiment, each FIFO memory circuit is provided with an address for storing the data to be written next. Instead, set the NA value that is an empty address output to 1
Prepare as one address.

Next, using a common memory, a plurality of FIFOs are used.
A method of initializing a circuit included in the memory circuit will be described.

After initialization, no data is written in the common memory 101. Therefore, each register set (WAR and RAR) is set with a symbol indicating that no data is stored. After that, the operation when data arrives and a write address is generated will be described below. Free address F usually
The unused address NA output from the IFO 103 is used to form an address chain. However, at the time of initialization, first, the contents of the free address FIFO 103 and the value of the counter 104 are cleared. When the data arrives and the unused address NA is needed, the counter 104
The output is output as an unused address NA. NA is 1
Counter 1 to the number of data items that can be stored by all the FIFO memory circuits, which starts with the capacity of the common memory.
Output by 04. After that, the vacant address FI
The FO103 output is used as NA.

[0030]

As described above, according to the present invention,
Next, by holding the address to write the data in common in all the FIFO circuits, the memory can be effectively used. Further, the initialization operation independent of the number of configured FIFOs can be performed, the memory can be effectively used, and its practical effect is great.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a memory control circuit and its peripheral circuits for explaining the operation of an embodiment of the present invention.

FIG. 2 is a diagram showing an address chain for explaining the operation of the embodiment of the present invention.

FIG. 3 is a diagram showing an address chain for explaining the operation of the embodiment of the present invention.

FIG. 4 is a diagram showing an address chain for explaining the operation of the embodiment of the present invention.

FIG. 5 is a configuration diagram of a conventional FIFO memory circuit.

FIG. 6 is a configuration diagram of a conventional FIFO memory circuit.

FIG. 7 is a diagram showing an address chain for explaining the operation of a conventional FIFO memory circuit.

[Explanation of symbols]

 101 common memory 102 address memory 103 empty address FIFO 104 counter 110 write address register (WAR) select 111-113 write address register 120 read address register (RAR) selector 121-123 read address register

Claims (2)

[Claims] 1. A plurality of FIFOs (First In First Out) for controlling writing and reading in one common memory.
In the memory control circuit for composing the memory circuit, a set of two types of registers (write address register and read address register) corresponding to the composing FIFO memory circuit, and an empty space for storing an unused address in the common memory An address FIFO and an address memory for forming a chain of addresses of the number of FIFO memory circuits using the set of registers, and when writing data to the FIFO memory circuit, an address output from the empty address FIFO A value is written to the address memory of the address indicated by the write address register corresponding to the FIFO memory circuit for writing data and to the write address register, and at the same time, the data is written to the common memory at the empty address FI. When writing to an address output from O and reading data from the FIFO memory circuit, the read address is output from the read address register corresponding to the FIFO memory circuit from which the data is read to the common memory and the address memory, The vacant address FIFO inputs the read address, simultaneously writes data to the common memory, and writes the next address read from the address memory to the read address register, thereby corresponding to each FIFO memory circuit, to the read address register. The common memory and the address memory each store the address at which the data to be read first and the next address are stored, and the write address register stores the data that previously arrived at the memory. Have addresses on Li is written by using the address memory and the write address register and the read address register, and ending the write address register to starting the read address register FI
A memory control circuit characterized by forming a chain for each FO memory circuit. 2. The memory control circuit according to claim 1, wherein a counter is added as a constituent element of the memory control circuit, and the counter counts up each time data is written in the common memory, and when the memory control circuit is initialized, The data is output from the empty address FIFO until the total amount of data that can be held in all the FIFO memory circuits that can be configured in the common memory is written at the time of writing the data after clearing the internal capacity of the empty address FIFO. A method for initializing a memory control circuit, wherein the counter output value is used in place of the address value to be read, and thereafter the address value output from the FIFO memory for empty addresses is used.