JPH05324862A - Microcomputer - Google Patents

Abstract

PURPOSE:To improve the throughput of the microcomputer by increasing the conversion rate of an internal A/D converter. CONSTITUTION:The A/D converter 8' incorporated in the microcomputer 1 is equipped with plural A/D registers 13' for temporarily storing the conversion output of the A/D converter 12 of the A/D converter 8' until it is read out by a CPU; and the A/D conversion data are stored in the A/D registers 13' and the data held in the A/D registers 13' are read out at a CPU's request.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer in which the conversion rate of a built-in A / D converter is improved and the processing speed is improved.

[0002]

2. Description of the Related Art In recent years, microcomputers have
t, 8 bits, 16 bits, 32 bits ... versatility,
While higher performance is being achieved, there is a one-chip implementation that incorporates logic circuits and peripheral functions around the CPU to configure a microcomputer circuit that was conventionally configured with multiple chips with as few components as possible.

For example, in the one-chip microcomputer 1 shown in FIG. 6, the CPU 2, ROM 3,
In addition to the RAM 4, the I / O port 5, etc., the timer / counter 6, the interrupt controller 7, the A / D converter 8, and other functions are incorporated.

As shown in FIG. 5, the A / D converter 8 of the microcomputer 1 has a multiplexer circuit 10 having a plurality of input channels ch _{1 to} ch _n , a sample & hold circuit 11 and an A / D converter. 1
2 and an A / D control circuit 15 connected to the A / D register 13 and the internal data bus 14. The analog input signal selected by the multiplexer circuit 10 from the plurality of analog input signals is sampled. The & analog circuit is held by the & hold circuit 11, and the held analog input signal is converted into digital data by the A / D converter 12.

The converted digital data is temporarily stored in the A / D register 13, read out by the CPU 2 via the data bus 14, stored in the RAM 4, and then stored in the next analog input. A / D conversion processing is performed. At this time, the series of A / D conversion operations from the selection of the analog input of the multiplexer circuit 10 to the storage of the conversion data in the A / D register 13 are performed by the CPU 2
Is performed in accordance with the control sequence of the A / D control circuit 15 which has received the A / D conversion instruction from.

[0006]

However, the A / D converter of the above microcomputer has a problem that the conversion rate of the A / D conversion becomes relatively low.

The above-mentioned A / D converter is
Since the A / D converter synchronizes with the read timing of the CPU when the A / D converted data is read by the CPU,
If the conversion data of the D converter is temporarily stored in the A / D register and the stored data is not read by the CPU and the next A / D conversion is performed, the data in the A / D register is destroyed. Will end up. Therefore, the CPU is A / D
When the conversion is performed, other processing is interrupted, and as described above, the contents of the A / D register are saved in the RAM, and the saved data is restored and used again. ..

However, the access time of the RAM is low, and it takes a relatively long time for the CPU to read data, and when a plurality of analog inputs are sequentially A / D-converted at high speed, the A / D in the processing is performed. Not only can the conversion processing time not be fully satisfied, but CP is required for this series of processing.
Most of the execution time of U is occupied, which causes a problem of imposing a heavy load on the CPU.

Therefore, an object of the present invention is to prevent the conversion rate of the A / D conversion from being restricted by the access time of the RAM.

[0010]

In order to solve the above problems, the present invention has a CPU means and an A / D conversion means for A / D converting a plurality of analog inputs.
The / D conversion means selects a multiplexer from a plurality of analog inputs and outputs it, a sample and hold circuit that holds the analog input of the multiplexer during the A / D conversion period, and a hold output of the sample and hold circuit. An A / D converter for converting the data into digital data,
An A / D register for temporarily storing the converted output of the A / D converter until the CPU means reads it, and the multiplexer for selecting an analog input in accordance with an A / D conversion instruction from the CPU means, and the selected analog input. A /
A microcomputer having an A / D control circuit for A / D converting the D converter, comprising a plurality of the A / D registers, and storing the conversion data A / D converted by the A / D converter in the register. And store the stored data in C
The configuration is such that reading is performed in response to a request from the PU means.

The number of the A / D registers provided in the plurality corresponds to the number of analog input signals with high conversion frequency to be A / D converted, and at least equal to or more than the number of the input signals. It is preferable to prepare.

The microcomputer can also be used as a control device.

Further, the above microcomputer is suitable for use in an antilock control device for automobiles.

[0014]

In the microcomputer configured as described above, for example, a plurality of analog input signals input to the multiplex circuit are A / D-converted in sequence, and the digital data of the converted analog input signals are the analog input signals. After being sequentially stored and saved in the A / D register corresponding to, the A / D conversion process for the next analog input signal is repeated. That is, the A / D conversion is the A of the CPU.
This is executed independently of reading data from the / D register.

Further, the data stored in the A / D register is directly read by the CPU and various processing is performed.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. At that time, the parts described in the conventional example are given the same numbers in the drawings, and the description thereof will be omitted.

A microcomputer 1 having the same configuration as that shown in FIG. 6 according to this embodiment, as shown in FIG. 1, has an A / D converter 8'having m RAM memory registers. The register 13 '(n = m) and the A / D control circuit 15' are provided.

[0018] The A / D register 13 ', the address is allocated to each register (0 to m), the address, the channel ch ₁ to CH multiplexer circuit 10
It corresponds to the address of _n . Each register (0 to m) of the A / D register 13 'is also connected to the data bus 14 of the CPU 2, and the content of each register is directly read by the CPU 2. In the present embodiment, the number m of the A / D registers 13 'is the same as the number of input channels of the multiplexer circuit 10 (n = m). However, for example, the number of the A / D registers 13' is A / D converted. It may be set to be smaller than the number of input channels of the multiplexer circuit 10 (2 ≦ m ≦ n) by making only the input channels that need to be subjected to A / D conversion in a short cycle frequent.

On the other hand, from the A / D control circuit 15 ', the data select bus 16 is connected to the multiplexer circuit 10 and the A / D register 13', and the A / D control circuit 15 '.
Selects an input channel of the multiplexer circuit 10 on the basis of an A / D conversion instruction from the CPU 2, and at the same time, an A / D corresponding to the selected input channel.
Select register 13 '(0 to m) and select the selected A /
The analog signal data sequentially A / D converted is stored in the D register 13 '(0 to m). Thus, this A /
In the D converter 8 ', when A / D conversion is performed, A
The conversion data output from the / D converter 12 is sequentially A /
The data is saved in the D register 13 '(0 to m), and the A / D converter 8'is immediately in a standby state ready for the next A / D conversion.

Further, the conversion data stored in the A / D register 13 'is directly accessed by the CPU 2,
2 is read and processed.

That is, the CPU 2 does not read the data from the A / D register 13 'immediately after the A / D conversion is performed and saves the data in the RAM 4 as in the conventional case, but rather the A / D conversion is performed.
Since the data stored in the register 13 'may be directly read from the A / D register 13' as needed, for example, high-speed processing can be performed without interrupting other processing.

This embodiment is constructed as described above. Next, its operation will be described, for example, when the microcomputer 1 is used in the ESC computer 20 for controlling the antilock brake of the automobile shown in FIG. ..

Generally, the ESC computer 20 includes a permanent magnet 21 and a coil 2 shown in FIG. 3 attached to each wheel.
2 and a sensor rotor 23, a speed sensor 24
From this, as shown in FIG. 4, the amplitude and frequency change according to the wheel speed, and the output AC voltage is A / D converted, and the A
For example, the wheel speed and the vehicle body speed at the time of braking are calculated from the amplitude / frequency data of the / D-converted voltage, and the wheel lock state is determined from the difference between the calculated values. Depending on the ESC actuator 25
To control the brakes so that the wheels are not locked.

Now, the output of the speed sensor 24 of each wheel is connected to the analog inputs (ch _{0 to} ch ₃ ) of the A / D converter 8'of the microcomputer 1 of this embodiment used as the ESC computer 20, I let it be processed.

By the way, the speed sensor 24 is
As shown in FIG. 4, the generation frequency of the AC voltage greatly changes according to the wheel speed, and becomes a high frequency during high speed traveling. Therefore, if you try to detect this AC voltage,
At least twice the sampling frequency is required, but in the above microcomputer 1, the A / D
The converted data of each speed sensor 24 converted is
The data is sequentially stored in the A / D register 13 ', and at the same time as the data is stored, the next A / D conversion can be performed.
Since it is not necessary to save the data from the A / D register to the RAM 4 every time the conversion is performed, the A / D conversion can be performed at high speed.
The conversion rate is reduced. As a result, speed sensor 2
A large number of A / D converted data of the output waveform of No. 4 can be sampled, and the high frequency output waveform of the speed sensor 24 during high speed traveling can also be detected accurately.

At this time, the CPU 2 does not have to save the conversion data from the A / D register 13 'to the RAM 4 for each A / D conversion, so that the processing time spent for this processing is not needed and the microcomputer While the processing speed of No. 1 is improved, it is possible to use the spare processing time to perform higher processing.

In the embodiment, the A / D register 13 '
Although the selection of each register (0 to m) and the writing of A / D conversion data are performed by the A / D control circuit 15 ', other than this, for example, the A / D register 13'
It is also possible to omit the address control of each of the registers (0 to m) by the A / D control circuit 15 'by using a FIFO memory or the like.

[0028]

According to the present invention, since the A / D converter has a plurality of A / D registers configured as described above, it is not necessary to transfer and store the A / D conversion result in the RAM, and a plurality of input signals can be stored. When A / D is converted to A / D and the result is calculated / processed for control, the microcomputer can be made to perform high-speed control.

Particularly, in the brake control device using the signal from the wheel speed sensor, the use of this microcomputer enables high-speed control and more precise brake control.

[Brief description of drawings]

FIG. 1 is a block diagram showing an A / D conversion unit of a microcomputer according to an embodiment.

[Fig. 2] System block diagram of anti-lock brake

[Fig. 3] Schematic diagram of a speed sensor

FIG. 4 is an operation diagram of FIG.

FIG. 5 is a block diagram showing a conventional A / D converter.

FIG. 6 is a block diagram of a microcomputer.

[Explanation of symbols]

 1 Microcomputer 2 CPU 8 A / D converter 10 Multiplexer circuit 11 Sample & hold circuit 12 A / D converter 13, 13 'A / D register 15, 15' A / D control circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Fumio Makino 1-3-3 Shimaya, Konohana-ku, Osaka City Sumitomo Electric Industries, Ltd. Osaka Factory (72) Inventor Isao Ikki 1-1-1, Shimaya, Konohana-ku, Osaka City No. 3 Sumitomo Electric Industries, Ltd. Osaka Works

Claims (3)

[Claims] 1. A / C is provided with a CPU means and a plurality of analog inputs.
A / D conversion means for D-converting, wherein the A / D conversion means selects and outputs one analog input from a plurality of analog inputs, and an analog input of the multiplexer during an A / D conversion period. A sample-and-hold circuit for holding, an A / D converter for converting the held output of the sample-and-hold circuit into digital data, and the A / D converter
The A / D register for temporarily storing the converted output of the D converter until the reading by the CPU means, and the multiplexer,
A microcomputer having an A / D control circuit for selecting an analog input according to an A / D conversion command from a CPU means and for A / D converting the selected analog input. It is equipped with a plurality of
A microcomputer characterized in that the / D converter stores the converted data which has been A / D converted, and the stored data is read out in response to a request from the CPU means. 2. A control device comprising the microcomputer according to claim 1. 3. An antilock brake control device for an automobile, comprising the microcomputer according to claim 1.