JPH05324537A - Data transfer circuit - Google Patents

Abstract

PURPOSE:To increase the data transfer speed. CONSTITUTION:A transfer start address register 1 to which the transfer start address value of the transfer destination or the transfer source of memory data is set and a skip address register 2 to which the difference value of the address value updated at each time of transfer of memory data is set are provided, and the transfer start address value of the transfer destination or the transfer source of memory data and the address interval of data to be transferred are set to the transfer start address register 1 and the skip address register 2 respectively before the start of transfer of memory data, and the difference value set to the skip address register 2 is added to the preceding address value at each time of transfer operation. Thus, memory data is discontinuously transferred at set address intervals, and the data transfer speed is increased because memory data is transferred without using software.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory data transfer circuit used for sending dot information stored in a frame buffer memory to a print head in a dot printer.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing an example of a conventional data transfer circuit.

In a dot printer, a conventional memory data transfer circuit used when the dot information stored in the frame buffer memory is sent to the print head is as shown in FIG. A transfer address counter 28 that sets an initial address value of a transfer destination or a transfer source of memory data by 31 and counts each clock from the initial address value by the count clock 27, a set data input signal 31, and a count clock 27 are input. A transfer length counter 25 that counts the number of transfers and a timing control circuit 26 that controls the timing of the transfer destination or transfer source memory bus are provided.

The data transfer circuit thus configured sets the initial address value of the transfer destination or transfer source of the memory data to the transfer address counter 28 by the setting data input signal (DB) 31 and also transfers the transfer length counter 2
Set the length of the data to be transferred to 5. next,
When the transfer start signal (ST) 33 is input to the timing control circuit 26, the timing control circuit 26 sends out a bus release request signal (RQ) 34 requesting release of the memory bus. When the request for releasing the memory bus is accepted by this, the bus request acceptance signal (AK) 32 is input to the timing control circuit 26, the timing control circuit 26 sends out the memory control signal (CT) 35, and the transfer address counter 2
The address set to 8 is the transfer address signal (A
R) 37 and outputs the transfer address signal (AR) 37
Write or read to the memory address indicated by.

Subsequently, the timing control circuit 26 sends a count clock 27 to the transfer address counter 28 and the transfer length counter 25. Count clock 2
The transfer address counter 28, to which 7 is input, adds 1 to the address value to update the address value for transferring the data.
On the other hand, the transfer length counter 25 inputs the count clock 27 and subtracts 1 from the number of data to be transferred. In this case, when the number of data to be transferred becomes 0, the transfer end signal (TC) 36 is output.

The timing control circuit 26 keeps the memory control signal (CT) 35 and the count clock 2 until the transfer end signal (TC) 36 is sent from the transfer length counter 25.
7 is transmitted to repeat the memory data transfer, and the transfer of the memory data is ended by the input of the transfer end signal (TC) 36, and the bus release request signal (RQ) 34 is released.

[0007]

Since the conventional data transfer circuit as described above uses the counter which updates the address value by one each time the memory data is transferred,
Although it is possible to send data with continuous address values, there is a drawback that data with discontinuous address values cannot be sent.

Therefore, in the conventional dot printer, when the dot information stored in the frame buffer memory is sent to the print head, the arrangement of the dot information stored in the frame buffer memory is changed by software, The memory data transfer circuit enables continuous transmission.

[0009]

A data transfer circuit according to the present invention comprises a transfer start address register for setting an address value for starting the transfer of data in a transfer destination or transfer source memory before starting the transfer of data. A skip address register that sets the address interval of the data to be transferred before starting the data transfer, and a number of times of transferring the data before starting the transfer of the data, and subtracts 1 from the transfer number by a count clock to 0. Transfer length counter that outputs a transfer end signal, an adder that adds the output value of the skip address register and the output value of the flip-flop, and the address signal from the transfer start address register Is held and the count clock is input, the output signal of the adder is input and updated to it. When a setting operation for the flop, the transfer start address register, the skip address register, and the transfer length counter is completed, a transfer request signal is input, a bus release request signal is transmitted, and the bus release request signal is received. A timing control circuit for inputting a request acceptance signal, transmitting a memory control signal, and outputting the count clock.

[0010]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

The embodiment shown in FIG. 1 is a transfer start address register for inputting a setting data input signal (DB) 11 before starting data transfer to set a transfer start address value of a transfer destination or a transfer source of memory data. 1, a skip address register 2 for inputting a setting data input signal 11 to set an address interval of data to be transferred, and a plurality of flip-flops 3 for inputting and holding a transfer address signal from the transfer start address register 1 An adder 4 for adding the output value of the skip address register 2 and the output value of the flip-flop 3, a transfer length counter 5 for inputting a setting data input signal 11 to count the number of transfers, and timing control for the memory bus. Timing control circuit 6
It has and.

Next, the operation of the data transfer circuit configured as described above will be described.

First, the transfer start address register 1 inputs the setting data input signal (DB) 11 to the input terminal D before starting the transfer of the memory data, and transfers the transfer start address of the transfer destination or transfer source of the memory data. Set the value. The transfer start address value set at this time is input to the input terminal PS of the flip-flop 3 connected to the output terminal Q of the transfer start address register 1, and the same value is also set in the flip-flop 3. Next, the skip address register 2 inputs the setting data input signal (DB) 11 to the input terminal D and sets the difference value of the address value updated every time the memory data is transferred once. Further, the transfer length counter 5 receives the setting data input signal (DB) 11 from the input terminal D.
To set the memory data transfer length.

When the above setting operation is completed, the timing control circuit 6 inputs a transfer start signal (ST) 13 instructing the start of memory data transfer to the input terminal ST. As a result, the timing control circuit 6 outputs a bus release request signal (RQ) 14 in order to request another circuit sharing the memory to release the memory bus. When this bus release request is accepted, a bus request acceptance signal (AK) 12 indicating that the memory bus is available is input to the input terminal ACK of the timing control circuit 6. The timing control circuit 6 starts the transfer of the memory data when the bus request acceptance signal (AK) 12 is input, and sends out the memory control signal (CT) 15. Memory control signal (CT)
Reference numeral 15 is a signal for instructing writing or reading of data to or from the memory, which is a transfer address signal (A
R) Write or read data to or from the memory address specified by 17.

Next, the timing control circuit 6 sends a count clock 7 from its output terminal CK to the input terminal CK of the transfer length counter 5 and the input terminal CK of the flip-flop 3. Each time the count clock 7 is input, the transfer length counter 5 is incremented by 1 from the initially set count value.
When the count value becomes 0, the transfer end signal (TC) 16 is output.

On the other hand, the flip-flop 3 to which the count clock 7 is input updates the value held therein and outputs the transfer address signal 17 (AR) which becomes the next transfer address. The updated address is the flip-flop 3 before the update.
Is a result value obtained by adding the output value from the output terminal Q and the difference value of the address value set in the skip address register 2 from the output terminal Q by the adder 4.

The timing control circuit 6 repeats and outputs the memory control signal (CT) 15 and the count clock 7 until the transfer end signal (TC) 16 output from the transfer length counter 5 is input to the input terminal TC. To do. As a result, memory data can be transferred while updating the address for each value set in the skip address register 2.

[0019]

As described above, the data transfer circuit of the present invention includes a transfer start address register for setting a transfer start address value of a transfer destination or a transfer source of memory data,
A skip address register for setting the difference value of the address value updated each time the memory data is transferred is provided, and the transfer start address value of the transfer destination or the transfer source of the memory data is set before starting the transfer of the memory data. Set the transfer start address register, set the address interval of the data to be transferred to the skip address register, and add the difference value set in the skip address register to the previous address value for each transfer operation. There is an effect that memory data can be transferred discontinuously at address intervals, and because memory data can be transferred without using software, the effect that the data transfer speed can be improved is there.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a conventional data transfer circuit.

[Explanation of symbols]

 1 Transfer Start Address Register 2 Skip Address Register 3 Flip-Flop 4 Adder 5.25 Transfer Length Counter 6.26 Timing Control Circuit 7.27 Count Clock 28 Transfer Address Counter 11.31 Setting Data Input Signal (DB) 12.32 Bus Request acceptance signal (AK) 13/33 Transfer start signal (ST) 14/34 Bus release request signal (RQ) 15/35 Memory control signal (CT) 16/36 Transfer end signal (TC) 17/37 Transfer address signal ( AR)

Claims (2)

[Claims] 1. A transfer start address register for setting an address value for starting transfer of data in a transfer destination or transfer source memory before starting transfer of data, and a transfer start address register for transferring data before starting transfer of data. A skip address register that sets an address interval and a transfer length that sets the number of times of data transfer before starting data transfer and subtracts the number of times of transfer by 1 by a count clock to output a transfer end signal when it becomes 0. A counter, an adder for adding the output value of the skip address register and the output value of the flip-flop, and the addition when the address signal from the transfer start address register is input and held and the count clock is input. And a transfer start address register for inputting and updating the output signal of the converter When the setting operation for the skip address register and the transfer length counter is completed, a transfer request signal is input to send a bus release request signal, and when the bus release request signal is accepted, a bus request acceptance signal is input to the memory. A data transfer circuit, comprising: a timing control circuit that outputs a control signal and outputs the count clock. 2. A transfer start address register for setting an address value for starting transfer of data in a transfer destination memory or a transfer source memory before starting data transfer, and a transfer start address register for transferring data before starting data transfer. A skip address register that sets an address interval and a transfer length that sets the number of times of data transfer before starting data transfer and subtracts the number of times of transfer by 1 by a count clock to output a transfer end signal when it becomes 0. A counter, an adder for adding the output value of the skip address register and the output value of the flip-flop, and the addition when the address signal from the transfer start address register is input and held and the count clock is input. A plurality of flip-flops for inputting and updating the output signal of the converter, and the transfer start address register. When a setting operation for the register, the skip address register, and the transfer length counter is completed, a transfer request signal is input to send a bus release request signal, and when the bus release request signal is accepted, a bus request acceptance signal is input. And a timing control circuit which outputs a memory control signal, outputs the count clock, inputs the transfer end signal, and ends the operation.