JPH05324319A - High speed arithmetic processing system - Google Patents

Abstract

PURPOSE:To enable an operation at a high speed by precisely and quickly issuing an instruction for stopping and releasing an instruction execution pipeline to an instruction control part when microprogram dividing processing is requested by providing an operation completion signal(VEND signal) on an operation overlap processing cycle. CONSTITUTION:An instruction processor is provided with the instruction execution pipeline of variable length with the operation overlap processing cycle made into multiple stages in addition to an operation cycle. Also, it is equipped with a floating point computing element 210 by which an operation overlap operation can be performed and a versatile computing element 110 and performs operation control by a microprogram. The operation completion signal VEND in the operation overlap processing cycle is provided, and the operation of operation overlap processing made into multiple stages is executed by using the floating point computing element 210, and when the microprogram dividing processing is requested while executing the processing, the processing of instruction sequence can be advanced by controlling the timing to issue the operation completion signal VEND in the operation overlap processing cycle.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic processing system for an instruction processing device having a variable length instruction execution pipeline. The instruction processor must be capable of executing many instructions at high speed. Above all, it is the four arithmetic operations that require particularly high speed, especially for large machines,
Since the high-speed processing capability of scientific and technological calculations is important, the ability to execute floating-point arithmetic instructions at high speed is required.

For this reason, a large-scale machine is provided with a dedicated floating-point arithmetic unit, and further, for data processing, instructions are executed at high speed by an advanced pipeline processing system. Specifically, arithmetic overlap processing, which can be configured relatively easily, is often used. When the arithmetic overlap processing is used, a dedicated floating point arithmetic unit is configured to be capable of arithmetic overlap operation so that the instruction execution pipeline has an arithmetic overlap processing cycle (V cycle) in addition to a normal arithmetic cycle. Set up.

Floating point arithmetic instructions use this V cycle.
Use and execute. At least one V cycle is required
However, regarding floating point arithmetic instructions that require more than 3 cycles,
In order to achieve high-speed processing with
For example, V₁ Cycle, V ₂ Increase to cycle
It In other words, increase the number of arithmetic overlap processing cycles
To do.

On the other hand, some floating point arithmetic instructions require special micro program processing depending on the contents of their operand data. When the floating-point arithmetic unit outputs an exceptional intermediate result during execution of the operation, the micro
Special post-processing by program processing may be required.

[0005]

2. Description of the Related Art Generally, the processing system of an arithmetic control unit in an instruction processing device is divided into the following two cases. One is a method in which a micro program controls a general-purpose arithmetic unit to execute an instruction, that is, a case of performing micro program processing.

In the second method, a dedicated arithmetic unit such as a floating point arithmetic unit is provided, and the execution of normal operand data is executed at high speed by the dedicated arithmetic unit. , Special operand data processing, or processing of exceptional intermediate results output by a computing unit.
This is a method that is used properly according to the content of data.

By the way, conventionally, in the case where an instruction to be executed needs to perform special processing and the necessity of the special processing can be judged only by decoding the instruction, the instruction control unit , When the instruction is decoded and the arithmetic control unit is activated, the instruction code for the arithmetic control unit is modified to instruct the arithmetic control unit that the instruction requires special processing. Was.

On the other hand, some floating point arithmetic instructions require special post-processing to obtain the final result of the intermediate result output by the floating point arithmetic unit, depending on the operand data. There is. There are also instructions that require special processing depending on the operand data.

When special processing is required depending on the operand data and when special post-processing is required, it is naturally impossible for the instruction control unit to judge the necessity.

Therefore, when the arithmetic control unit is activated and the operand data of the instruction to be executed is supplied from the storage control unit or the instruction control unit to the arithmetic control unit, the arithmetic control unit analyzes the operand data. Therefore, the necessity of the above processing is determined. At this time, a dedicated floating-point arithmetic unit corresponding to a command code from the instruction control unit to the arithmetic control unit is activated.

When the above processing is required by analyzing the operand data, the arithmetic control unit does not notify the instruction control unit of the arithmetic end signal, thereby stopping the instruction execution pipeline of the instruction control unit. ..

Then, the arithmetic control unit determines the processing of the instruction that has detected the above condition in the micro program, and continues the instruction processing under the micro program control. When the micro program indexing process ends, the operation control unit notifies the instruction control unit of an operation end signal and cancels the stopped state of the instruction execution pipeline of the instruction control unit.

FIG. 4 shows an operation example when a general instruction is executed in the conventional instruction execution pipeline. In the instruction execution pipeline, the processing executed in each cycle is clearly defined.

In the figure, D cycle is instruction decode cycle, A cycle is operand address calculation cycle, and T cycle is T.
A cycle is a TLB access cycle, a B cycle is an operand cache access cycle, an E cycle is an operation cycle of the operation control unit, and a W cycle is an operation result write cycle.

Since each cycle of the instruction execution pipeline can be overlapped, the processing result can be obtained for each cycle unless the subsequent instruction is kept waiting due to the influence of the preceding instruction.

In FIG. 4, the operand register 10
1 is for storing operand data,
The calculation result register 102 is for storing the calculation result. Further, the general-purpose arithmetic unit 110 performs various calculations. Note that the EEND signal, which will be described later, is not notified at the timing shown by the dotted line in the figure.

The instructions shown in FIG.
It is an instruction that executes an operation in a cycle. In this case, the operation control unit sends an operation end signal (EEND signal) to the instruction control unit.
You do not need to notify me. However, a multi-E cycle instruction that executes an operation in two cycles or more like
In the final operation cycle (E cycle), it is necessary to notify the instruction control unit of the operation end signal (EEND signal).

FIG. 5 and FIG. 6 show an operation example of the instruction execution pipeline when the operation overlap processing is performed by the conventional method. Execution of floating-point arithmetic may require two or more cycles, and if arithmetic overlap processing is possible, arithmetic overlap processing cycle (V cycle)
To use.

FIG. 5 shows floating point operation instructions 2 to
It shows the case of executing in a cycle. In the figure, a floating-point arithmetic unit 210 is a dedicated arithmetic unit that can perform arithmetic overlap processing, and executes instructions in two cycles. Figure 5
In the configuration shown in, the calculation process is executed in two cycles, but the calculation result is
It is output every other cycle.

Since the final results of all the instructions of ,,, and can be obtained by the dedicated floating point arithmetic unit 210, the execution of the arithmetic can be continued in a fixed cycle. Therefore, it is not necessary for the arithmetic control unit to notify the instruction control unit of the arithmetic end signal (EEND signal).

FIG. 6 shows a case where a floating point arithmetic instruction is executed in 3 cycles. Floating point arithmetic unit 310
Is a dedicated arithmetic unit that can perform arithmetic overlap processing,
Instructions are executed in 3 cycles. In the configuration shown in FIG.
The calculation process is executed in three cycles, and the calculation result is output every two cycles by the calculation overlap process.

The instructions of ,, and are the instructions for which the final arithmetic result can be obtained by the floating point arithmetic unit 310. On the other hand, the instruction 1 is an instruction that requires special post-processing for the operation result of the floating point arithmetic unit 310. Therefore,
When executing an instruction, the instruction control unit is prevented from being notified of the operation end signal (EEND signal) before the necessary post-operation processing is determined in the microprogram. Then, the general-purpose arithmetic unit 110 by the micro program control
And the instruction processing is continued.

When the processing is completed, the final operation result is set in the operation result storage waiting register 103, and the operation end signal (EEND signal) is notified to the instruction control unit. By the notification of the operation end signal (EEND signal), the instruction execution pipeline enters the operation overlap processing cycle (V cycle). In the operation overlap processing cycle (V cycle), the contents of the operation result storage wait register 103 are transferred to the operation result register 102.

As shown in FIG. 6, the arithmetic overlap processing cycle (V cycle) is only one cycle. Therefore, despite providing the dedicated floating-point arithmetic unit 310 capable of arithmetic overlap processing,
Even in the optimum case, the calculation result can be obtained only every two cycles.

Therefore, a method of deepening the degree of overlap of the arithmetic overlap processing, that is, a method of making the arithmetic overlap processing cycle (V cycle) multistage is used. For example, the arithmetic overlap processing cycle (V cycle) is changed to V ₁ cycle and V ₂ cycle.

FIG. 7 shows the arithmetic overlap processing cycle.
(V cycle) to V₁ Cycle and V ₂ Change to cycle
It shows an operation example of the instruction execution pipeline when it is changed
It In the figure, it is the first arithmetic overlap processing cycle.
V₁ The cycle has a store wait register 104
It It is the second operation overlap processing cycle.
V ₂ The cycle has a storage wait register 103
It

The instruction processing of (1) is determined in a micro program, and the general-purpose arithmetic unit 110 is controlled by the micro program.
When the operation result is obtained by operating, the operation result is stored in the storage wait register 1 out of the storage wait registers 104 and 103 having two stages included in the operation overlap processing cycle.
Set to 04.

In the V ₁ cycle, the storage wait register 10
The contents of 4 are transferred to the storage wait register 103. In the V ₂ cycle, the contents of the storage wait register 103 are transferred to the operation result register 102. According to the configuration example of FIG. 7, when the dedicated floating point arithmetic unit 310 can obtain the final arithmetic result, the arithmetic result can be output for each cycle.

[0029]

An operation end signal (hereinafter referred to as "EEN") to the instruction control unit is detected by detecting a case where special post-processing is required depending on the operand data.
D signal ". ), If the indexing conditions for the micro program are separated in detail, useless micro program indexing does not occur. However,
Since the creation logic of the EEND signal becomes complicated, the signal delay of the EEND signal to the instruction control unit increases.

Since the EEND signal is used directly for controlling the instruction processing pipeline, an increase in the signal delay of the EEND signal is an unacceptable problem especially in a high speed instruction processing device. Therefore, the configuration shown in FIG. 7 cannot be practically used.

This problem is the same when the floating-point operation instruction shown in FIG. 5 is executed in two cycles, and in the two-cycle floating-point operation, the micro program indexing process is performed due to the signal delay of the EEND signal. Cannot be used.

That is, in the configuration shown in FIG. 5, the processing in the case where no index is made to the micro program is
Even if it can be executed in 2 cycles by using the dedicated floating point arithmetic unit, there is a process when it is necessary to determine to the micro program depending on the operand data, so the actual floating point arithmetic of 2 cycles You cannot use the bowl.

In view of the above conventional problems, the present invention provides an instruction to an instruction control unit when the need for micro program indexing processing arises depending on the operand data of the instruction to be executed. An object of the present invention is to provide a means for realizing a high-speed operation by an operation overlap processing by accurately and promptly issuing instructions for stopping and canceling the execution pipeline.

[0034]

According to the present invention, the above object is achieved by means as set forth in the claims.

That is, the invention of claim 1 has a variable length instruction execution pipeline having a multistage operation overlap processing cycle in addition to the operation cycle, and a dedicated floating point operation capable of operation overlap operation. A vessel,
In an instruction processing device having a general-purpose arithmetic unit and performing arithmetic control by a micro program, an arithmetic end signal of an arithmetic overlap processing cycle different from the EEND signal is provided, and arithmetic overlap operation is possible in the arithmetic overlap processing. Using the dedicated floating-point arithmetic unit, the operation of the arithmetic overlap processing is executed in the multi-stage arithmetic overlap processing cycle, and during the execution, the arithmetic overlap processing cycle is extended and the microprogram indexing processing is executed. If so, it is a high-speed arithmetic processing method that advances the processing of the instruction sequence by controlling the timing of issuing the arithmetic end signal in the arithmetic overlap processing cycle.

Further, according to the invention of claim 2, an operand save register for saving the contents of the operand register is provided, and the operation overlap processing cycle is extended to execute the microprogram indexing processing. Operand data of an instruction following the instruction is transferred from the operand register to the operand save register as needed when the execution of the microprogram indexing process is started, and when the execution of the microprogram indexing process is completed, This is a high-speed arithmetic processing method for restoring the operand data saved in the operand save register to the operand register.

[0037]

In the present invention, in addition to the conventional operation end signal for notifying the end of the operation cycle (E cycle), a new operation end signal for the operation overlap processing cycle (hereinafter referred to as "VE
ND signal ”. ) Is provided.

Then, in the instruction for performing the arithmetic overlap processing, the VEND signal is notified to the instruction control unit in the first cycle (V ₁ cycle) of the arithmetic overlap processing. At this time, the EEND signal is not notified.

1 and 2, instead of the conventional EEND signal for notifying the end of the operation cycle (E cycle),
An example of the operation of the instruction execution pipeline when the VEND signal according to the present invention is provided and the VEND signal is used will be shown. In the figure, CSA indicates an address register of the control store, and CSD indicates a control register.
Indicates store read / register.

FIG. 1 is a diagram showing a case where a floating point arithmetic operation instruction is executed in two cycles. As is apparent from this configuration example, conventionally, in the 2-cycle floating point operation, the micro program indexing process could not be applied due to the signal delay of the EEND signal.
By using the END signal, the micro program indexing process can be performed even in the 2-cycle floating point operation.

FIG. 2 is a diagram showing a case where a floating point arithmetic operation instruction is executed in three cycles. As shown in FIG. 2, even in an instruction processing pipeline having a multi-stage arithmetic overlap processing cycle, micro program indexing processing has become possible.

However, it is possible to use the VEND signal.
There are some problems that must be resolved. VEND
When using signals, micro program indexing process
Is V ₁ Run in a cycle. During this time,
If the subsequent instruction shown does not wait under other conditions,
The operation cycle (E cycle) is awaited.

Therefore, it is necessary to consider means for making this subsequent instruction wait in the operation cycle (E cycle). For example, when performing special processing or post-processing of calculation results in micro program indexing processing,
The instruction control unit specifies the instruction code for the arithmetic control unit in the subsequent instruction entry.

If necessary, a register 105 for saving the operand data of the subsequent instruction from the operand register 101 is provided to hold the operand data of the subsequent instruction. And micro
When the program indexing process ends, the contents of the operand save register 105 are changed to the operand register 10
Restore to 1.

When the micro program indexing process is completed, the micro code is read from the control store (CS) by the command code of the subsequent instruction, the read micro code is decoded, and the execution of the subsequent instruction is started.

[0046]

FIG. 3 is a diagram showing an embodiment of the present invention.
In the figure, operand registers 101-1 and 101-2,
101-3, the operation result register 102, the two-stage storage wait registers 103, 104, and the operand save registers 105-1, 105-2, 105-3 have the same configurations as those already described in other figures. is there.

Micro program work register 10
Reference numerals 6-1, 106-2 and 106-3 hold operand data and intermediate results of micro program processing, and the selector circuit 712 is a bus or BB.
The US is selected.

The floating point arithmetic unit 210 is a dedicated arithmetic unit capable of performing arithmetic overlap operation and processes an instruction in two cycles. The floating-point arithmetic unit 310 is a dedicated arithmetic unit that can perform arithmetic overlap operation, and processes instructions in 3 cycles. The general-purpose arithmetic unit 110 performs various arithmetic operations such as micro-program indexing operation.

The calculation result 1101 is the calculation result of the general-purpose calculator 110. Further, the calculation result 2101 is a calculation result of the 2-point floating point calculator 210, and the calculation result 3101 is a calculation result of the 3-cycle floating point calculator 310.

The status 1102 indicates the general-purpose arithmetic unit 110.
Operand status and operation result status of. The status 2102 indicates that the floating point arithmetic unit 2
10 is the operand status and the operation result status, and the status 3102 is the floating point arithmetic unit 310.
Operand status and operation result status of.

A control store (hereinafter referred to as "CS") 710 stores a micro program of the arithmetic control unit. The address register 701 is
It is an address register of the CS 710 (hereinafter referred to as “CSA”), and has a microcode address 7101.
Is the subsequent microcode address of CS 710 in a multi-E cycle.

The entry address 7102 is the entry address of the microprogram indexing process, and the read register (CSD) 702 is the CS71.
0 read register.

The status control circuit 711 controls various statuses according to the situation. The EEND signal 7111 and the VEND signal 7112 have already been described in detail. The control signal 7113 is a control signal of the CSA 701.

The instruction execution pipeline control circuit 750 is
It controls the pipeline operation of the instruction processing unit. The command code 7501 is a command code for the arithmetic control unit, and the register stack 760 is composed of various registers. Operand cache 770 is a high speed memory that holds operand data. 7601 is the operand data read from the register stack 760. 7602 is the operand data read from the register stack 760. 7701 is the operand data read from the operand cache 770. 1021 is the operation result data from the operation result register 102.

[0055]

As described above, according to the present invention,
In a configuration including a variable length instruction processing pipeline having a multi-stage arithmetic overlap processing cycle and a dedicated floating point arithmetic unit capable of arithmetic overlap operation,
Since the VEND signal is provided, the indexing processing of the micro program can be realized even in the instruction processing pipeline having the multistage operation overlap processing cycle.

Further, the high-speed arithmetic processing is executed by the multi-stage arithmetic overlap processing and the dedicated floating point arithmetic unit, while the special processing and the post-processing of the arithmetic result are processed by the micro program control. This makes it possible to achieve both high-speed arithmetic processing by a dedicated floating-point arithmetic unit and appropriate micro-program processing. Therefore, there is an effect that it is possible to realize an appropriate configuration that makes use of the dedicated floating-point arithmetic unit.

[Brief description of drawings]

FIG. 1 is a diagram showing an operation example of an instruction execution pipeline according to the present invention.

FIG. 2 is a diagram showing an operation example of an instruction execution pipeline according to the present invention.

FIG. 3 is a diagram showing an embodiment of the present invention.

FIG. 4 is a diagram showing an operation example of a conventional instruction execution pipeline.

FIG. 5 is a diagram showing an operation example of a conventional instruction execution pipeline.

FIG. 6 is a diagram showing an operation example of a conventional instruction execution pipeline.

FIG. 7 is a diagram showing an operation example of a conventional instruction execution pipeline.

[Explanation of symbols]

101, 101-1, 101-2, 101-3 Operand register 102 Operation result register 103, 104 Storage wait register 105, 105-1, 105-2, 105-3 Operand save register 106-1, 106-2, 106-3 Work register 110 General-purpose arithmetic unit 210,310 Floating-point arithmetic unit 701 Address register 702 Read register 710 Control store 711 Status control circuit 712 Selector circuit 750 Instruction execution pipeline control circuit 760 Register stack 770 Operand cache 1101, 1021, 3101 Operation result 1102, 2102, 3102 Status 7101 Microcode address 7102 Entry address 7111 EEND signal 7112 VEN Signal 7113 control signal 7501 command code 7601,7602,7701 operand data 1021 operation result data

Claims (2)

[Claims] 1. A dedicated floating point arithmetic unit having a variable length instruction execution pipeline having a multi-stage arithmetic overlap processing cycle in addition to the arithmetic cycle and capable of arithmetic overlap operation, and a general-purpose arithmetic unit. In the instruction processing device that has the operation control by a micro program, the operation end signal of the operation overlap processing cycle different from the operation end signal of the operation cycle is provided, and the operation overlap operation can be performed in the operation overlap processing. The dedicated floating-point arithmetic unit is used to execute the arithmetic overlap processing in a multi-stage arithmetic overlap processing cycle, and during that execution, the arithmetic overlap processing cycle is extended to execute the microprogram indexing processing. If it is decided to do so, the operation end signal of the operation overlap processing cycle is issued. Fast processing method, characterized in that that will timing control to advance the processing of the instruction sequence. 2. An operand save register for saving the contents of an operand register, and an operand of an instruction following an instruction for extending a calculation overlap processing cycle and executing microprogram indexing processing. Data is transferred from the operand register to the operand save register as needed at the start of the microprogram indexing process, and saved to the operand save register at the end of the microprogram indexing process. The high-speed arithmetic processing method according to claim 1, wherein the operand data is restored in the operand register.