JPH05324005A - Command ff/fb controller - Google Patents

Command ff/fb controller

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Publication number
JPH05324005A
JPH05324005A JP12483792A JP12483792A JPH05324005A JP H05324005 A JPH05324005 A JP H05324005A JP 12483792 A JP12483792 A JP 12483792A JP 12483792 A JP12483792 A JP 12483792A JP H05324005 A JPH05324005 A JP H05324005A
Authority
JP
Japan
Prior art keywords
signal
control
output
lower limit
target value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12483792A
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Japanese (ja)
Other versions
JP2994135B2 (en
Inventor
Kazuo Hiroi
和男 広井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
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Filing date
Publication date
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Priority to JP4124837A priority Critical patent/JP2994135B2/en
Publication of JPH05324005A publication Critical patent/JPH05324005A/en
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Publication of JP2994135B2 publication Critical patent/JP2994135B2/en
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Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To improve the controllability, to prevent a reset windup, and to obtain balanceless and bumpless operation at the time of gain correction and automatic-manual switching. CONSTITUTION:A command FF control part 20 and a speed type two-degree-of- freedom PI control part 30 are combined with each other and the PI control part is provided with a switch part 35 on the output side of an arithmetic means 34 in addition to a command filter means 31 which gives a two degree of freedom to P operation while speed type P control arithmetic 33 and speed type I control arithmetic 34 are separated. Then FB control and FF control are put together in the form of speed type signals and converted into a position control signal, which is passed through an upper/lower-limit limiting means 42 to obtain an operation signal. At this time, a deviation deciding means 44 decides whether or not there is a deviation from a limited value from the input/ output difference of the upper/lower-limit limiting means and decides the variation state of a position type control signal by integral operation from the signs of the decision signal and the output of an I control arithmetic means, thereby performing and stopping the integral operation by turning ON and OFF a switch means.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、ボイラ負荷配分制御シ
ステムのボイラ蒸気流量制御装置や多種燃料燃焼システ
ムの全熱量制御装置などに利用される目標値FF制御と
FB制御とを組合わせた目標値FF/FB制御装置に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is a combined target of target value FF control and FB control used in a boiler steam flow rate control device for a boiler load distribution control system, a total heat amount control device for a multi-fuel combustion system, and the like. Value FF / FB controller.

【0002】[0002]

【従来の技術】この種の制御装置は、主として目標値と
操作量とが共に同一または異種の工業単位で表されるカ
スケード制御系の1次制御ループに適用されることが多
く、この場合には目標値を直接FF制御し、FB制御は
FF制御量を制限された範囲内で修正制御する構成とな
っている。
2. Description of the Related Art A control device of this type is often applied mainly to a primary control loop of a cascade control system in which a target value and a manipulated variable are both represented by the same or different industrial units. Has a configuration in which the target value is directly FF controlled, and the FB control is a configuration in which the FF control amount is corrected and controlled within a limited range.

【0003】このような技術の代表的な適用例として
は、例えばボイラ負荷配分システムにおけるボイラ蒸気
流量制御装置や多種燃料燃焼システムの全熱量制御装置
などが上げられる。
Typical applications of such a technique include, for example, a boiler steam flow controller in a boiler load distribution system and a total heat quantity controller for a multi-fuel combustion system.

【0004】ところで、従来のボイラ負荷配分システム
は、図5に示す如く熱供給配管1に対して複数のボイラ
1 ,22 ,…が並列に接続され、これらボイラ21
2,…出力側の蒸気流量検出器31 ,32 ,…で検出
された蒸気流量PV1 ,PV2 ,…が加算手段4に導入
され、ここで得られたトータル蒸気流量と蒸気圧力調節
装置5の圧力調節出力信号とを加算手段6で加算する。
そして、この加算信号にそれぞれ負荷配分比率α1 ,α
2 ,…を乗じた各配分信号を目標値SV1 ,SV2 ,…
として各目標値FF/FB制御装置71 ,72 ,…に導
入する。
Meanwhile, the conventional boiler load distribution system includes a plurality of boiler 2 1, 2 2 for the heat supply pipe 1 as shown in FIG. 5, ... are connected in parallel, these boilers 2 1,
2 2 , ... The steam flow rates PV 1 , PV 2 , ... Detected by the output-side steam flow rate detectors 3, 1 , 3 2 , ... Are introduced into the adding means 4, and the total steam flow rate and steam pressure obtained here are obtained. The pressure adjusting output signal of the adjusting device 5 is added by the adding means 6.
Then, the load distribution ratios α 1 and α are added to the added signal, respectively.
2, the target value of each allocation signal multiplied by ... SV 1, SV 2, ...
Is introduced into each target value FF / FB control device 7 1 , 7 2 , ....

【0005】ここで、例えば1つの制御装置7(=
1 )は、図6に示すように目標値SVn (SV1 )に
係数手段11でFF制御ゲインK(Kは通常1近傍とす
る)を乗算して基本操作量K・SVn とし、かつ、目標
値SVn と蒸気流量PVn (=PV1 )とを一般のPI
Dコントローラ12に導き、ここで偏差演算手段13に
て信号SVn とPVn との偏差en を求める。さらに、
下段の速度形PID調節演算手段14では前記偏差en
に基づいて下記する演算、つまり △MVn =Kp {(en −en-1 )+(△t/TI )・en +(TD /△t)・(en −2en-1 +en-2 )}…(1) なる速度形演算を行って今回変化分の速度形PID調節
演算信号△MVn を求めた後、速度形−位置形信号変換
手段15に導入し、ここで MVn =MVn-1 +△MVn ……(2) の演算式により位置形PID調節信号MVn を求めてい
る。
Here, for example, one controller 7 (=
7 1 ), as shown in FIG. 6, the target value SV n (SV 1 ) is multiplied by the FF control gain K (K is usually close to 1 ) in the coefficient means 11 to obtain the basic manipulated variable K · SV n , In addition, the target value SV n and the steam flow rate PV n (= PV 1 )
It is led to the D controller 12, and the deviation calculating means 13 determines the deviation e n between the signals SV n and PV n . further,
In the lower speed type PID adjustment calculation means 14, the deviation e n
Described below on the basis of the calculation, i.e. △ MV n = K p {( e n -e n-1) + (△ t / T I) · e n + (T D / △ t) · (e n -2e n -1 + e n-2 )} (1) The speed type calculation is performed to obtain the speed type PID adjustment calculation signal ΔMV n corresponding to the current change, and then the speed type-position type signal conversion means 15 is introduced. Here, the position-type PID adjustment signal MV n is obtained by the arithmetic expression of MV n = MV n-1 + ΔMV n (2).

【0006】なお、上式においてKp :比例ゲイン、T
I :積分時間、TD :微分時間、△t:制御周期、
n :今回の偏差信号、en-1 :前回の偏差信号、e
n-2 :前前回の偏差信号、MVn :今回の調節信号、M
n-1 :前回の調節信号、△MVn:今回の調節信号の
変化分である。
In the above equation, K p : proportional gain, T
I : integration time, T D : derivative time, Δt: control cycle,
e n: this time of the deviation signal, e n-1: the last of the deviation signal, e
n-2 : previous and previous deviation signal, MV n : current adjustment signal, M
V n-1 : the previous adjustment signal, ΔMV n : the change amount of the current adjustment signal.

【0007】しかし、以上のようにして得られた位置形
PID調節信号MVn は通常0〜100%であるので、
減算手段16にて50%で減じて信号範囲を、−50〜
0〜+50%の信号とした後、上下限制限手段17で所
定の上限制限値+δ、下限制限値−δで制限した後、後
続の加算手段18に導き、ここでFF制御系の基本操作
量K・SVn をFB制御系の出力で修正して負荷配分指
令信号とし、この負荷配分指令信号を対応するボイラ2
1 に供給するものである。
However, since the position type PID control signal MV n obtained as described above is usually 0 to 100%,
The signal range is reduced by 50% by the subtracting means 16 to be -50 to
After a signal of 0 to + 50%, the upper and lower limit limiter 17 limits the signal with a predetermined upper limit limit value + δ and a lower limit limit value -δ, and then guides it to a subsequent adding unit 18, where the basic operation amount of the FF control system is set. K · SV n is corrected by the output of the FB control system to form a load distribution command signal, and this load distribution command signal is used by the corresponding boiler 2
And supplies to 1.

【0008】[0008]

【発明が解決しようとする課題】しかしながら、以上の
ような目標値FF/FB制御装置では次のような問題点
が指摘されている。
However, the following problems have been pointed out in the above-mentioned target value FF / FB control device.

【0009】(1) 目標値SVn を変化させた時、目
標値FF制御成分とPID制御成分とが重畳するので、
PID制御成分のみでも目標値追従特性が振動的となる
のに対し、さらにFF制御ゲインにPD,つまり比例ゲ
インおよび微分ゲインも加わるので高ゲインとなり、制
御性を悪化させる問題がある。
(1) Since the target value FF control component and the PID control component are superposed when the target value SV n is changed,
While the target value tracking characteristic is oscillating even with only the PID control component, PD is also added to the FF control gain, that is, the proportional gain and the differential gain, so that the gain becomes high and the controllability deteriorates.

【0010】(2) 位置形PID調節信号MVn が上
下限制限手段17に引っかかり、かつ、偏差en が残っ
た状態のとき、PID調節演算手段14の積分動作が継
続し続けるので、ある時点で偏差en が逆方向に動いた
とき、上下限制限手段17の例えば上限値に相当する操
作信号を出力し続け、この操作信号が元に戻るのに時間
がかかり,いわゆるリセットワインドアップの問題が生
じ、この点でも制御性が著しく悪化する。 (3) 目標値FF制御とFB制御とが位置形信号で結
合されているので、ゲイン適応形などの高度化に不適当
である。
(2) When the position-type PID adjustment signal MV n is caught by the upper and lower limit limiting means 17 and the deviation e n remains, the integration operation of the PID adjustment calculating means 14 continues to continue at a certain point. When the deviation e n moves in the opposite direction, the operation signal corresponding to, for example, the upper limit value of the upper and lower limit limiting means 17 is continuously output, and it takes time for the operation signal to return to the original state, which is a so-called reset windup problem. Occurs, and controllability also deteriorates significantly in this respect. (3) Since the target value FF control and the FB control are connected by the position type signal, it is unsuitable for sophistication such as gain adaptive type.

【0011】(4) さらに、前述と同様に目標値FF
制御とFB制御とが位置形信号で結合されているので、
自動−手動切換え時にスムーズに移行する,いわゆるバ
ランスレス・バンプレス化の処理が複雑である。
(4) Further, similarly to the above, the target value FF
Since the control and the FB control are combined by the position type signal,
The so-called balanceless bumpless process, which is a smooth transition during automatic-manual switching, is complicated.

【0012】本発明は上記実情に鑑みてなされたもの
で、目標値の変化に対してFB制御の2自由度化により
最適な制御性を確保し、積分動作によって調節信号が拡
大方向にあるとき積分動作を停止し、或いは積分動作に
よって調節信号が解消する方向にあるとき積分動作を実
行することによりリセットワインドアップを防止し、さ
らにFB制御成分とFF制御成分とをそれぞれ速度形調
節演算を実行した後に結合することにより高度化および
切換え時のバランスレスバンプレス化に十分対処しうる
目標値FF/FB制御装置を提供することを目的とす
る。
The present invention has been made in view of the above situation. When the FB control has two degrees of freedom with respect to the change of the target value, the optimum controllability is secured, and when the adjusting signal is in the expanding direction by the integral operation. Reset windup is prevented by stopping the integration operation, or by executing the integration operation when the adjustment signal is in the direction where the adjustment signal is canceled by the integration operation, and further executes the velocity type adjustment calculation for the FB control component and the FF control component, respectively. It is an object of the present invention to provide a target value FF / FB controller capable of sufficiently coping with advancement and balanceless bumplessness at the time of switching by combining them after the above.

【0013】[0013]

【課題を解決するための手段】請求項1に対応する発明
は上記課題を解決するために、目標値SVn の変化に対
して速応出力するための目標値FF(フィードフォワー
ド)制御部と、前記目標値SVn と制御対象からの制御
量PVn とに基づいて調節演算を実行して得られる調節
演算信号を用いて目標値FF制御部の出力を修正制御す
るFB(フィードバック)制御部とを組合せた目標値F
F/FB制御装置において、
In order to solve the above-mentioned problems, the invention corresponding to claim 1 includes a target value FF (feedforward) control unit for outputting a quick response to a change in the target value SV n. , An FB (feedback) control unit for correcting and controlling the output of the target value FF control unit using an adjustment calculation signal obtained by executing an adjustment calculation based on the target value SV n and the control amount PV n from the controlled object Target value F combining and
In the F / FB controller,

【0014】前記FB制御部として、FB制御としての
P(比例)動作の最適2自由度化係数をα0 、P動作の
比例ゲインをKp 、目標値FF制御のゲインをKとした
とき、少くともP動作の2自由度化係数α(=α0 −K
/Kp )をもつ目標値フィルタ手段、この目標値フィル
タ手段からの演算目標値SVn ′と前記制御量PVn
の偏差に基づいて調節演算を行う,少くともI(積分)
調節演算を分離した速度形PIまたは速度形PID
(D:微分)調節演算手段、前記I調節演算手段の出力
側に設けられたスイッチ手段、前記速度形PIまたは速
度形PID調節演算手段によって得られた速度形PIま
たはPID調節演算信号を加算合成する合成手段を有
し、
As the FB control unit, when the optimum two-degree-of-freedom coefficient of P (proportional) operation as FB control is α 0 , the proportional gain of P operation is K p , and the gain of target value FF control is K, At least P-motion two-degree-of-freedom coefficient α (= α 0 -K
/ K p ), the adjustment calculation is performed based on the deviation between the calculated target value SV n ′ from the target value filter means and the control amount PV n , at least I (integration)
Speed type PI or speed type PID with separate adjustment calculation
(D: differential) adjustment calculation means, switch means provided on the output side of the I adjustment calculation means, speed PI or PID adjustment calculation signals obtained by the speed PI or speed PID adjustment calculation means are added and synthesized. Have a synthesizing means to

【0015】さらに、この合成手段から得られた速度形
PIまたはPID調節演算信号と前記FF制御部のFF
制御信号FFn (=SVn ・K)の差分演算によって得
られる速度形FF制御信号△FFn とを加算した後、位
置形FF/FB調節信号に変換する信号変換手段と、こ
の信号変換手段からの位置形FF/FB調節信号を上下
限制限値で制限して操作信号を出力する上下限制限手段
と、
Further, the velocity type PI or PID adjustment calculation signal obtained from the synthesizing means and the FF of the FF control section.
A signal conversion means for adding a speed type FF control signal ΔFF n obtained by a difference calculation of the control signal FF n (= SV n · K) and then converting it to a position type FF / FB adjustment signal, and this signal conversion means. Upper and lower limit limiting means for limiting the position type FF / FB adjustment signal from the above with an upper and lower limit limiting value and outputting an operation signal,

【0016】この上下限制限手段の入出力差の信号に基
づいて位置形FF/FB調節信号が上下限制限値を越え
たことを判定する上下限制限値逸脱判定手段、この判定
手段の出力△Ln-1 と前記I調節演算手段の出力△In
とが同符号であるとき積分動作によって前記調節信号が
拡大方向にあると判断して前記スイッチ手段をオフし積
分動作を停止する同符号判定手段を有する積分動作制御
手段とを設けた目標値FF/FB制御装置である。
An upper / lower limit limit deviation determining means for determining that the position type FF / FB adjustment signal exceeds the upper / lower limit limiting value based on the input / output difference signal of the upper / lower limit limiting means, and an output Δ of this determining means. L n-1 and the output ΔI n of the I adjustment calculation means
And the same sign, a target value FF provided with integration operation control means having the same sign determination means for judging that the adjustment signal is in the expanding direction by the integration operation and turning off the switch means to stop the integration operation. / FB controller.

【0017】次に、請求項2に対応する発明は、特に積
分動作制御手段として、前記上下限制限手段の入出力差
の信号に基づいて位置形FF/FB調節信号が上下限制
限値内にあるか否かを判定する操作信号判定手段と、こ
の操作信号判定手段の出力△Ln-1 と速度形I調節演算
手段の出力△In とがゼロまたは異符号であるとき積分
動作によって前記調節信号が解消する方向にあると判断
して前記スイッチ手段をオンして積分動作を実行するゼ
ロ・異符号判定手段とを設けたものであり、
Next, in the invention according to claim 2, the position type FF / FB adjustment signal is set within the upper and lower limit limit values based on the input / output difference signal of the upper and lower limit limit means, particularly as integral operation control means. whether the determining operation signal determining means whether there, said by the integral operation when the output △ I n the output △ L n-1 and the velocity-type I regulating operation means of the operation signal determination unit is zero or opposite sign And a zero / different sign determining means for executing the integration operation by turning on the switch means when it is determined that the adjustment signal is in the direction of canceling,

【0018】さらに、請求項3に対応する発明は、同じ
く積分動作制御手段に関し、前記上下限制限手段の入出
力差の信号に基づいて位置形FF/FB調節信号が上下
限制限値を越えたことを判定する上下限制限値逸脱判定
手段と、この判定手段の出力△Ln-1 ,速度形FF制御
信号△FFn ,前記P調節演算手段の出力△Pn または
前記PD調節演算手段の出力△PDn の加算値と前記I
調節演算手段の出力△In とが同符号であるとき積分動
作によって前記調節信号が拡大方向にあると判断して前
記スイッチ手段をオフし積分動作を停止する同符号判定
手段とを設けた構成である。
Further, the invention corresponding to claim 3 relates to the integral operation control means, wherein the position type FF / FB adjustment signal exceeds the upper and lower limit values based on the input / output difference signal of the upper and lower limit means. Of the upper and lower limit value deviation determination means for determining the above, the output ΔL n-1 of this determination means, the speed type FF control signal ΔFF n , the output ΔP n of the P adjustment calculation means or the PD adjustment calculation means. The added value of the output ΔPD n and the above I
When the output ΔI n of the adjustment calculation means has the same sign, it is judged by the integration operation that the adjustment signal is in the expanding direction, and the switch means is turned off to stop the integration operation. Is.

【0019】さらに、請求項4に対応する発明は、同様
に積分動作制御手段について、前記上下限制限手段の入
出力差の信号に基づいて位置形FF/FB調節信号が上
下限制限値内にあるか否かを判定する操作信号判定手段
と、この操作信号判定手段の出力△Ln-1 ,速度形FF
制御信号△FFn ,前記P調節演算手段の出力△Pn
たは前記PD調節演算手段の出力△PDn の加算値と前
記I調節演算手段の出力△In とがゼロまたは異符号で
あるとき積分動作によって前記調節信号が解消する方向
にあると判断して前記スイッチ手段をオンして積分動作
を実行するゼロ・異符号判定手段とを設けた構成であ
る。
Further, in the invention corresponding to claim 4, similarly, in the integral operation control means, the position type FF / FB adjustment signal is within the upper and lower limit values based on the input / output difference signal of the upper and lower limit limiting means. Operation signal determination means for determining whether or not there is an output ΔL n-1 of the operation signal determination means, speed type FF
Control signal △ FF n, when the output △ I n the sum of the output △ PD n of the output △ P n or the PD adjusting operation means of the P regulation computation means and said I regulatory calculation means is zero or opposite sign This is a configuration provided with zero / different sign determination means for determining that the adjustment signal is in a direction to be canceled by the integration operation and turning on the switch means to execute the integration operation.

【0020】[0020]

【作用】従って、請求項1,3に対応する発明は以上の
ような手段を講じたことにより、速度形PIまたはPI
DのFB制御部に、P動作の最適2自由度化係数を
α0、P動作の比例ゲインをKp 、目標値FF制御のゲ
インをKとしたとき、少くともP動作の2自由度化係数
α(=α0 −K/Kp )をもつ目標値フィルタ手段を設
けたことにより、目標値の変化に対する制御性と制御量
の変化に対する制御性とをそれぞ独立的に調整でき、最
適な制御性を得ることができる。また、上下限制限値逸
脱判定手段において上下限制限手段の入出力差の信号が
ゼロ以外の信号のときには位置形FF/FB調節信号が
上下限制限手段の上下限制限値を越えていると判定で
き、しかも上下限制限値逸脱判定手段で得られた信号ま
たは当該判定手段の出力信号,速度形P調節演算信号お
よび速度形FF制御信号の加算信号と、速度形I調節演
算手段の出力信号とが同符号の場合には積分動作によっ
て速度形FF/FB調節信号が上下限制限値より益々拡
大する方向に作用しているので、このときにはスイッチ
手段をオフして積分動作を停止すれば、積分動作のリセ
ットワインドアップを防止できる。さらに、FB制御お
よびFF制御とも速度形演算を行って結合しているの
で、既に前回までの調節信号が信号変換手段に確保され
ており、この調節信号に今回値の調節信号を加算すれば
よいので、外部信号の組合わせやゲイン修正が容易に行
え、しかも自動−手動切換え時にバランスレスバンプレ
ス化を実現することができる。
Therefore, in the invention corresponding to claims 1 and 3, the speed type PI or PI is obtained by taking the above means.
In the FB control unit of D, when the optimum two-degree-of-freedom coefficient for P operation is α 0 , the proportional gain for P operation is K p , and the gain for the target value FF control is K, at least two degrees of freedom for P operation are provided. By providing the target value filter means having the coefficient α (= α 0 −K / K p ), the controllability with respect to the change of the target value and the controllability with respect to the change of the control amount can be independently adjusted, which is optimum. It is possible to obtain excellent controllability. Further, when the input / output difference signal of the upper / lower limit limiting means is a signal other than zero in the upper / lower limit limit deviation determining means, it is determined that the position type FF / FB adjustment signal exceeds the upper / lower limit limiting value of the upper / lower limit limiting means. A signal obtained by the upper / lower limit limit deviation determining means or an output signal of the determining means, an addition signal of the speed type P adjustment calculation signal and the speed type FF control signal, and an output signal of the speed type I adjustment calculation means. , The speed type FF / FB adjustment signal acts in such a direction that the speed-type FF / FB adjustment signal further expands from the upper and lower limit values by the integration operation. Therefore, at this time, if the switch means is turned off to stop the integration operation, Operation reset windup can be prevented. Further, since the FB control and the FF control are also combined by performing the velocity type calculation, the adjustment signal up to the previous time has already been secured in the signal converting means, and the adjustment signal of the current value may be added to this adjustment signal. Therefore, it is possible to easily combine the external signals and correct the gain, and it is possible to realize the balanceless bumpless mode at the time of automatic-manual switching.

【0021】次に、請求項2,4に対応する発明は、操
作信号判定手段において前記上下限制限手段の入出力差
の信号がゼロのときには位置形FF/FB調節信号が上
下限制限手段の上下限制限値内にあると判定でき、しか
も操作信号判定手段で得られた信号または当該判定手段
の出力信号,速度形P調節演算信号および速度形FF制
御信号の加算信号と、速度形I調節演算手段の出力信号
とがゼロまたは異符号の場合には積分動作によって上下
限制限値をオーバーしている速度形FF/FB調節信号
が解消する方向にさようしているので、このときにはス
イッチ手段をオンして積分動作を実行する構成とすれ
ば、積分動作のリセットワインドアップを防止できる。
Next, in the invention according to claims 2 and 4, when the input / output difference signal of the upper / lower limit limiting means is zero in the operation signal judging means, the position type FF / FB adjustment signal is the upper / lower limit limiting means. It can be determined that the value is within the upper and lower limit values, and the signal obtained by the operation signal determination means or the output signal of the determination means, the addition signal of the speed type P adjustment calculation signal and the speed type FF control signal, and the speed type I adjustment are provided. When the output signal of the computing means is zero or of a different sign, the speed-type FF / FB adjustment signal exceeding the upper and lower limit values is canceled by the integration operation, so that the switching means is used at this time. With the configuration in which is turned on to execute the integration operation, reset windup of the integration operation can be prevented.

【0022】[0022]

【実施例】以下、本発明の実施例について図面を参照し
て説明する。先ず、請求項1に係わる発明の一実施例に
ついて図1を参照して説明する。
Embodiments of the present invention will be described below with reference to the drawings. First, an embodiment of the invention according to claim 1 will be described with reference to FIG.

【0023】この制御装置は、目標値SVn の変化に速
応出力する目標値FF制御部20と、FB制御の速度形
PI調節演算信号を用いて目標値FF制御成分を修正制
御する速度形2自由度PI制御部30とが設けられてい
る。
This control device uses a target value FF control unit 20 which outputs in response to changes in the target value SV n , and a speed type which corrects and controls the target value FF control component using a speed type PI adjustment calculation signal for FB control. A 2-degree-of-freedom PI control unit 30 is provided.

【0024】この目標値FF制御部20は、目標値SV
n にFF制御ゲインK(Kは1近傍の値とする)を乗算
してFF制御の静的補償分FFn =K・SVn を得る係
数手段21と、静的補償分の今回値FFn と静的補償分
の前回値FFn-1 との差分,つまり速度形FF制御信号
△FFn を取り出す差分演算手段22とで構成されてい
る。なお、この差分演算手段22によって求める速度形
FF制御信号△FFnは、 △FFn =FFn −FFn-1 =K・(SVn −SVn-1 )=K・△SVn で表せる。
The target value FF control unit 20 determines the target value SV
The coefficient means 21 for multiplying n by the FF control gain K (K is a value near 1) to obtain the static compensation amount FF n = K · SV n for the FF control, and the current value FF n of the static compensation amount. And a difference value from the previous value FF n-1 for static compensation, that is, a difference calculation means 22 for extracting the speed type FF control signal ΔFF n . Incidentally, the speed-type FF control signal △ FF n determined by the difference calculating means 22 can be expressed by △ FF n = FF n -FF n -1 = K · (SV n -SV n-1) = K · △ SV n ..

【0025】一方、速度形2自由度PI制御部30は、
目標値SVn を受けて少くともP動作を2自由度化する
目標値フィルタ手段31と、この目標値フィルタ手段3
1を経由して出力される演算目標値SVn ′と制御量P
n とから偏差en を求める偏差演算手段32と、この
偏差演算手段32からの偏差en を用いて下記(3)式
および(4)式に基づいて速度形P調節演算信号△Pn
および速度形I調節演算信号△In を得る速度形P調節
演算手段33および速度形I調節演算手段34とが設け
られている。 △Pn =Kp (en −en-1 ) ……(3) △In =Kp (△t/TI )en ……(4)
On the other hand, the velocity type two-degree-of-freedom PI control section 30 is
A target value filter means 31 for receiving the target value SV n and making the P motion at least two degrees of freedom, and the target value filter means 3
Calculation target value SV n ′ and control amount P output via 1
A deviation calculation means 32 and a V n a deviation e n, the following (3) using the deviation e n from the deviation calculating means 32 and Equation (4) speed type P regulating operation signal based on the equation △ P n
And speed type P adjustment calculation means 33 and speed type I adjustment calculation means 34 for obtaining the speed type I adjustment calculation signal ΔI n . △ P n = K p (e n -e n-1) ...... (3) △ I n = K p (△ t / T I) e n ...... (4)

【0026】また、この速度形2自由度PI制御部30
は、速度形I調節演算手段34の出力側にスイッチ手段
35を介して加算手段36が設けられ、この加算手段3
6にて常時は速度形P調節演算手段33の出力と速度形
I調節演算手段34の出力とを加算して速度形PI調節
演算信号を得、この速度形PI調節演算信号を後続の加
算手段37に送出する構成となっている。この加算手段
37は、前記差分演算手段22からの速度形FF制御信
号△FFn の他、速度形P調節演算手段33の出力信号
△Pn と速度形I調節演算手段34の出力信号△In
を加算合成し、この加算合成後の信号を速度形FF/F
B調節信号△MVn として出力する。41は速度形−位
置形信号変換手段であって、速度形FF/FB調節信号
△MVn を取り込んで下記の(5)式に基づき、 MVn =MVn-1 +△MVn =MVn-1 +△Pn +△In ′+△FFn ……(5) なる演算を行って位置形FF/FB調節信号MVn を求
めた後、上下限制限手段42に送出している。但し、上
式においてMVn :今回の位置形FF/FB調節信号、
MVn-1 :前回の位置形FF/FB制御信号である。
Further, the speed type two-degree-of-freedom PI control section 30
Is provided with an addition means 36 on the output side of the speed type I adjustment calculation means 34 via a switch means 35.
At 6, the output of the speed type P adjustment calculation means 33 and the output of the speed type I adjustment calculation means 34 are always added to obtain a speed type PI adjustment calculation signal, and this speed type PI adjustment calculation signal is added to the subsequent addition means. It is configured to send to 37. The addition means 37 outputs the speed type FF control signal ΔFF n from the difference calculation means 22, the output signal ΔP n of the speed type P adjustment calculation means 33 and the output signal ΔI of the speed type I adjustment calculation means 34. n and are added and synthesized, and the signal after this addition and synthesis is velocity type FF / F
It is output as a B adjustment signal ΔMV n . Reference numeral 41 denotes a velocity type-position type signal converting means, which takes in the velocity type FF / FB adjustment signal ΔMV n and based on the following equation (5): MV n = MV n-1 + ΔMV n = MV n −1 + ΔP n + ΔI n ′ + ΔFF n (5) The position-type FF / FB adjustment signal MV n is calculated and then sent to the upper and lower limit limiting means 42. However, in the above equation, MV n is the current position type FF / FB adjustment signal,
MV n-1 : Previous position type FF / FB control signal.

【0027】この上下限制限手段42は、位置形FF/
FB調節信号MVn に対し、上下限制限値設定手段43
からの上限制限値(K・SVn +δ)および下限制限値
(K・SVn −δ)を用いて制限しつつ操作信号M
n ′を取り出し、図示しない制御対象に印加する。こ
の上限制限値(K・SVn +δ)および下限制限値(K
・SVn −δ)は目標値FF制御の静的補償分FF
n (=K・SVn )に信号発生手段431からの所定の
値δを加減算することにより得られる。なお、上下限制
限手段42の機能は3個の入力信号の中間値を選択すれ
ばよい。
The upper and lower limit limiting means 42 is a position type FF /
Upper and lower limit value setting means 43 for the FB adjustment signal MV n
The operation signal M while limiting using the upper limit value (K · SV n + δ) and the lower limit value (K · SV n −δ) from
V n ′ is taken out and applied to a controlled object (not shown). The upper limit value (K · SV n + δ) and the lower limit value (K
・ SV n −δ) is the static compensation FF of the target value FF control
It is obtained by adding or subtracting a predetermined value δ from the signal generating means 431 to n (= K · SV n ). The function of the upper and lower limit limiting means 42 may be to select the intermediate value of the three input signals.

【0028】さらに、前記上下限制限手段42の入出力
端間には、位置形FF/FB制御信号MVn が上下限制
限値内にあるときゼロを出力し、上下限制限値を越えた
ときにゼロ以外の信号である上下限制限値逸脱信号△L
n-1 を出力する上下限制限値逸脱判定手段44が設けら
れ、この上下限制限値逸脱信号△Ln-1 は積分動作傾向
抽出手段45に送られる。この積分動作傾向抽出手段4
5は速度形I調節演算手段34の今回の出力信号△In
と上下限制限値逸脱判定手段44の上下限制限値逸脱信
号の前回値△Ln-1 とを乗算することにより時間的経過
に伴って変化する積分動作傾向信号を取り出す。同符号
判別手段46は△In ・△Ln-1 >0のとき△In と△
n-1 とが同符号であると判別し、この場合には積分動
作によって位置形FF/FB調節信号が上下限制限値を
越えて拡大する方向に動いていると判断し、スイッチ手
段35をオフとすることにより積分動作を停止するもの
である。従って、以上のような実施例のような構成によ
れば、従来の種々の問題点を解決することができる。
Further, between the input and output terminals of the upper and lower limit limiting means 42, zero is output when the position type FF / FB control signal MV n is within the upper and lower limit limits, and when the upper and lower limit limits are exceeded. High and low limit value deviation signal ΔL that is a signal other than zero
An upper / lower limit limit value deviation determining means 44 for outputting n−1 is provided, and the upper / lower limit limit value deviation signal ΔL n−1 is sent to the integration action tendency extracting means 45. This integration operation tendency extraction means 4
5 is the current output signal ΔI n of the speed type I adjustment calculation means 34.
By multiplying the previous value ΔL n-1 of the upper and lower limit value deviation signal of the upper and lower limit value deviation determining means 44, an integral action tendency signal that changes with the passage of time is extracted. Same sign discrimination means 46 when the △ I n · △ L n- 1> 0 △ and I n
It is determined that L n-1 has the same sign, and in this case, it is determined by the integration operation that the position type FF / FB adjustment signal is moving in the direction of expanding beyond the upper and lower limit values, and the switch means 35 By turning off, the integration operation is stopped. Therefore, according to the configuration of the above-described embodiment, various conventional problems can be solved.

【0029】先ず、目標値SVn を目標値フィルタ手段
31を経由して得られる演算目標値SVn ′と制御量P
n との偏差en に基づいてPI調節演算を実行し速度
形PI調節演算信号を得るが、このとき目標値フィルタ
手段31のP動作(比例ゲイン)における2自由度化係
数αをFF制御とFB制御に最適な値に設定し、目標値
FF制御と2自由度PI制御とを組み合わせているの
で、目標値追従特性と外乱抑制特性とを同時に最適な状
態に制御できる。因みに、目標値フィルタ手段31の伝
達関数H(s) は下記する(6)式で表すことができる。 H(s) =(1+αTI ・s )/(1+TI ・s ) ……(6)
First, the target value SV n is calculated through the target value filter means 31 and the calculated target value SV n ′ and the control amount P are obtained.
PI adjustment calculation is executed based on the deviation e n from V n to obtain a velocity-type PI adjustment calculation signal. At this time, the 2-degree-of-freedom coefficient α in the P operation (proportional gain) of the target value filter means 31 is FF controlled. Since the target value FF control and the two-degree-of-freedom PI control are combined with each other, the target value following characteristic and the disturbance suppressing characteristic can be simultaneously controlled to the optimum state. Incidentally, the transfer function H (s) of the target value filter means 31 can be expressed by the following equation (6). H (s) = (1 + αT I・ s) / (1 + T I・ s) …… (6)

【0030】但し、α:比例ゲインの2自由度化係数、
I :積分時間、s :ラプラス演算子である。ここで、
FB制御のみの場合の制御量PV→操作量MV間の伝達
関数をCPM(s) 、目標値SV→操作量MV間の伝達関数
をCSM(s) とすると、下記の(7)式および(8)式の
ようになる。 CPM(s) =MV/PV=Kp {1+1/(TI ・s )} ……(7) CSM(s) =MV/SV=Kp {α+1/(TI ・s )} ……(8)
Where α is a two-degree-of-freedom coefficient of proportional gain,
T I : integration time, s: Laplace operator. here,
When the transfer function between the controlled variable PV and the manipulated variable MV in the case of only the FB control is C PM (s) and the transfer function between the target value SV and the manipulated variable MV is C SM (s), the following equation (7) is obtained. And it becomes like Formula (8). C PM (s) = MV / PV = K p {1 + 1 / (T I · s)} (7) C SM (s) = MV / SV = K p {α + 1 / (T I · s)} ... … (8)

【0031】従って、目標値フィルタ手段31は(6)
式のような伝達関数H(s) をとるとき、上記(7)式お
よび(8)式に示すようなP動作のみ2自由度化となっ
ている。ここで、比例ゲインの2自由度化係数αを例え
ば下記の(9)式のように選定する。 α=α0 −K/Kp ……(9)
Therefore, the target value filter means 31 is (6)
When the transfer function H (s) like the expression is taken, only the P motion as shown in the expressions (7) and (8) has two degrees of freedom. Here, the two-degree-of-freedom coefficient α of the proportional gain is selected, for example, by the following equation (9). α = α 0 −K / K p (9)

【0032】但し、K:目標値FF制御ゲイン、Kp
比例ゲイン、α0 :FB制御のみの時の比例ゲインの最
適2自由度化係数(0.4近傍)、α:目標値FF制御
を組合わせた時の比例ゲインの最適2自由度化係数であ
る。
However, K: target value FF control gain, K p :
Proportional gain, α 0 : Optimal 2-DOF coefficient of proportional gain when only FB control (0.4 vicinity), α: Optimal 2-DOF coefficient of proportional gain when target value FF control is combined is there.

【0033】つまり、比例ゲインの2自由度化係数αを
(9)式のように選定すれば、目標値FF/FB制御に
おいて目標値変化に対する制御性と制御量変化に対する
制御性とを完全に独立的に調整でき、これにより最適な
制御性を得られ、従来装置の問題点(1)を解決でき
る。
That is, if the two-degree-of-freedom coefficient α of the proportional gain is selected as shown in the equation (9), the controllability with respect to the target value FF / FB control and the controllability with respect to the control amount change are completely achieved. It can be adjusted independently, and thereby optimal controllability can be obtained, and the problem (1) of the conventional device can be solved.

【0034】次に、速度形P調節演算手段33の出力△
n と速度形I調節演算手段34の出力△In と速度形
FF制御信号△FFn とを加算し、さらに信号変換手段
41で位置形FF/FB調節信号MVn に変換した後、
上下限制限手段42に導入するが、このときMVn が上
下限制限値内にあれば、上下限制限手段42の入出力値
は同じになり、よって上下限制限値逸脱判定手段44の
出力がゼロ,つまりMVn が上下限制限値を逸脱してい
ないと判定することができる。
Next, the output Δ of the speed type P adjustment calculation means 33
After P output of n and the velocity-type I regulating calculating means 34 △ adds the I n and the speed-type FF control signal △ FF n, and converted into a position type FF / FB adjustment signal MV n further signal conversion unit 41,
This is introduced into the upper and lower limit limiting means 42. At this time, if MV n is within the upper and lower limit limiting values, the input and output values of the upper and lower limit limiting means 42 become the same, so the output of the upper and lower limit limiting value deviation determining means 44 is It can be determined that zero, that is, MV n does not deviate from the upper and lower limit values.

【0035】しかし、MVn が上下限制限値を逸脱した
とき、上下限制限手段42の入出力値が異なり、上下限
制限値逸脱判定手段44からゼロ以外の信号△Ln-1
出力0し、これが積分動作傾向判断手段45に送られ
る。この積分動作傾向判断手段45には今回の速度形I
調節演算信号△In が入力されている。従って、この積
分動作傾向判断手段45では△Ln-1 と△In とを乗算
すれば、積分動作の傾向が分かる。つまり、出力△L
n-1 と△In とが同符号であれば、積分動作が同じ方向
に作用しており、位置形FF/FB調節信号が上下限制
限値を越えて拡大する方向にある。そこで、同符号判別
手段46では、△Ln-1 と△In が同符号であるか否か
について△Ln-1 ・△In >0により判別し、同符号の
ときスイッチ手段35をオフに設定し、積分動作を停止
する。ゆえに、従来装置の問題点(2)である積分動作
のリセットワインドアップを完全に防止できる。
However, when MV n deviates from the upper and lower limit limit values, the input and output values of the upper and lower limit limit means 42 differ, and the non-zero signal ΔL n-1 is output from the upper and lower limit limit deviation deciding means 44. Then, this is sent to the integration operation tendency determination means 45. This integral motion tendency judging means 45 is provided with the current speed type I.
The adjustment calculation signal ΔI n is input. Therefore, in this integration operation tendency judging means 45, the tendency of the integration operation can be known by multiplying ΔL n-1 by ΔI n . That is, the output ΔL
If n-1 and ΔI n have the same sign, the integration operation is acting in the same direction, and the position type FF / FB adjustment signal is in the direction of expanding beyond the upper and lower limit values. Therefore, the same sign discriminating means 46 discriminates whether or not ΔL n-1 and ΔI n have the same sign by ΔL n-1 · ΔI n > 0, and when they have the same sign, the switch means 35 is operated. Set to off and stop integration operation. Therefore, the reset windup of the integral operation, which is the problem (2) of the conventional device, can be completely prevented.

【0036】さらに、FF制御およびFB制御が共に完
全に速度形演算を行って組合わせているので、外部信号
との組合わせやゲイン修正などが簡単にでき、高度化へ
のアプローチが容易になり、しかも前回までの位置形操
作信号MVn-1 に今回値△MVn を加算する構成である
ので、従来装置の問題点(3),(4)である例えば自
動−手動切換え時のバランスレスバンプレス化を実現で
きる。
Further, since the FF control and the FB control are combined by completely performing the velocity type calculation, the combination with the external signal and the gain correction can be easily performed, and the approach to the sophistication becomes easy. Moreover, since the current value ΔMV n is added to the position type operation signal MV n-1 up to the previous time, there are problems (3) and (4) of the conventional apparatus, for example, balanceless during automatic-manual switching. Can be bumpless.

【0037】なお、上記実施例では、FF/FB調節信
号が上下限制限値に引かかっていることおよび△Ln-1
・△In >0のとき、当該FF/FB調節信号が上下限
制限値を拡大的方向でオーバ−していることを検出した
が、例えば△Ln-1 >0かつ△In >0または△Ln-1
<0かつ△In <0の論理和(OR)により検出しても
等価である。
In the above embodiment, the FF / FB adjustment signal is caught by the upper and lower limit values, and ΔL n-1.
When ΔI n > 0, it is detected that the FF / FB adjustment signal exceeds the upper and lower limit values in the expanding direction. For example, ΔL n-1 > 0 and ΔI n > 0. Or △ L n-1
It is equivalent if detected by a logical sum (OR) of <0 and ΔI n <0.

【0038】次に、請求項2に係わる発明の一実施例に
ついて図2を参照して説明する。すなわち、この制御装
置は、図1の積分動作の実行有無に関して全く逆の考え
に立つものである。つまり、積分動作の停止ではなく積
分動作を実行するための判断機能を設けたことにある。
Next, an embodiment of the invention according to claim 2 will be described with reference to FIG. That is, this control device has a completely opposite idea regarding whether or not to execute the integration operation of FIG. That is, the judgment function for executing the integration operation is provided instead of stopping the integration operation.

【0039】具体的には、速度形−位置形信号変換手段
41の位置形FF/FB調節信号MVn が上下限制限値
内にあるか否か,つまり上下限制限値内にあるときゼロ
を出力し、それ以外のときにゼロ以外の信号を出力する
操作信号判定手段51と、この操作信号判定手段51の
出力と速度形I調節演算手段34の出力とを乗算して積
分動作の傾向を見る積分動作傾向判断手段52と、この
積分動作傾向判断手段52の出力がゼロまたは異符号で
あるか否かを判別するゼロ・異符号判別手段53とを設
け、ゼロ時または異符号時に積分動作が縮小方向にある
と判断し、スイッチ手段54をオンに設定して積分動作
を実行するものである。
Specifically, it is determined whether or not the position type FF / FB adjustment signal MV n of the speed type / position type signal converting means 41 is within the upper and lower limit values, that is, when it is within the upper and lower limit values, zero is set. The operation signal determining means 51 that outputs a signal other than zero at other times and the output of the operation signal determining means 51 and the output of the speed type I adjustment calculating means 34 are multiplied to determine the tendency of the integration operation. The integration operation tendency determining means 52 to be viewed and the zero / different sign determining means 53 for determining whether the output of the integration operation tendency determining means 52 is zero or a different sign are provided, and the integration operation is performed at the time of zero or a different sign. Is determined to be in the reduction direction, the switch means 54 is turned on, and the integration operation is executed.

【0040】従って、この実施例の構成によれば、積分
動作傾向判断手段52の出力がゼロまたはマイナスであ
ること,つまり△Ln-1 ・△In ≦0(△Ln-1 と△I
n とが異符号または何れかがゼロ)であることを判別す
るゼロ・異符号判別手段53を設け、ここでゼロまたは
異符号であれば位置形FF/FB調節信号MVn が上下
限制限手段42の上下限制限値に引かかっていないか、
積分動作によって位置形FF/FB調節信号MVn が制
限値オーバーに対して解消する方向にあるので、スイッ
チ手段54をオンに設定して積分動作を実行する。その
結果、位置形FF/FB調節信号MVn が速やかに上下
限制限値内に入り、しかも積分動作が拡大方向にあると
き、かつ、スイッチ手段54をオフに設定しているの
で、積分動作のリセット・ワインドアップを完全に防止
できる。
Therefore, according to the construction of this embodiment, the output of the integration operation tendency judging means 52 is zero or minus, that is, ΔL n-1 · ΔI n ≤0 (ΔL n-1 and Δ I
A zero / different sign discriminating means 53 for discriminating that n is a different sign or one of them is zero, and if the sign is zero or a different sign, the position type FF / FB adjustment signal MV n is the upper and lower limit limiting means. Is the upper or lower limit value of 42 not caught?
Since the position-type FF / FB adjustment signal MV n is in a direction to be resolved against the limit value over by the integration operation, the switch means 54 is set to ON to execute the integration operation. As a result, the position type FF / FB adjustment signal MV n quickly enters the upper and lower limit values, and when the integration operation is in the expanding direction and the switch means 54 is set to OFF, the integration operation You can completely prevent reset windup.

【0041】勿論、本実施例では、図1と同様な構成の
目標値フイルタ手段31をもった速度形2自由度PI制
御部30を設けているので、図1と同様な効果を奏する
ものである。
Of course, in this embodiment, since the velocity type two-degree-of-freedom PI control unit 30 having the target value filter means 31 having the same structure as that of FIG. 1 is provided, the same effect as that of FIG. 1 can be obtained. is there.

【0042】なお、この実施例では、△Ln-1 ・△In
≦0で位置形FF/FB調節信号が上下限制限値内にあ
ることおよび積分動作による位置形FF/FB調節信号
が上下限制限値を解消する方向にあることを検出した
が、例えば△Ln-1 ≧0かつ△In <0または△Ln-1
≦0かつ△In >0の論理和で検出しても等価である。
In this embodiment, ΔL n-1 · ΔI n
When ≦ 0, it is detected that the position type FF / FB adjustment signal is within the upper and lower limit limit values and that the position type FF / FB adjustment signal due to the integration operation is in the direction of eliminating the upper and lower limit values. n-1 ≧ 0 and ΔI n <0 or ΔL n-1
It is equivalent even if it is detected by the logical sum of ≦ 0 and ΔI n > 0.

【0043】さらに、請求項3に係わる発明の一実施例
について図3を参照して説明する。この制御装置は、上
下限制限値逸脱判定手段44と積分動作傾向判断手段4
5との間に今回操作量算出手段61を設け、積分動作の
リセット・ワインドアップ防止機能の正確性を期するも
のである。つまり、図1では、前回操作量が制限に引か
かっていることおよび△Ln-1 と△In とが同符号の時
に積分動作を停止したのに対し、本実施例では△Ln-1
の代わりに前記今回操作量算出手段61にて△Ln-1
△Pn +△FFn の演算を行うことにより、今回操作量
が制限に引っかかっていたことおよび[△Ln-1 +△P
n +△FFn ]と△In とが同符号の時に積分動作を停
止する。
Further, an embodiment of the invention according to claim 3 will be described with reference to FIG. This control device includes upper and lower limit value deviation determining means 44 and integral operation tendency determining means 4.
5, the operation amount calculating means 61 is provided this time to ensure the accuracy of the reset / windup prevention function of the integration operation. That is, in FIG. 1, the integration operation is stopped when the previous manipulated variable has reached the limit and ΔL n-1 and ΔI n have the same sign, whereas in the present embodiment, ΔL n-1.
Instead of the above, the current manipulated variable calculating means 61 calculates ΔL n-1 +
By performing the calculation of ΔP n + ΔFF n , the operation amount was caught by the limit this time, and [ΔL n-1 + ΔP n
The integration operation is stopped when [ n + ΔFF n ] and ΔI n have the same sign.

【0044】なお、この実施例は、[△Ln-1 +△Pn
+△FFn ]・△In >0で位置形FF/FB調節信号
が上下限制限値を越えたことおよび積分動作による位置
形FF/FB調節信号が上下限制限値を越えて拡大する
方向にあることを検出したが、例えば[△Ln-1 +△P
n +△FFn ]>0かつ△In >0または[△Ln-1
△Pn +△FFn ]<0かつ△In <0の論理和で検出
しても等価である。
In this embodiment, [ΔL n-1 + ΔP n
+ ΔFF n ] · ΔI n > 0 and the position type FF / FB control signal exceeds the upper and lower limit limits, and the direction in which the position type FF / FB control signal due to the integral operation exceeds the upper and lower limit limits and expands However, for example, [ΔL n-1 + ΔP
n + ΔFF n ]> 0 and ΔI n > 0 or [ΔL n-1 +
Even if the logical sum of ΔP n + ΔFF n ] <0 and ΔI n <0 is detected, they are equivalent.

【0045】さらに、請求項4に係わる発明の一実施例
について図4を参照して説明する。この制御装置は、図
3の積分動作の実行有無に関して全く逆の考えに立つも
のである。つまり、積分動作の停止ではなく積分動作を
実行するための判断機能を設けたことにある。
Further, an embodiment of the invention according to claim 4 will be described with reference to FIG. This control device is based on the opposite idea as to whether or not to execute the integration operation of FIG. That is, the judgment function for executing the integration operation is provided instead of stopping the integration operation.

【0046】すなわち、この実施例は、操作信号判定手
段51と積分動作傾向判断手段52との間に今回操作量
算出手段71が設けられ、積分動作のリセット・ワイン
ドアップ防止機能の正確性を期することにある。つま
り、図2では、前回操作量が上下限制限値内にあること
および△Ln-1 と△In とが異符号の時に積分動作を実
行するのに対し、本実施例では△Ln-1 の代わりに前記
今回操作量算出手段61にて△Ln-1 +△Pn +△FF
n の演算を行うことにより、今回操作量が制限値内にあ
ることおよび[△Ln-1 +△Pn +△FFn ]と△In
とが異符号の時に積分動作を実行する機能をもってい
る。
That is, in this embodiment, the current manipulated variable calculation means 71 is provided between the operation signal determination means 51 and the integration operation tendency determination means 52, and the accuracy of the reset / windup prevention function of the integration operation is ensured. To do. That is, in FIG. 2, the integration operation is executed when the previous manipulated variable is within the upper and lower limit values and ΔL n-1 and ΔI n have different signs, whereas in the present embodiment, ΔL n is used. Instead of -1, the current manipulated variable calculating means 61 uses ΔL n-1 + ΔP n + ΔFF
By calculating n , the current manipulated variable is within the limit value, and [ΔL n-1 + ΔP n + ΔFF n ] and ΔI n
It has a function to execute the integration operation when and have different signs.

【0047】なお、この実施例では、[△Ln-1 +△P
n +△FFn ]・△In ≦0で操作出力が上下限制限値
内にあることおよび調節信号が上下限制限値をオーバし
ているとき積分動作が制限オーバ−値を解消する方向で
あることを検出しているが、例えば[△Ln-1 +△Pn
+△FFn ]≧0かつ△In <0または[△Ln-1 +△
n +△FFn ]≦0かつ△In >0の論理和で検出し
ても等価である。また、上記各請求項の実施例では速度
形2自由度PI制御について説明したが、速度形2自由
度PID制御についても同様に適用できるものである。
その他、本発明はその要旨を逸脱しない範囲で種々変形
して実施できる。
In this embodiment, [ΔL n-1 + ΔP
n + ΔFF n ] · ΔI n ≤0, the operation output is within the upper and lower limit limits, and when the control signal exceeds the upper and lower limit limits, the integral operation is in the direction of canceling the limit over-value. It is detected that there is, for example, [ΔL n-1 + ΔP n
+ ΔFF n ] ≧ 0 and ΔI n <0 or [ΔL n-1 + Δ
It is equivalent even if the logical sum of P n + ΔFF n ] ≦ 0 and ΔI n > 0 is detected. Further, although the speed type two degrees of freedom PI control is described in the embodiments of the above claims, the speed type two degrees of freedom PID control can be similarly applied.
Besides, the present invention can be variously modified and implemented without departing from the scope of the invention.

【0048】[0048]

【発明の効果】以上説明したように本発明によれば、次
のような種々の効果を奏する。
As described above, according to the present invention, the following various effects are exhibited.

【0049】請求項1,3の発明では、目標値FF制御
と2自由度PI制御とを組合わせることにより目標値お
よび制御量の変化に対する制御性を大幅に改善でき、し
かも位置形FF/FB調節信号がある制限値を越え、か
つ、積分動作が拡大方向にあるとき積分動作を停止する
ので確実にリセットワインドアップを防止できる。ま
た、ゲイン修正および自動−手動切換え時のバランスレ
スバンプレス化を容易に実現でき、高度化へのアプロー
チを容易に達成可能である。
According to the first and third aspects of the present invention, by combining the target value FF control and the two-degree-of-freedom PI control, the controllability with respect to changes in the target value and the control amount can be greatly improved, and further, the position type FF / FB When the adjustment signal exceeds a certain limit value and the integration operation is in the expanding direction, the integration operation is stopped, so that reset windup can be reliably prevented. In addition, it is possible to easily realize gainless correction and balanceless bumpless at the time of automatic-manual switching, and it is possible to easily achieve an advanced approach.

【0050】次に、請求項2,4の発明は、請求項1,
3の発明と同様に制御性を大幅に改善できるとともに、
ゲイン修正および自動−手動切換え時のバランスレスバ
ンプレス化を容易に実現でき、さらに位置形FF/FB
調節信号が制限値内にあり、かつ、積分動作が解消方向
にあるとき積分動作を実行するので、結果としてリセッ
トワインドアップを防止できる。
Next, the inventions of claims 2 and 4 relate to claims 1 and 2.
Similar to the invention of 3, the controllability can be greatly improved, and
Gain correction and balanceless bumpless operation at the time of automatic-manual switching can be easily realized. Furthermore, position type FF / FB
Since the integration operation is performed when the adjustment signal is within the limit value and the integration operation is in the canceling direction, the reset windup can be prevented as a result.

【図面の簡単な説明】[Brief description of drawings]

【図1】請求項1に係わる目標値FF/FB制御装置の
一実施例を示す構成図。
FIG. 1 is a configuration diagram showing an embodiment of a target value FF / FB control device according to claim 1.

【図2】請求項2に係わる目標値FF/FB制御装置の
一実施例を示す構成図。
FIG. 2 is a configuration diagram showing an embodiment of a target value FF / FB control device according to claim 2;

【図3】請求項3に係わる目標値FF/FB制御装置の
一実施例を示す構成図。
FIG. 3 is a configuration diagram showing an embodiment of a target value FF / FB control device according to claim 3;

【図4】請求項4に係わる目標値FF/FB制御装置の
一実施例を示す構成図。
FIG. 4 is a configuration diagram showing an embodiment of a target value FF / FB control device according to claim 4;

【図5】従来の一般的なボイラ負荷システムの概略構成
図。
FIG. 5 is a schematic configuration diagram of a conventional general boiler load system.

【図6】従来の目標値FF/FB制御装置の構成図。FIG. 6 is a block diagram of a conventional target value FF / FB control device.

【符号の説明】[Explanation of symbols]

20…目標値FF制御部、21…係数手段、22…差分
演算手段、30…速度形2自由度PIまたはPID制御
部、31…フィルタ手段、33…速度形P調節演算手
段、34…速度形I調節演算手段、35…スイッチ手
段、36,37…加算手段、41…信号変換手段、42
…上下限制限手段、43…上下限制限値設定手段、44
…上下限制限値逸脱手段、45,52…積分動作傾向抽
出手段、46…同符号判別手段、51…操作信号判定手
段、53…ゼロ・異符号判別手段、61,71…今回操
作量算出手段。
20 ... Target value FF control section, 21 ... Coefficient means, 22 ... Difference computing means, 30 ... Velocity type 2 degrees of freedom PI or PID control section, 31 ... Filtering means, 33 ... Velocity type P adjustment computing means, 34 ... Velocity type I adjustment calculation means, 35 ... switch means, 36, 37 ... addition means, 41 ... signal conversion means, 42
... upper and lower limit limiting means, 43 ... upper and lower limit limiting value setting means, 44
... upper / lower limit limit deviation means, 45, 52 ... integral action tendency extraction means, 46 ... same sign discrimination means, 51 ... operation signal determination means, 53 ... zero / different sign discrimination means, 61, 71 ... current operation amount calculation means ..

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 目標値SVn の変化に対して速応出力す
るための目標値FF(フィードフォワード)制御部と、
前記目標値SVn と制御対象からの制御量PVn とに基
づいて調節演算を実行して得られる調節演算信号を用い
て目標値FF制御部の出力を修正制御するFB(フィー
ドバック)制御部とを組合せた目標値FF/FB制御装
置において、 前記FB制御部として、FB制御としてのP(比例)動
作の最適2自由度化係数をα0 、P動作の比例ゲインを
p 、目標値FF制御のゲインをKとしたとき、少くと
もP動作の2自由度化係数α(=α0 −K/Kp )をも
つ目標値フィルタ手段、この目標値フィルタ手段からの
演算目標値SVn ′と前記制御量PVnとの偏差に基づ
いて調節演算を行う,少くともI(積分)調節演算を分
離した速度形PIまたは速度形PID(D:微分)調節
演算手段、前記I調節演算手段の出力側に設けられたス
イッチ手段、前記速度形PIまたは速度形PID調節演
算手段によって得られた速度形PIまたはPID調節演
算信号を加算合成する合成手段を有し、 さらに、この合成手段から得られた速度形PIまたはP
ID調節演算信号と前記FF制御部のFF制御信号FF
n (=SVn ・K)の差分演算によって得られる速度形
FF制御信号△FFn とを加算した後、位置形FF/F
B調節信号に変換する信号変換手段と、 この信号変換手段からの位置形FF/FB調節信号を上
下限制限値で制限して操作信号を出力する上下限制限手
段と、 この上下限制限手段の入出力差の信号に基づいて位置形
FF/FB調節信号が上下限制限値を越えたことを判定
する上下限制限値逸脱判定手段、この判定手段の出力△
n-1 と前記I調節演算手段の出力△In とが同符号で
あるとき積分動作によって前記調節信号が拡大方向にあ
ると判断して前記スイッチ手段をオフし積分動作を停止
する同符号判定手段を有する積分動作制御手段とを備え
たことを特徴とする目標値FF/FB制御装置。
1. A target value FF (feedforward) control unit for outputting a quick response to a change in the target value SV n ,
An FB (feedback) control unit that corrects and controls the output of the target value FF control unit using an adjustment calculation signal obtained by performing an adjustment calculation based on the target value SV n and the control amount PV n from the controlled object. In the target value FF / FB control device, the optimum two-degree-of-freedom coefficient of P (proportional) operation as FB control is α 0 , the proportional gain of P operation is K p , and the target value FF as the FB control unit. When the control gain is K, a target value filter means having at least a two-degree-of-freedom coefficient α (= α 0 −K / K p ) for P operation, and a calculation target value SV n ′ from this target value filter means. Of the speed type PI or the speed type PID (D: differential) adjusting calculation means, which separates at least the I (integral) adjusting calculation, and performs the adjusting calculation based on the deviation between the control amount PV n and the control amount PV n . Switch hand provided on the output side The speed type PI or the speed type PID adjusting arithmetic means, and the speed type PI or PID adjusting arithmetic signal, and the speed type PI or P obtained from the synthesizing means.
ID adjustment calculation signal and FF control signal FF of the FF controller
After adding the speed type FF control signal ΔFF n obtained by the difference calculation of n (= SV n · K), the position type FF / F
A signal converting means for converting into a B adjusting signal, an upper and lower limit limiting means for limiting the position type FF / FB adjusting signal from the signal converting means with an upper and lower limit limiting value, and outputting an operation signal, and an upper and lower limit limiting means. Upper / lower limit limit deviation determination means for determining that the position type FF / FB adjustment signal exceeds the upper / lower limit limit value based on the input / output difference signal, and the output Δ of this determination means
When L n-1 and the output ΔI n of the I adjustment calculation means have the same sign, the integration operation determines that the adjustment signal is in the expanding direction and the switch means is turned off to stop the integration operation. A target value FF / FB control device comprising: integral operation control means having a determination means.
【請求項2】 請求項1において積分動作制御手段は、
前記上下限制限手段の入出力差の信号に基づいて位置形
FF/FB調節信号が上下限制限値内にあるか否かを判
定する調節信号判定手段と、この調節信号判定手段の出
力△Ln-1 と速度形I調節演算手段の出力△In とがゼ
ロまたは異符号であるとき積分動作によって前記調節信
号が解消する方向にあると判断して前記スイッチ手段を
オンして積分動作を実行するゼロ・異符号判定手段とを
有することを特徴とする目標値FF/FB制御装置。
2. The integral operation control means according to claim 1,
An adjustment signal determination means for determining whether or not the position type FF / FB adjustment signal is within the upper / lower limit limit value based on the input / output difference signal of the upper / lower limit limitation means, and an output ΔL of the adjustment signal determination means. When n-1 and the output ΔI n of the speed type I adjustment calculation means are zero or have different signs, it is judged that the adjustment signal is in the direction to be canceled by the integration operation, and the switch means is turned on to perform the integration operation. A target value FF / FB control device having a zero / different sign determining means for executing.
【請求項3】 請求項1において積分動作制御手段は、
前記上下限制限手段の入出力差の信号に基づいて位置形
FF/FB調節信号が上下限制限値を越えたことを判定
する上下限制限値逸脱判定手段と、この判定手段の出力
△Ln-1 ,速度形FF制御信号△FFn ,前記P調節演
算手段の出力△Pn または前記PD調節演算手段の出力
△PDn の加算値と前記I調節演算手段の出力△In
が同符号であるとき積分動作によって前記調節信号が拡
大方向にあると判断して前記スイッチ手段をオフし積分
動作を停止する同符号判定手段とを有することを特徴と
する目標値FF/FB制御装置。
3. The integral operation control means according to claim 1,
An upper / lower limit limit deviation determining means for determining that the position type FF / FB adjustment signal exceeds the upper / lower limit limiting value based on the input / output difference signal of the upper / lower limit limiting means, and an output ΔL n of this determining means. -1, velocity type FF control signal △ FF n, and an output △ I n the sum of the output △ PD n of the output △ P n or the PD adjusting operation means of the P regulation computation means and said I regulatory computing means the Target value FF / FB control device, which has the same sign determining means for judging that the adjustment signal is in the expanding direction by the integration operation when it is a sign and turning off the switch means to stop the integration operation.
【請求項4】 請求項1において積分動作制御手段は、
前記上下限制限手段の入出力差の信号に基づいて位置形
FF/FB調節信号が上下限制限値内にあるか否かを判
定する操作信号判定手段と、この操作信号判定手段の出
力△Ln-1 ,速度形FF制御信号△FFn ,前記P調節
演算手段の出力△Pn または前記PD調節演算手段の出
力△PDn の加算値と前記I調節演算手段の出力△In
とがゼロまたは異符号であるとき積分動作によって前記
調節信号が解消する方向にあると判断して前記スイッチ
手段をオンして積分動作を実行するゼロ・異符号判定手
段とを有することを特徴とする目標値FF/FB制御装
置。
4. The integral operation control means according to claim 1,
An operation signal determination means for determining whether or not the position type FF / FB adjustment signal is within the upper / lower limit limit value based on the input / output difference signal of the upper / lower limit limitation means, and an output ΔL of this operation signal determination means. n-1, velocity type FF control signal △ FF n, the output of the I regulatory calculating means and the sum of the output △ PD n of the output △ P n or the PD adjusting operation means of the P regulation computation means △ I n
When and are zero or different signs, it has a zero / different sign judging means for judging that the adjustment signal is in a direction to be canceled by the integration operation and turning on the switch means to execute the integration operation. Target value FF / FB control device to perform.
JP4124837A 1992-05-18 1992-05-18 Target value FF / FB control device Expired - Lifetime JP2994135B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4124837A JP2994135B2 (en) 1992-05-18 1992-05-18 Target value FF / FB control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4124837A JP2994135B2 (en) 1992-05-18 1992-05-18 Target value FF / FB control device

Publications (2)

Publication Number Publication Date
JPH05324005A true JPH05324005A (en) 1993-12-07
JP2994135B2 JP2994135B2 (en) 1999-12-27

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP4124837A Expired - Lifetime JP2994135B2 (en) 1992-05-18 1992-05-18 Target value FF / FB control device

Country Status (1)

Country Link
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014013461A (en) * 2012-07-03 2014-01-23 Horiba Ltd Pressure control device, flow rate control device, program for pressure control device and program for flow rate control device
JP2014059600A (en) * 2012-09-14 2014-04-03 Toshiba Corp Process controller

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014013461A (en) * 2012-07-03 2014-01-23 Horiba Ltd Pressure control device, flow rate control device, program for pressure control device and program for flow rate control device
JP2014059600A (en) * 2012-09-14 2014-04-03 Toshiba Corp Process controller

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