JPH053209A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To eliminated crystal defects and reduce leakage current of a transistor array by making its side walls crescent-shaped or U-shaped. CONSTITUTION:A silicon substrate 1 includes a LOCOS 2 for isolation. Heavily ion-implanted region 6 for source and drain are formed on the surface area of the substrate surrounded by the LOCOS 2. Lightly doped regions 5 are formed on these ends of the regions 6 that are opposed. A gate electrode 4 is formed on a gate oxide 3 that is located on the substrate between the source and drain. The semiconductor device thus fabricated has side walls 7 that are crescent- shaped or U-shaped.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method.

[0002]

2. Description of the Related Art Regarding a conventional method for manufacturing a semiconductor device,
This will be described with reference to FIGS.

First, an element isolation film 12 is formed on a semiconductor substrate 11 by a local oxidation method (LOCOS) using a silicon nitride film. After that, the insulating film 13 is formed by the surface oxidation method or the vapor phase growth (CVD) method (FIG. 16).

Further, a metal film 14a is formed on the entire surface by a sputter deposition method or a CVD method to form an electrode of the MOS transistor. Then, to form the pattern,
A resist is applied and a resist pattern 20 is formed by a lithography method (FIG. 17).

Further, the gate 14 is formed by patterning the metal film 14a by a dry etching method or the like. Next, the low concentration impurity ions 15a are implanted by the ion implantation method to form the low concentration impurity ion implantation region 15b. (FIG. 18).

Next, the low-concentration diffusion layer 15 is formed by annealing the low-concentration injection layer 15b to be in an electrically activated state. After this, the source and drain of the MOS transistor are LDD (lightly doped drai).
n) To form the structure, an insulating film 17a is formed on the semiconductor substrate 11 including the gate 14 and its sidewalls and the element isolation film 12 (FIG. 19).

Then, the insulating film 17a is etched by a dry etching method having a strong anisotropy by a thickness of about the film thickness of the flat portion. As a result, sidewalls 17 having a convex surface are formed along the corners between the sidewalls of the gate 14 and the semiconductor substrate 11. After this,
High-concentration impurity ions 16a are formed in the semiconductor substrate 11 by ion implantation using the gate 14 and the sidewall 17 as a mask.
Is introduced to form a high-concentration impurity ion implantation region 16b (FIG. 20).

Then, annealing is performed to recrystallize the amorphous layer in the high-concentration impurity ion-implanted region 16b to activate the impurities and form the high-concentration impurity diffusion layer 16 (FIG. 21).

Next, on the gate 14 and the element isolation film 12
Further, the insulating film 18 including the sidewalls 17 is formed on the semiconductor substrate 11 by the sputter deposition method or the CVD method. Further, a resist pattern for forming a contact is formed on the insulating film 18 using a lithography method, and a contact is formed on the semiconductor substrate 11 and the gate 14 by a dry etching method having a strong anisotropy. Further, a metal film such as aluminum for forming an external electrode via a contact is formed by a sputtering method or a CVD method, and a resist pattern is formed by using a lithography method, and then a source electrode is formed by an anisotropic dry etching method. 19c, the drain electrode 19a, and the gate electrode 19b are formed to manufacture a semiconductor device (FIG. 22).

The M of the LDD structure thus formed
In the OS transistor, as the device is miniaturized, adjacent constituent elements must be closer to each other, and the impurity diffusion layer must be formed shallower. In addition, the effect of stress due to various films that make up the device cannot be ignored. The films used in the device have different stresses, and therefore, the stress applied to the entire device is set to a value in an appropriate range.

However, when not only the stress of each film directly acts on the semiconductor substrate in the film forming process but also when the film is patterned and used, the magnitude of the stress depends on the shape of the formed pattern. Is different. In particular, a phenomenon in which a large stress is concentrated on the pattern edge portion and the film peels off occurs. Further, the stress concentrated on the pattern edge causes pattern edge defects 20 in the crystal in the semiconductor substrate 11 as shown in FIG. 14 by the annealing performed after the impurity ion implantation. The pattern edge defect 20 is generated when the stress generated in the contact portion between the sidewall 17 and the semiconductor substrate 11 directly acts on the semiconductor substrate 11. Particularly, stress concentrates on the edge 21 of the sidewall 17, and the edge 21 and the semiconductor substrate 1
Since a large force is applied to the portion in contact with 1, the pattern edge defect 20 is induced. The edge 21 of the sidewall 17 that causes the pattern edge defect 20 is located on the surface of the impurity diffusion layers 15 and 16, and the impurity diffusion layers 15 and 16 are shallowly formed. The edge defect 20 causes the device characteristics to significantly deteriorate.

In the annealing process for recrystallization after implanting the impurity ions, the difference in the recrystallization rate at the bottom of the region into which the impurity ions are implanted and the recrystallization rate from the sidewall causes the pattern It is speculated that the edge defect 20 may occur and the stress of the insulating film 17a at the pattern edge may accelerate the growth of the defect. The pattern edge defect 20 is formed on the semiconductor substrate 1 by implanting impurity ions.
This occurs remarkably in the case of implantation of high-concentration impurity ions such that 1 becomes amorphous.

Therefore, the insulating film 1 is formed after the impurity ions are implanted.
A method of etching 7a, moving the position of the pattern edge, and then annealing is disclosed in JP-A-11-11.
No. 7023 is proposed.

According to this method, when the impurity ion-implanted layer is recrystallized, the influence of the stress on the pattern edge is alleviated.

However, according to a study by the inventor, by simply changing the position of the pattern edge, the same crystal defect as in the case where the position is not changed is found in the edge portion of the impurity ion-implanted layer. It was found that the above stress cannot be sufficiently relaxed only by changing the position of the pattern edge.

[0016]

Then, when the cause of crystal defects was further investigated, it was revealed that the shape was significantly affected by the shape of the sidewall edge.

After implanting the impurity ions into the semiconductor substrate, an annealing process must be performed to electrically activate them. That is, when the impurity ions are implanted at a certain concentration or more, the impurity ion implantation region of the semiconductor substrate becomes amorphous. For example, the amount of ions implanted to form a source region and a drain region of a MOS transistor is sufficient to make it amorphous.

The amorphous layer formed by ion-implanting impurities into the patterned region is
Since the crystal planes of the bottom portion and the side wall portions are different, the recrystallization rate in the annealing step is different for each crystal plane. If there is a difference in recrystallization rate, a mismatch occurs on the crystal plane, and crystal defects are likely to occur.

Moreover, the membrane elements have different magnitudes of stress. Therefore, a large stress is concentrated on the pattern edge. The stress concentrated on this edge increases the mismatch of the recrystallized surface to create a crystal defect, which further deepens the pattern edge defect.

On the other hand, in order to increase the degree of integration in the semiconductor device or reduce the size thereof, the impurity diffusion layer has been formed shallower. There is a possibility that the impurity diffusion layer may be formed deeper than the impurity diffusion layer. for that reason,
In order to further miniaturize the constituent elements of the semiconductor device, it is a new subject to eliminate the factor of the characteristic deterioration or to make the influence of the factor negligible.

As a result of a detailed study of the measures for solving this problem, the inventor has found that the stress concentrated in the pattern edge portion is significantly affected by the shape of the film edge portion during patterning. I found it. The present invention is based on this finding.

[0022]

In order to solve the above problems, a semiconductor device according to the present invention comprises a semiconductor substrate, a source and a drain formed on the semiconductor substrate, and a side where the source and the drain face each other. Ion-implanted regions of lower concentration than the source / drain formed at the ends, a gate electrode formed on the silicon substrate between the source and the drain via a gate oxide film, and formed at both ends of the gate electrode And the side wall has a concave shape.

In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming a gate oxide film on a semiconductor substrate, a step of forming a gate electrode on the gate oxide film, and the gate. A step of implanting low-concentration impurity ions serving as a source and a drain using the electrode as a mask; a step of depositing a CVD-SiO ₂ film on the surface of the gate electrode and the surface of the semiconductor substrate by an atmospheric pressure CVD method; a step of anisotropically dry-etching the ₂ film, forming a high concentration impurity ion implantation region of the CVD-SiO ₂ film as a mask, the CVD-SiO
_And isotropically etching the _two films to form sidewalls having a concave shape.

In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming a gate oxide film on a semiconductor substrate, a step of forming a gate electrode on the gate oxide film, and the gate. A step of implanting low-concentration impurity ions serving as a source and a drain using the electrode as a mask; a step of depositing a CVD-SiO ₂ film on the surface of the gate electrode and the surface of the semiconductor substrate by an atmospheric pressure CVD method; a step of anisotropically dry-etching the ₂ film, forming a high concentration impurity ion implantation region of the CVD-SiO ₂ film as a mask, the CVD-SiO
₂ a step of isotropically etching the film to form a concave sidewall, a step of annealing the semiconductor substrate, a step of forming an interlayer film on the sidewall, the gate electrode, and the semiconductor substrate A step of forming a contact on the interlayer film and forming an external electrode.

[0025]

According to the means of the present invention, the side wall has a crescent shape or a concave shape, so that the generation of crystal defects can be eliminated. Further, when the side wall angle becomes 52 degrees or less, the side wall becomes a silicon substrate. The stress exerted on can be reduced.

Further, ion implantation for forming a source and a drain is performed on the convex side wall, whereby a mixed solution of hydrofluoric acid and ammonium fluoride (capacity ratio HF:
A concave surface can be etched with NH ₄ F = 1: 12).

Further, when performing etching for making the sidewalls concave, when forming the drain by etching so as to be located away from the tip portion where the convex sidewalls and the silicon substrate are in contact with each other. The occurrence of mismatch defects due to stress near the edge of the high-concentration impurity ion-implanted region is suppressed during the recrystallization of Al.

When the sidewalls are etched in a concave shape, ashing with O ₂ gas is performed to make the sidewall shape more concave.

By the above etching method, the sidewall can be formed in a concave shape with good reproducibility and stably.

In another method, the sidewall 7b can be etched in a concave shape by performing sputtering using an inert gas such as argon gas and then performing isotropic etching.

Further, by forming the sidewalls into a concave shape, when a transistor array having sidewalls is formed, the leakage current can be reduced by one digit or more as compared with the conventional transistor array.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor device of the present invention. A LOCOS 2 for element isolation is formed on the silicon substrate 1. Silicon substrate 1 sandwiched between LOCOS 2
A high-concentration impurity ion implantation region 6 to be a source / drain is formed on the surface of the. A lower concentration impurity ion implantation region 5 than the ion implantation region 6 is formed at a side end where the ion implantation region 6 faces each other. A structure having a relationship between the position of the source / drain diffusion layer and its concentration is called an LDD structure. The region having such two impurity concentrations is realized by forming sidewalls 7 formed at both ends of the gate electrode, as described later.
A gate electrode 4 is formed on the upper surface of the silicon substrate 1 between the source and the drain via a gate oxide film 3. Sidewalls 7 are formed on both ends of the gate electrode 4. In the semiconductor device of this embodiment, the side wall 7 has a crescent shape or a concave shape and is formed on both side surfaces of the gate electrode 4.

Further, the film thickness of the CVD-SiO ₂ film 7a is determined by how far the high-concentration impurity diffusion layer is formed from the edge of the gate electrode 4. At most, the thickness of the gate oxide film 3 and the gate electrode 4
The thickness may be about the sum of the film thickness of the polysilicon film.

The sidewall 7 is required to have a concave shape, which will be described in detail with reference to FIG. 12. The tangent to the concave surface at the point where the concave surface, which is the surface of the sidewall 7, contacts the silicon substrate 1, When the sidewall angle formed by the surface of the single crystal silicon substrate 1 is 52 degrees or less, the stress exerted by the sidewall 7 on the silicon substrate 1 is reduced, and when it is 42 degrees or less, it can be significantly reduced.

The mixed film of silane and N ₂ O forms an interlayer film 8 of CVD-SiO ₂ film at about 700 ° C. In this interlayer film 8, contacts for forming external electrodes of source, drain and gate electrodes are formed.

An aluminum film of a mixture of Al-Si-Cu is formed on the contact. This aluminum film is the source external electrode 9a, the gate external electrode 9b, and the drain external electrode 9c.

The contacts for forming the external electrodes are
Since the side wall 7 is concave, the contact edge is concave and is forward tapered.

As a result, the step coverage at the contact portion of the aluminum film formed by sputter deposition is improved. If the step coverage is good, disconnection does not occur at the contact portion of the aluminum film. Therefore, the step of isotropically etching the contact edge to form a concave surface and the step of burying the contact with polysilicon or a CVD-W film are unnecessary.

Furthermore, since the step coverage of the aluminum film is good, the film thickness of the aluminum film can be reduced. Therefore, after etching the aluminum film,
It is possible to prevent moisture from entering the aluminum film and corroding it. Therefore, the coverage of the passivation film, phosphosilicate glass (PSG), and the silicon nitride film by the plasma CVD method is also improved,
Increased passivation effect.

Next, an embodiment of the method for manufacturing a semiconductor device of the present invention will be described with reference to FIGS.

As shown in FIG. 2, the single crystal silicon substrate 1
Then, a nitride film having a film thickness of 160 nm is formed by a low pressure CVD apparatus. Here, the CVD condition of the nitride film is, for example, dichlorosilane (SiH ₂ Cl ₂ ) gas and NH ₃ gas at a temperature of about 800 ° C.

Further, a resist is applied on the nitride film. Next, exposure is performed using the mask of the element region for forming about 256 × 10 ³ transistor arrays, development is performed, and patterning is performed.

Then, the resist pattern is subjected to anisotropic etching by reactive ion etching (RIE) using a mixed gas of CF ₄ + O ₂ and CH ₃ Br for anisotropic etching of the nitride film. The portion of the silicon substrate 1 that is to be oxidized is exposed.

After that, the portion of the silicon substrate 1 exposed in the dry oxygen atmosphere at a temperature of about 1000 ° C. is oxidized to form a LOCOS 2 having a film thickness of about 500 nm. This L
The OCOS2 electrically isolates the individual transistors of the approximately 256 × 10 ³ transistor array.

After that, the nitride film is completely removed to expose the silicon substrate 1, and then the silicon substrate 1 is oxidized in a dry oxygen atmosphere to form a gate oxide film 3. At this time, the oxidation temperature is 900 ° C. and the film thickness is about 20 nm.

Next, as shown in FIG. 3, a polysilicon film 4a for forming a gate electrode is formed on the gate oxide film 3 by a low pressure CVD method. As the growth conditions, for example, silane (SiH ₄ ) gas is used to grow the film thickness of 250 nm at a temperature of about 610 ° C.

After that, heating is performed at a temperature of about 900 ° C. in a phosphine (PH ₃ ) gas atmosphere. As a result, the phosphine is thermally diffused in the polysilicon film 4a and reduces the sheet resistance of the polysilicon film 4a to about 10Ω.

After that, the resist 10 is applied and exposed, and the resist 10 is patterned so that the width of the transistor element becomes 800 nm.

Next, as shown in FIG. 4, the polysilicon film 4a is subjected to reactive ion etching (RIE) using a mixed gas of SF ₆ and Freon 115. At this time, the gate electrode 4 having an almost vertical sidewall is anisotropically etched along the pattern of the resist 10.

Next, in order to obtain an LDD-structure transistor, first, low-concentration impurity ion 5a is implanted into the source and drain to form a low-concentration impurity ion-implanted region 5b.
To form. The formation conditions at this time are that P ⁺ ions have an acceleration energy of about 30 keV and a dose of about 2 × 10 ¹³ cm ^-2.
To inject.

In the LDD structure, the source and the drain are formed of a low-concentration impurity diffusion layer and a high-concentration impurity diffusion layer, respectively. By forming the low-concentration diffusion layer near the gate and the high-concentration diffusion layer away from the gate, it is possible to reduce the influence of hot carriers caused by device miniaturization. Therefore, the ion implantation region 5
b is formed by implanting impurity ions at a relatively low acceleration voltage using the gate electrode 4 as a mask.

Next, as shown in FIG. 5, the temperature is about 900.degree.
Annealing is performed for 30 minutes in the nitrogen atmosphere.
By this annealing, the ion implantation region 5b forms the electrically active low concentration diffusion layer 5.

Further, a CVD-SiO ₂ film 7a having a thickness of about 300 nm is grown by the atmospheric pressure CVD method. The growth conditions are a mixed gas of silane and N ₂ O and a temperature of about 700.
Perform at ℃.

Here, the CVD-SiO ₂ film 7a is a film for forming a sidewall 7 described later. In forming the sidewall 7, the polysilicon film which is the gate electrode 4 is not adversely affected. further,
It is necessary to use a film having excellent adhesion to the gate electrode 4 and the silicon substrate 1. As the film satisfying this condition, the CVD-SiO ₂ film 7a is used in this embodiment.

Further, the film thickness of the CVD-SiO ₂ film 7a is determined by how far the high-concentration impurity diffusion layer is formed from the edge of the gate electrode 4. At most, the thickness of the gate oxide film 3 and the gate electrode 4
The thickness may be about the sum of the film thickness of the polysilicon film.

In this embodiment, the sum of the two is about 270 nm, while the thickness of the CVD-SiO ₂ film 7a is about 3 nm.
It was set to 00 nm.

Next, as shown in FIG. 6, CHF ₃ and O ₂
Using a mixed gas of the CVD-SiO ₂ film 7a is anisotropically dry etched to form a convex side walls 7b on the side walls of the gate electrode 4. The sidewall 7b thus formed by dry etching is formed so that the surface thereof is convex along the corner formed by the gate electrode 4 and the silicon substrate 1.

According to this process, the CVD-S is used in the embodiment.
The iO ₂ film 7a is etched by approximately the same thickness as that formed on the flat portion of the silicon substrate 1.

The etching amount at this time does not necessarily have to be the film thickness of the CVD-SiO ₂ film 7a on the flat portion of the substrate, and is formed on the flat portion of the silicon substrate 1. CVD-SiO ₂ film 7
It may be determined depending on the degree of variation in the film thickness of a, that there is no residue after etching, and how much the gap between the high-concentration impurity diffusion layer and the gate electrode to be formed in the subsequent step should be.

Further, in order to form a high-concentration impurity diffusion layer as a source and a drain, As ⁺ ions 6a are implanted with the acceleration energy of about 40 keV and the dose amount of about 4 × 10 ¹⁵ cm ^{-2 using the} sidewall 7b as a mask. Then, the high-concentration impurity ion implantation region 6b is formed.

Next, after implanting a high concentration of impurity ions, a mixed liquid of hydrofluoric acid and ammonium fluoride (volume ratio HF:
NH ₄ F = 1: 12) at isotropically etching the side wall 7b.

At this time, high concentration of ions are implanted into the sidewall 7b. For this reason, the convex portion is largely damaged by the ions. As described above, the oxide film on the side wall 7b, which is heavily damaged, has a high etching rate during etching.

Therefore, as shown in FIG. 7, the sidewall 7b has a concave surface along the corner formed by the gate formed of the gate oxide film 3 and the gate electrode 4 of the polysilicon film and the silicon substrate 1. Is formed.

At this time, the position of the sidewall on the silicon substrate 1 is further changed to the high concentration impurity ion implantation region 6b.
Etching is performed so as to be located 50 nm away from the edge of.

By this etching, CVD-SiO ₂
The stress concentrated on the edge portion of the sidewall 7b is relaxed by the film 7a, and the occurrence of mismatch defects due to the stress near the edge of the high-concentration impurity ion implantation region is suppressed during recrystallization when forming the source and drain. .

Further, in the step of etching the side wall 7b in a concave shape, 100% of O ₂ gas is applied from the vertical direction.
After ashing for 10 minutes with W, CF ₄ +10
Even in the method of performing isotropic dry etching of the oxide film with% O ₂ , the shape of the side wall 7 becomes a concave shape similar to the method of performing wet etching.

The ashing with O ₂ gas for 100 W for 10 minutes not only damages the sidewall 7b by the implantation, but also damages it. Therefore, the etching rate at the time of isotropic dry etching becomes faster at the convex portion of the convex surface of the sidewall 7b before the implantation. In this way, the sidewall 7 can be stably formed in a concave shape with good reproducibility.

Another method is a method of performing sputtering using an inert gas such as argon gas and further performing isotropic etching.

This etching method will be described with reference to FIG. As shown in FIG. 10, a mixed gas of silane and N ₂ O is used at a temperature of about 700 ° C. on a side wall of a gate composed of a gate oxide film 52 and a gate electrode 53 made of a polysilicon film on a silicon substrate 51. A CVD-SiO ₂ film is formed using an atmospheric pressure CVD device, and this CVD-Si film is formed.
Sidewalls 54a are formed on the O ₂ film by a reactive dry etching method having a strong anisotropy. Further, in order to form a high concentration impurity diffusion layer as a source and a drain,
Using the sidewalls 54a as a mask, As ⁺ ions are implanted with an acceleration energy of about 40 keV and a dose of about 4 × 10 ¹⁵ cm ^-2 to form a high concentration disordered ion implantation region 55.

Next, as shown in FIG. 10, etching with argon ions 56 is performed by the RF sputtering method. Argon ions are vertically incident on the silicon substrate 51. At this time, the sputtering phenomenon caused by the inert gas ions such as argon ions has a relationship between the etching rate and the incident angle as shown in FIG.

In FIG. 11, the horizontal axis is the incident angle of ions,
When the etching rate is taken on the vertical axis, the incident angle becomes the fastest at about 45 degrees. A distribution that maximizes a predetermined angle of incidence is drawn between the two as shown in FIG. Therefore, when argon ions are incident at about 45 degrees, the etching rate is about five times faster than when they are incident vertically.

In the sputter etching rate of the sidewall 54a, the etching of the step portion progresses abnormally faster than that of the flat portion. The shape after etching is such that the edge angle between the silicon substrate 51 and the sidewall 54b is about 4
It becomes a shape with a taper of 5 degrees.

Next, with a gas of CF ₄ + 10% O ₂ ,
Isotropic dry etching is performed on the CVD-SiO ₂ film. At this time, as shown in FIG.
However, the surface is formed in a concave shape along the corner formed by the gate formed of the gate oxide film 52 and the gate electrode 53 of the polysilicon film and the silicon substrate 51. At this time, as described with reference to FIG. 7, the etching amount is such that the position of the edge of the sidewall 54 on the silicon substrate 51 is 50 from the edge of the high concentration impurity ion implantation region 55.
Etching is performed so as to be positioned at a distance of nm.

This sidewall etching step is the most important step for completing the present invention.
As described in detail below, the angle formed by the surface of the sidewall 7 and the surface of the silicon substrate 1 (sidewall angle σ)
It makes sense to keep the value within a predetermined range, and a method that can achieve it is shown here.

First, the sidewall angle σ will be described with reference to FIG. The numbers in the figure are exactly the same as those shown in FIG.

The sidewall 54 is formed on the surface of the silicon substrate 51 and the sidewalls of the gate oxide film 52 and the gate electrode 53.

The side wall angle σ is the side wall 54
The angle formed by the tangent to the concave surface at the point where the concave surface, which is the surface of the single crystal silicon substrate 51, contacts the surface of the single crystal silicon substrate 1.

Next, FIG. 13 shows the relationship between the sidewall angle σ and the stress. The horizontal axis represents the sidewall angle σ, and the vertical axis represents the principal stress exerted by the sidewall on the silicon substrate.

The principal stress increases as the sidewall angle increases. This indicates that the sidewall that is normally used has a convex shape, the sidewall angle defined here is close to 90 degrees, and the principal stress due to it is large.

That is, in a sidewall having a convex surface (σ = about 90 degrees) as shown in FIG. 6, the stress is 2 ×.
It is 10 ⁸ dynes / cm ² . As the sidewall angle becomes smaller, the stress becomes smaller. When the sidewall angle σ is 52 degrees or less, a decrease in stress is recognized, and
Below the frequency, it has decreased significantly.

From these, it can be seen that the main stress, which is the main factor of the defect caused by the formation of the sidewall 54, is remarkably reduced by making the surface shape of the sidewall 54 concave.

However, as described above, the stress of the sidewall 54 is concentrated near the edge of the sidewall 54 regardless of its surface shape. Therefore, a defect occurs when the shape of the edge portion of the sidewall 54 is simply changed. That is, the recrystallization anneal performed after the impurity ion implantation causes a mismatch in the crystal lattice of the contact portion between the sidewall 54 where the main stress is concentrated and the silicon substrate 1.

In order to reduce the occurrence of crystal defects, it is desirable to form the sidewall 54 at a position slightly apart from the high concentration impurity ion implantation region 55 and then anneal it.

Here, FIG. 14 shows a simulation result in which defects are eliminated when the sidewall is formed at a position away from the end portion of the gate electrode.

The horizontal axis of the thick line in the center of the figure is the silicon substrate. The rectangle in the upper right part of the figure is the gate electrode. The sidewall is shown on the right of the solid line on the stairs at the top of the figure. The side wall angle formed by the end of the side wall and the silicon substrate is α, and α is 6 in this simulation.
It is once. The magnitude of stress and its direction are indicated by arrows at the bottom of the figure. The longer the arrow, the greater the stress.

From this, it can be seen that the stress is particularly concentrated near the ends of the sidewalls and near the gate electrodes.

The stress in the middle of the sidewall is large because the arrow is long. However, its direction is parallel to the substrate and does not contribute to the generation of crystal defects.

When the sidewall has a convex shape in this manner, crystal defects are induced at the end where the sidewall and the substrate are in contact with each other. At this time, the direction of the stress substantially coincides with the sidewall angle of the sidewall. If the side wall angle is made closer to the parallel to the substrate, crystal defects will not occur even if the stress is large.

Therefore, defects are not generated in the silicon substrate by using the region where the end of the side wall at the time of formation is retreated by etching and the stress is reduced in this way.

In this case, the stress becomes even smaller as the distance between the two becomes wider. According to the experiment, the stress at the sidewall edge is sufficiently relaxed when the distance is about 50 nm.

Next, in order to bring the impurity ion-implanted region 6b into an electrically activated state, it is annealed in a nitrogen atmosphere at a temperature of about 900 ° C. for about 30 minutes, and as shown in FIG. The diffusion layer 6 is formed.

[0093] Next, as shown in FIG. 9, using the atmospheric pressure CVD apparatus, a mixed gas of silane and N ₂ O, about temperature 70
An interlayer film 8 of a CVD-SiO ₂ film is formed at 0 ° C. Further, the interlayer film 8 is anisotropically dry-etched using a mixed gas of CHF ₃ and O ₂ to form contacts for forming external electrodes of source, drain and gate electrodes.

Then, Al--S is formed by the sputter deposition method.
An aluminum film of a mixture of i-Cu is formed. This aluminum film is anisotropically dry-etched using a mixed gas of BCl ₃ , Cl ₂ and CHCl ₃ to form a source external electrode 9a, a gate external electrode 9b and a drain external electrode 9c.

The contacts for forming the external electrodes are
Since the side wall 7 is concave, the contact edge is concave and is forward tapered.

As a result, the step coverage at the contact portion of the aluminum film formed by sputter deposition is improved. If the step coverage is good, disconnection does not occur at the contact portion of the aluminum film. Therefore, the step of isotropically etching the contact edge to form a concave surface and the step of burying the contact with polysilicon or a CVD-W film are unnecessary.

Further, since the step coverage of the aluminum film is good, the thickness of the aluminum film can be reduced. Therefore, after etching the aluminum film,
It is possible to prevent moisture from entering the aluminum film and corroding it. Therefore, the coverage of the passivation film, phosphosilicate glass (PSG), and the silicon nitride film by the plasma CVD method is also improved,
Increased passivation effect.

With respect to the transistor array manufactured as described above, the result of observing the generation state of crystal defects using a transmission electron microscope (TEM) is shown in FIG.
It shows in (b).

In FIG. 15A, the sidewall 7 is formed so as to be in contact with the gate electrode 4. The blackened region 31 is a crystal defect.

The crystal defect generated by the implantation of As ⁺ ions is generated at a position away from the point A of the impurity ion implantation region edge in the source / drain direction. As described above, since no crystal defect is generated from the position of the edge of the sidewall 7, etching is performed so that the surface of the sidewall 7 becomes a concave surface, and the edge is formed closer to the gate electrode side. If you can do it

FIG. 15B shows a cross section of a transistor array manufactured by a conventional method for comparison, taken as T.
The state of the crystal defect observed by EM is shown.

Crystal defects 32 were generated at the edge portions of the sidewalls 17. Then, it occurs at a position deeper than the defect generated by normal ion implantation. It is considered that this is because the stress at the edge of the sidewall 17 causes a mismatch in the crystal, and the crystal defect caused by the mismatch grows deeply by the subsequent annealing.

Furthermore, the sidewalls 7 and 1 of both of them
When a transistor array having No. 7 was formed and its leak current was measured, the transistor array according to the method of the present embodiment was 1 compared with the transistor array according to the conventional method.
The leak current was reduced by more than one digit. From these results as well, it was confirmed that the method of the present invention is a useful method for manufacturing a transistor having stable characteristics with a small leak current.

Although the low-concentration impurity diffusion layer 5 is formed after the gate electrode 4 made of the polysilicon film is etched in the above-mentioned embodiment, the same result as that described above can be obtained without this. . In the embodiment, n
Although an example of implanting p-type impurity ions has been described, it goes without saying that similar effects can be obtained by implanting p-type impurity ions.

Furthermore, the method of the present invention is effective even when it is applied to the case where a substrate made of another semiconductor such as a compound semiconductor other than silicon is used.

[0106]

According to the method of the present invention, a conductive film is formed on a semiconductor substrate with an insulating film interposed, a sidewall is formed on the side wall of the conductive film, and then impurity ions are implanted. Moreover, since the surface of the sidewall is formed in a concave shape, it is possible to prevent a large stress from being concentrated directly on the edge of the impurity ion implantation region. Thereby, when annealing is performed for electrically activating the impurity ion-implanted layer, generation of defects due to stress at the edge of the impurity ion-implanted region is suppressed. Furthermore, by forming the sidewalls in the above-described shape and forming the edges away from the edges of the impurity ion-implanted regions, defects due to stress during the annealing process may occur at the edges of the impurity ion-implanted regions. Suppressed.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device for explaining an embodiment of the present invention.

FIG. 2 is a sectional view of a method of manufacturing a semiconductor device for explaining an embodiment of the present invention.

3A to 3C are cross-sectional views of a method of manufacturing a semiconductor device for explaining an embodiment of the present invention.

FIG. 4 is a process sectional view of a method for manufacturing a semiconductor device for explaining an embodiment of the present invention.

FIG. 5 is a process sectional view of a method for manufacturing a semiconductor device for explaining an embodiment of the present invention.

FIG. 6 is a sectional view of a method of manufacturing a semiconductor device for explaining an embodiment of the present invention.

FIG. 7 is a process sectional view of a method of manufacturing a semiconductor device for explaining an embodiment of the present invention.

FIG. 8 is a process sectional view of a method for manufacturing a semiconductor device for explaining an embodiment of the present invention.

FIG. 9 is a process sectional view of a method for manufacturing a semiconductor device for explaining an embodiment of the present invention.

FIG. 10 is a detailed cross-sectional view in order of the steps of a method for manufacturing a semiconductor device, for illustrating the embodiment of the present invention.

FIG. 11 is a diagram illustrating the relationship between the incident angle of ions and the etching rate of the present invention.

FIG. 12 is a model diagram for explaining the relationship between the sidewall angle and stress of the present invention.

FIG. 13 is a characteristic diagram showing the relationship between the sidewall angle and stress of the present invention.

FIG. 14 is a diagram for explaining stress concentration of the present invention.

FIG. 15 is a cross-sectional view in order of the steps of the method for manufacturing the semiconductor device of the present invention.

16A to 16C are process cross-sectional views illustrating a conventional method for manufacturing a semiconductor device.

FIG. 17 is a process cross-sectional view illustrating a conventional semiconductor device manufacturing method.

FIG. 18 is a process cross-sectional view illustrating the conventional method for manufacturing a semiconductor device.

FIG. 19 is a process cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

FIG. 20 is a process sectional view illustrating the method for manufacturing the conventional semiconductor device.

FIG. 21 is a process sectional view illustrating the method for manufacturing the conventional semiconductor device.

FIG. 22 is a process sectional view explaining the method for manufacturing the conventional semiconductor device.

[Explanation of symbols]

1 Silicon substrate 2 LOCOS 3 Gate oxide film 4 gate electrode 5, 6 Ion implantation area 7 Sidewall

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Mariko Ito             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electronics             Industry Co., Ltd.

Claims (6)

[Claims] 1. A semiconductor substrate, a source and a drain formed on the semiconductor substrate, an ion-implanted region having a lower concentration than the source / drain formed at a side end where the source and the drain face each other, A gate electrode is formed between the source and the drain on the silicon substrate via a gate oxide film, and sidewalls are formed at both ends of the gate electrode. The side wall has a concave shape. A semiconductor device characterized by the above. 2. The semiconductor according to claim 1, wherein the sidewall has a sidewall angle of not more than 52 degrees between a tangent line at which an end of the sidewall contacts the semiconductor substrate and the semiconductor substrate. apparatus. 3. The principal stress of the sidewall is 2 × 10 ⁸
The semiconductor device according to claim 1, wherein the semiconductor device is smaller than dyne / cm ² . 4. A step of forming a gate oxide film on a semiconductor substrate, a step of forming a gate electrode on the gate oxide film, and a step of implanting low concentration impurity ions to be a source and a drain using the gate electrode as a mask. C. by a normal pressure CVD method on the surface of the gate electrode and the surface of the semiconductor substrate.
A step of depositing a VD-SiO ₂ film, and the CVD-Si
Anisotropic dry etching of the O ₂ film and the CV
A step of forming a high-concentration impurity ion-implanted region using the D-SiO ₂ film as a mask; and a step of isotropically etching the CVD-SiO ₂ film to form a concave sidewall. A method for manufacturing a characteristic semiconductor device. 5. The sidewall is formed into a concave shape by using an inert gas and is formed at one time by a sputtering etching which has the fastest etching rate at an incident angle of 45 degrees. A method for manufacturing a semiconductor device as described above. 6. A step of forming a gate oxide film on a semiconductor substrate, a step of forming a gate electrode on the gate oxide film, and a step of implanting low-concentration impurity ions serving as a source and a drain using the gate electrode as a mask. C. by a normal pressure CVD method on the surface of the gate electrode and the surface of the semiconductor substrate.
A step of depositing a VD-SiO ₂ film, and the CVD-Si
Anisotropic dry etching of the O ₂ film and the CV
A step of forming a high-concentration impurity ion-implanted region using the D-SiO ₂ film as a mask; a step of isotropically etching the CVD-SiO ₂ film to form a sidewall having a concave surface; A semiconductor device comprising: an annealing step; a step of forming an interlayer film on the sidewall, the gate electrode, and the semiconductor substrate; and a step of forming a contact with the interlayer film and forming an external electrode. Manufacturing method.