JPH0531876B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is directed to a device that continuously reproduces field-recorded television signals as still images, such as an image pickup device that converts an image received by an image pickup device into a video signal. The present invention relates to a video signal processing device that can be used in electronic still cameras and the like that can store still images by magnetically recording them on magnetic disks and display them on television receivers.

Configuration of conventional example and its problems In the field image, discontinuity of 0.5H (1H indicates horizontal scanning period = approximately 63.5μs) occurs every field (approximately every 1/60 seconds), and the discontinuity occurs on the television screen. It becomes skewed. To prevent this, conventional video signal processing devices process the video signal every other field.
By delaying 0.5H, we remove this discontinuity and
In addition, the field signals were interlaced frame by frame. That is, FIG. 1 is a circuit block diagram for creating a pseudo frame, and the input terminal 1 is used to input the playback signal of the electronic camera device, and as shown in FIG. There is a 0.5H discontinuity in the horizontal synchronization signal at _T1 . The 0.5H delay device 2 delays the input signal a from the input terminal 1 by 0.5H.
It consists of a glass delay line or CCD memory or RAM. This output is the input signal a delayed by exactly 0.5H, as shown in FIG. 2b. Switch these two signals a and b at a predetermined timing.
Select with Sw ₁ . The control signal C of switch Sw ₁ is
This occurs in the control circuit 3. In other words, the horizontal synchronization of input signal a becomes discontinuous before and after T ₁ , the phase is discontinuous for each field, and the vertical synchronization signal is always the same as input signal a.
It generates a control signal C that outputs . As a result, the output terminal 14 receives a television signal with no phase discontinuity around _T2 , as shown in FIG. 2d, and when displayed on a television receiver, no skew occurs. The result is an interlaced image.

However, when waveform distortion occurs in the 0.5H delay device 2, a signal difference occurs between the first field where the input signal a is projected and the second field where the 0.5H delayed signal b is projected, resulting in flickering. There was a problem in that it was seen as an unsightly image, making it unsightly. Typical waveform distortions include signal reflection components in the case of a glass delay line, and linearity or noise interference in the case of a CCP memory.

OBJECTS OF THE INVENTION The present invention solves the above-mentioned conventional drawbacks, and an object of the present invention is to provide a video signal processing device that can reduce flicker caused by a signal difference between a first field and a second field.

Structure of the Invention The present invention solves the above-mentioned conventional drawbacks.
The first video signal whose horizontal synchronization phase causes discontinuity of 1/2 horizontal scanning time for each field is 1/2H.
delay means for obtaining a delayed second video signal; delay addition means for obtaining a third video signal obtained by adding the first video signal and a signal delayed by one horizontal scanning period; and a switch means for switching the signal and the third video signal for each field at or near a discontinuous point of horizontal synchronization of the first video signal.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a circuit block diagram of a video signal processing apparatus according to an embodiment of the present invention, in which the same components as those shown in FIG. 1 are given the same reference numerals and their explanations will be omitted.

In Fig. 3, 2a and 2b are 0.5H delay devices,
5 is a clock section, 6 is a mixing amplifier circuit, and 7 is an amplifier circuit. In this embodiment, 0.5H delay device 2a,
As 2b, a 455-stage CCD memory is used, and 4f _sc (f _sc
is driven at a clock frequency of approximately 3.58 MHz (color subcarrier frequency). The input signal from the input terminal 1 is delayed by 0.5H in the first 0.5H delay device 2a, and further delayed by 0.5H in the second delay device 2b to obtain a 1H delayed signal. Each 0.5H delay device 2a, 2b is driven by a clock signal from a clock section 5. The 1H delayed signal and the input signal are mixed at the same ratio in the mixing amplifier circuit 6, and the gain is set to 1/
Set it to 2. On the other hand, the 0.5H delayed signal is amplified by the amplifier circuit 7 to have the same amplitude as the output signal of the mixing amplifier circuit 6. The switch Sw ₁ is controlled by a signal generated in the control circuit 3.

Figure 4 is a signal waveform diagram of each part of the circuit shown in Figure 3, where e is the input signal, f is the 0.5H delay signal, and g is the 1H delay signal.
The delayed signal h is a summed signal obtained by adding the input signal e and the 1H delayed signal g to reduce the amplitude to 1/2. The vertical transients of the signal are therefore averaged. As shown in FIG. 4h, the waveform of the vertical synchronizing signal of the addition signal h changes. Therefore, the output signal j
is the vertical synchronization signal and the first signal with a delay of 0.5H before and after it.
field is selected, and the video signal portion is created with a waveform almost similar to that of a television signal by switching between the first field and the second field for each field before the discontinuous point of horizontal synchronization in the first field. It can be done. In other words, the control signal i consists of a pulse whose phase is inverted for each field before the discontinuity point of the 0.5H delay signal f, and a pulse whose phase is inverted for each field before the discontinuity point of the 0.5H delay signal f, and a pulse whose phase is inverted for each field before the discontinuity point of the 0.5H delay signal f, and a pulse whose phase is inverted for each field before the discontinuity point of the 0.5H delay signal f, and a pulse whose phase is inverted for each field before the discontinuity point of the 0.5H delay signal f, and a pulse whose phase is inverted for each field before the discontinuity point of the 0.5H delay signal
It is made from two pulses: the pulse up to ~2H. By selecting the first and second fields with the switch _Sw1 in this manner, the output signal j is obtained.

In this way, 0.5H delay device 2a or 2b
When the distortion due to ΔV is connected in two stages,
The distortion of 1H delay is 2ΔV, and by adding this to the undistorted input signal e and reducing it by half, the distortion becomes
2ΔV/2=ΔV, which is equivalent to the distortion of 0.5H delay, and it is possible to prevent flickering.

Furthermore, since the signals are added in front and rear horizontal synchronization, there is an interpolation effect. If the horizontal number of the output signal j is assigned as shown in FIG. 4, the image will be displayed on the television receiver as shown in FIG. 5. The ~ raster shown by the solid line ends at the right edge of the screen, and the raster '~' shown by the dashed line ends at the center of the screen,
Return to the top of the CRT. If the amplitude of horizontal No. is 1,
The amplitude before and after is 1/2, and when interlaced, the result is exactly interpolated, and the signal changes smoothly.

Effects of the Invention As explained above, according to the present invention, it is possible to satisfactorily prevent the occurrence of flickering, etc., and to obtain the effect of interpolation, so that signal changes are smoothed, and excellent image quality can be obtained. .

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram of a conventional video signal processing device, FIG. 2 is a signal waveform diagram of each part of the circuit shown in FIG. 1, and FIG. 3 is a circuit block diagram of a video signal processing device according to an embodiment of the present invention. , FIG. 4 is a signal waveform diagram of each part of the circuit shown in FIG. 3, and FIG. 5 is a signal interpolation diagram when a television signal is displayed on a television receiver by a video signal processing device in an embodiment of the present invention. FIG. 2a, 2b...0.5H delay device, 3...Control circuit, 5...Clock section, 6...Mixing amplifier circuit, 7
...Amplification circuit, Sw ₁ ...Switch.

Claims (1)

[Claims] 1. The phase of horizontal synchronization is 1/2 for each field.
a delay means for obtaining a second video signal obtained by delaying the first video signal by 1/2H, which causes discontinuity in horizontal scanning time;
delay addition means for obtaining a third video signal by adding the first video signal and a signal delayed by one horizontal scanning period; A video signal processing device comprising a switch means for switching each field at or near a discontinuous point of horizontal synchronization of a video signal. 2. When switching the second video signal and the third video signal for each field at or near a discontinuous point of horizontal synchronization of the first video signal, the switching means always switches the vertical synchronization signal and its vicinity to the first video signal. 2. The video signal processing device according to claim 1, wherein the video signal processing device is configured to select two video signals.