JPH053182A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable a pattern to be sharply lessened in dimensional error so as to obtain a polycrystalline silicon gate element of high accuracy by a method wherein a thin silicon oxide film formed at a low temperature is used as an etching mask. CONSTITUTION:In a method of manufacturing a semiconductor device, where an amorphous silicon film 53 is deposited on a substrate 51 and then selectively etched using a mask pattern formed on the film 52, and the substrate 51 is thermally treated to turn the amorphous silicon film 53 polycrystalline, a thin silicon oxide film 54 which is formed at a low temperature at which an amorphous silicon film is not turned polycrystalline is used as the mask pattern formed on the amorphous silicon film 53.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a highly accurate polycrystalline silicon gate element.

[0002]

2. Description of the Related Art In recent years, with the demand for improved performance in semiconductor devices, for example, in silicon gate elements, there is a demand for finer gate dimensions and thinner gate underlayer oxide films. In order to realize this, a high-precision fine processing technique and a process technique which do not cause a high etching selectivity and an undercut between a silicon film and an underlying oxide film are required.

FIG. 2 shows a first conventional method for a polycrystalline silicon gate device structure. A silicon oxide film 12 is formed on a silicon substrate 11 by a thermal oxidation method, a polycrystalline silicon film 13 is deposited on the silicon oxide film 12, and a resist pattern 14 is further formed thereon (FIG. 2a). After that, the polycrystalline silicon film 13 is dry-etched using the resist pattern 14 as a mask to form a polycrystalline silicon pattern 13 '(FIG. 2).
b). After that, the resist pattern 14 is removed by ashing the sample with oxygen plasma to complete the desired polycrystalline silicon gate device structure (FIG. 2c). In this method, the polycrystalline silicon film having large crystal grains is etched. However, there is a drawback that a large undercut occurs due to the etching reaction along the grain boundaries.
Particularly, in the case of a polycrystalline silicon film to which an n-type impurity is added, electrons in the film attract ions to etch the side wall of the silicon film, so the undercut amount becomes a very large value.

FIG. 3 shows a second conventional technique (Japanese Patent Application No. 60-197843) improved so as to suppress the undercut generated during etching. According to this method, a base thermal oxide film 22 is formed on a silicon substrate 21, amorphous silicon 23 is deposited thereon, and then a resist 24 is formed thereon.
Are formed (FIG. 3a). Next, using the resist 24 as a mask, the resist 24 and the amorphous silicon 23 are etched to form a pattern (FIG. 3b), and then the resist 24 is removed to leave an amorphous silicon pattern 23 '(FIG. 3c). The crystalline silicon is heat-treated to form a polycrystalline silicon pattern 25. The characteristic of this method is that
This is intended to obtain a desired polycrystalline silicon pattern by etching the silicon film in an amorphous state in which undercut is unlikely to occur, using a resist pattern as a mask, and then performing heat treatment for polycrystallization. The advantages of this method are:
It is possible to suppress the amount of undercut generated during etching to be smaller than that of the first conventional method.

However, it has become clear that this method also has two problems that may be caused by a thick resist mask. The first problem is related to the nonuniformity of the etching pattern shape due to the thick mask. Recently, an ECR plasma etching apparatus utilizing low-energy ions has been adopted for etching a silicon film due to the need for low damage and high selectivity etching. However, since this method uses ions that are transported along the divergent magnetic field, the angle of incidence of the ions on the wafer surface is perpendicular to the center of the wafer but obliquely enters the wafer periphery due to the effect of the divergent magnetic field. To do.

FIG. 4 shows an etching pattern shape when ions are obliquely incident on a sample having a thick film etching mask. Thick film mask 3 on amorphous silicon film 31
When the ions 33 obliquely enter the sample surface having 2 (FIG. 4a), there is a large region where the ions cannot reach the wafer surface, and therefore the shape of the etching pattern 31 ′ is significantly asymmetrical as shown in FIG. 4b. The pattern size also causes a large overweight error. Note that this phenomenon increases in proportion to the mask thickness and the oblique incident angle of ions. As described above, when a large-diameter wafer is etched using a thick film etching mask in a divergence type ECR plasma device, it has been found that a remarkable pattern shape and dimensional error occur at the center and the outer periphery of the wafer. As described above, with this method, it is difficult to secure an etching pattern with good uniformity over the entire surface of the large-diameter wafer.

The second problem is that the etching selectivity is lowered by using a resist as an etching mask. Recently, with the demand for further improvement in performance, the film thickness of the gate underlayer oxide film is required to be further reduced. Therefore, it is desired to further improve the etching selection ratio between the silicon film and the silicon oxide film as compared with the conventional case.
However, when etching is performed by masking a resist containing carbon, hydrogen, and oxygen as main components, carbon in the sputtered resist reacts with oxygen in the underlying thermal oxide film to locally change the etching rate of the underlying oxide film. It turned out that the phenomenon of raising the temperature inevitably cannot be avoided. As described above, the resist mask causes a problem that the etching selectivity is unavoidably lowered. As described above, the conventional technique requires a uniform pattern shape over the entire surface of the wafer, which is further required as the diameter of the wafer is increased, and an etching selectivity ratio which is required as the underlying oxide film is further thinned. It had a drawback that it could not meet the requirement of further improvement.

[0008]

SUMMARY OF THE INVENTION The present invention solves the drawbacks of the prior art and ensures a highly uniform pattern shape and a high etching selection ratio over the entire surface of a large-diameter wafer, while maintaining high precision and no undercut. An object is to provide a method for manufacturing a semiconductor device having a crystalline silicon gate element.

FIG. 5 shows an etching pattern shape when ions are obliquely incident on a sample having a thin film etching mask. A thin film mask 4 on the amorphous silicon film 41.
When the ions 43 are obliquely incident on the sample surface having 2 (FIG. 5a), the area where the ions cannot reach the wafer surface is significantly reduced by the reduction of the mask thickness, so that the asymmetric shape of the etching pattern 41 ′ is as shown in FIG. 5b, the pattern size is greatly improved, and the pattern size error is significantly reduced as compared with FIG. 4b.

[0010]

In order to achieve the above object, the present invention is to deposit an amorphous silicon film on a substrate and then form the amorphous silicon film by a mask pattern formed on the amorphous silicon film. In a method of manufacturing a semiconductor device in which a silicon film is selectively etched and then heat-treated to polycrystallize the amorphous silicon film, the amorphous pattern is used as a mask pattern formed on the amorphous silicon film. The gist of the invention is a method for manufacturing a semiconductor device, which uses a thin silicon oxide film formed at a low temperature so as not to polycrystallize the silicon film.

[0011]

According to the present invention, by using a thin silicon oxide film formed at a low temperature as an etching mask, it is possible to greatly reduce the pattern size error and form a highly accurate polycrystalline silicon gate device. be able to.

[0012]

EXAMPLES Next, examples of the present invention will be described. It is needless to say that the embodiment is merely an example, and various modifications and improvements can be made without departing from the spirit of the present invention.

FIG. 1 is a diagram for explaining an embodiment of a method for manufacturing a semiconductor device according to the present invention. In the figure, 51 is a silicon substrate, 52 is a thermal oxide film, 53 and 53 'are amorphous silicon films and patterns, 54 and 54' are low temperature formed silicon oxide films and patterns, 55 is a resist pattern, and 56 is polycrystalline silicon. A pattern is shown. First, an ultrathin silicon oxide film 52 having a thickness of 10 nm or less is formed on a silicon substrate 51 by a thermal oxidation method, and then a chemical vapor deposition method (CVD method) in which disilane and phosphine are reacted at a temperature of 650 degrees. )
Then, an amorphous silicon film 53 having a thickness of 300 nm is deposited. Further, a 100 nm thick silicon oxide 54 is deposited on the amorphous silicon film 53 by an atmospheric pressure CVD method in which monosilane is thermally decomposed at a low temperature (for example, 400 degrees) that does not polycrystallize the amorphous silicon film 53. After that, a resist pattern 55 having a thickness of 1 μm is formed on the film 54 (FIG. 1a).

Next, the silicon oxide film 54 is etched by a dry etching method using the resist pattern 55 as a mask, and thereafter, the unnecessary resist pattern 55 is removed by ashing treatment in oxygen plasma to have a thickness of 100 nm. A thin film etching mask made of the silicon oxide film pattern 54 'of FIG. Next, an amorphous silicon film 53 is formed using the silicon oxide film pattern 54 'as a mask by an ECR plasma flow etching device.
Is etched to form an amorphous silicon film pattern 53 '(FIG. 1c).

Finally, the sample is heat-treated in a nitrogen atmosphere at 900 ° C. for 30 minutes to form a predetermined polycrystalline silicon film pattern 56 (FIG. 1d). As described above, the method of the present invention is characterized in that the amorphous silicon film is etched by using the thin silicon oxide film formed at a low temperature as an etching mask and is then polycrystallized by the subsequent heat treatment. Thus, in the etching of the silicon film, by adopting the manufacturing method in which the thin silicon oxide film mask is used instead of the conventional thick film resist mask, firstly, it is possible to improve the non-uniformity of etching in the conventional large-diameter wafer. Compared with the above, it is possible to secure a higher etching uniformity. Secondly, the lowering of the conventional etching selection ratio caused by the resist is solved to ensure a higher selection ratio than the conventional one. In the above embodiment, the thickness of the silicon oxide film formed at a low temperature is 100
However, considering the points such as generation of pinholes that cause defects and reduction in dimensional conversion difference, it is preferable to use 20 nm to 200 nm as the thickness of the silicon oxide film in practice.

As described above, by adopting the method of the present invention, it is possible to obtain a highly accurate polycrystalline silicon pattern while ensuring high uniformity and selectivity in a large-diameter wafer, which was difficult with the conventional method. Is possible. Although the etching mask is the silicon oxide film formed by the thermal decomposition reaction in this embodiment, the mask material and the forming method are not limited thereto. For example,
As a forming method, any plasma in a temperature range that does not polycrystallize an amorphous silicon film, such as an ECR plasma CVD method that can be formed at room temperature and low pressure or a high frequency plasma CVD method that can be formed by heating a substrate at about 400 degrees It goes without saying that the processing method may be used. The mask material may also be a silicon nitride film (Si-N) and a silicon oxynitride film (Si-O-N) that can be formed by a low temperature plasma CVD method or the like.

[0017]

As described above, according to the present invention,
By etching the amorphous silicon film using the thin silicon oxide film formed at a low temperature as an etching mask, and then polycrystallizing the amorphous silicon film by the subsequent heat treatment,
It is possible to form a highly accurate polycrystalline silicon gate element without undercut while ensuring high uniformity and selectivity in a large-diameter wafer. In particular, since the uniformity is higher and the pattern shape is better than before, there is an effect that it is possible to manufacture a device with a small yield of characteristics and a high yield.

[Brief description of drawings]

1A to 1D show an embodiment of a method for manufacturing a semiconductor device of the present invention.

2A to 2C are manufacturing process diagrams relating to a conventional method for manufacturing a semiconductor device in which a polycrystalline silicon film is etched using a resist mask.

3A to 3D are manufacturing process diagrams relating to a conventional method of manufacturing a semiconductor device in which an amorphous silicon film is etched using a resist mask and then heat treatment is performed.

FIG. 4A is a schematic view showing a state in which ions are obliquely incident on a sample having a thick film mask. (B) is
An example of the etching pattern shape formed according to the situation of (a) is shown.

FIG. 5A is a schematic view showing a state where ions are obliquely incident on a sample having a thin film mask. (B) is
An example of the etching pattern shape formed according to the situation of (a) is shown.

[Explanation of symbols]

 11 Silicon Substrate 12 Underlayer Thermal Oxide Film 13 Polycrystalline Silicon Film 13 ′ Pattern 14 Resist Pattern 21 Silicon Substrate 22 Underlayer Thermal Oxide Film 23 Polycrystalline Silicon Film 23 ′ Pattern 24 Resist Pattern 25 Polycrystalline Silicon Pattern 31 Amorphous Silicon Film 31 'Pattern 32 Thick film mask 33 Oblique incident ions 41 Amorphous silicon film 41' Pattern 42 Thin film mask 43 Oblique incident ions 51 Silicon substrate 52 Underlayer thermal oxide film 53 Amorphous silicon film 53 'Pattern 54 Low temperature formation silicon oxide film 54 ′ Pattern 55 Resist pattern 56 Polycrystalline silicon pattern

Claims (1)

Claim: What is claimed is: 1. An amorphous silicon film is deposited on a substrate, and then the amorphous silicon film is selectively etched by a mask pattern formed on the amorphous silicon film. In a method of manufacturing a semiconductor device in which a heat treatment is performed to polycrystallize the amorphous silicon film, a low temperature that does not polycrystallize the amorphous silicon film is used as a mask pattern formed on the amorphous silicon film. 1. A method of manufacturing a semiconductor device, which comprises using the thin silicon oxide film formed in step 1.