JPH053179B2 - - Google Patents
Info
- Publication number
- JPH053179B2 JPH053179B2 JP58185551A JP18555183A JPH053179B2 JP H053179 B2 JPH053179 B2 JP H053179B2 JP 58185551 A JP58185551 A JP 58185551A JP 18555183 A JP18555183 A JP 18555183A JP H053179 B2 JPH053179 B2 JP H053179B2
- Authority
- JP
- Japan
- Prior art keywords
- processor
- packet
- control
- slave
- system bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
- G06F13/128—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine for dedicated transfers to a network
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
- Information Transfer Systems (AREA)
- Small-Scale Networks (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18555183A JPS6076839A (ja) | 1983-10-04 | 1983-10-04 | プロセツサ制御方式 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18555183A JPS6076839A (ja) | 1983-10-04 | 1983-10-04 | プロセツサ制御方式 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6076839A JPS6076839A (ja) | 1985-05-01 |
| JPH053179B2 true JPH053179B2 (online.php) | 1993-01-14 |
Family
ID=16172785
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18555183A Granted JPS6076839A (ja) | 1983-10-04 | 1983-10-04 | プロセツサ制御方式 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6076839A (online.php) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2855326B2 (ja) * | 1987-04-09 | 1999-02-10 | 東洋通信機株式会社 | コンピユータ・システム |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS575141A (en) * | 1980-06-10 | 1982-01-11 | Toshiba Corp | Bus control system |
-
1983
- 1983-10-04 JP JP18555183A patent/JPS6076839A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6076839A (ja) | 1985-05-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4744023A (en) | Processor access control arrangement in a multiprocessor system | |
| US4945473A (en) | Communications controller interface | |
| EP0404414A2 (en) | Apparatus and method for assigning addresses to SCSI supported peripheral devices | |
| US4509140A (en) | Data transmitting link | |
| WO1982002442A1 (en) | Interrupt coupling and monitoring system | |
| US11409679B2 (en) | System component and use of a system component | |
| EP0344722A3 (en) | Operation mode settable lan interconnecting apparatus | |
| EP0790560A2 (en) | Interface for computer network | |
| US4796022A (en) | Double transit bus system | |
| KR102303424B1 (ko) | 랜덤 액세스 메모리를 포함하는 하나 이상의 처리 유닛을 위한 직접 메모리 액세스 제어 장치 | |
| US5930261A (en) | Bus protocol | |
| US6732210B1 (en) | Communication bus for a multi-processor system | |
| JP4104939B2 (ja) | マルチプロセッサシステム | |
| KR100285953B1 (ko) | 패킷버스및이를이용하여패킷데이터를전송하는장치및방법 | |
| JPS6246025B2 (online.php) | ||
| EP0579398A1 (en) | Method of addressing devices and transferring data signals on a bus | |
| EP0064074B1 (en) | Data transmitting link | |
| JPS6242306B2 (online.php) | ||
| CA1235229A (en) | Double transit bus system | |
| US5721946A (en) | Signal transfer method having unique word assigned to terminal stations appended before control frames originated from control station and terminal stations | |
| JPS6298444A (ja) | デ−タ通信方式 | |
| JP4125933B2 (ja) | 共通メモリを備えたプロセッサシステム | |
| JPH0223060B2 (online.php) | ||
| JP2705955B2 (ja) | 並列情報処理装置 | |
| US7177997B2 (en) | Communication bus system |