JPH053178B2 - - Google Patents

Description

[Detailed description of the invention] Industrial applications The present invention relates to a delta modulation signal demodulation circuit.

Conventional technology and its problems A delta modulation method that samples an analog signal, differentially quantizes the sample value using a 1-bit (2-level) quantizer, and transmits the code is often used in PCM transmission systems. be. An integrator is generally used as a demodulator in this delta modulation transmission system. It is known that in this method, bit errors occurring in the transmission system are accumulated by the integrator, which tends to deteriorate the reproduction quality. In particular, in a transmission system where multiple channels of data are serially transmitted, separated into each channel on the receiving side, and then joined together to form a series of data from each individual channel, if the error rate of the transmission system is high, the reproduction analog signal will be affected. A DC shift occurs at each connection point, resulting in a very low quality signal. In addition, a rotating head type is used for the transmission system.
When using a VTR, data is transmitted discontinuously depending on the rotation period of the head, so when variable speed playback such as fast playback or slow playback is performed, the error rate increases and a DC shift occurs at each data connection point. do. When performing fast playback or slow playback on a rotating head VTR, tracks may be thinned out, scanned across multiple tracks, or one track may be scanned overlappingly, so playback When restoring each time-division multiplexed channel of a signal (for example, an audio signal), a waveform phase shift (discontinuity) essentially occurs at each connection point of each channel, but at the same time, during variable speed playback, the transmitted The error rate of the delta modulated signal increases due to noise and level fluctuations of the reproduced output, and the DC error of the demodulated output increases.
As a result, a DC shift occurs at the connection point of each waveform, and the discontinuity of the waveform significantly deteriorates the reproduction quality. Furthermore, as the accumulation of DC error components increases, the reproduction circuit system may become saturated or the equivalent dynamic range may decrease.

Purpose of the invention In view of the above-mentioned problems, the present invention provides a method for delta modulation.
DC due to error bit when demodulating PCM signal
It is an object of the present invention to provide a demodulation circuit with less residual error components.

Summary of the Invention The delta modulation signal demodulation circuit of the present invention is a delta modulation signal demodulation circuit (FIG. 1) that decodes a reproduced delta modulation signal from a reproduction device (VTR 9) in a decoding circuit 12 and then demodulates the reproduced delta modulation signal. an integrator consisting of a differential amplifier 17 and a feedback circuit 18 to obtain an analog signal by integrating a delta modulated signal; a resistor R ₁ for varying the time constant of the time constant feedback circuit 18 of the integrator;
The above-mentioned time constant can be adjusted by a time constant variable means (Figs. 2 and 4) such as R ₂ and CdS20, and a high-speed playback mode signal F from the above-mentioned playback device or a bit error increase signal E from the above-mentioned decoding circuit. It consists of a switching means such as a switch 19 that changes the variable means to increase the DC negative feedback amount of the integrator. With this configuration, even if a DC error component occurs in the demodulated output, it is quickly erased.

Example The present invention will be described below with reference to Examples.

FIG. 1 is a block diagram of a delta modulation PCM transmission system for audio signals to which the present invention is applied. In Fig. 1, the inputs of the first channel (CH-1) and the second channel (CH-2) are given to delta modulators 3 and 4 via low-pass filters 1 and 2, and the current sample value and the previous sample value are input to delta modulators 3 and 4. The difference (size) from the sample value is quantized by 1 bit. The outputs of the delta modulators 3 and 4 are combined into a serial signal by a multiplexer 5, converted into a PCM signal with an error correction function by a coding circuit 6, and then data interleaved by an interleaving circuit 7. Further, the signal is converted into a video format signal by a video modulation circuit 8, and recorded by a rotary head type VTR 9.

The playback output of the VTR 9 is provided by a video demodulation circuit 10,
It is demodulated into a two-channel delta modulated signal via a deinterleaving circuit 11 and a decoding circuit 12, and then converted into an analog signal by delta demodulators 13 and 14.
After the conversion, the signals are passed through low-pass filters 15 and 16 and output as first and second channel audio signals to the outside.

As the delta demodulators 13 and 14 in FIG.
An integrator as shown in the figure is usually used. A delta modulation signal converted into positive and negative pulses is applied to the inverting input of the differential amplifier 17 constituting this integrator.
The output of the differential amplifier 17 is fed back to the inverting input via a feedback circuit 18 consisting of a series circuit of resistors R ₁ and R ₂ connected in parallel to integrating capacitors C and C. Resistors R ₁ and R ₂ are provided to cancel the DC offset of the integrator with a predetermined time constant, thereby making the low-frequency gain of the integrator a finite value. Feedback circuit 18 is a high pass filter and therefore:
Above the cutoff frequency c, the amount of negative feedback increases and the output level of the differential amplifier 17 decreases. That is, the circuit of FIG. 2 exhibits an integral characteristic as shown in FIG. 3, and by this integral action, the weight of each bit of the input delta modulation signal is converted into an analog level.

In the embodiment of the present invention, a switch 19 is provided for changing the cutoff frequency c of the integrator, as shown in FIG. This switch 19 is connected in parallel with the resistor _R1 of the feedback circuit 18, and when the switch 19 is closed, the parallel resistance of the capacitor C decreases, the amount of negative DC feedback increases, and the amount of feedback on the high frequency side decreases. Relatively decreasing. That is, feedback circuit 1
As the lower passband of 8 widens, the gain decreases, and the cutoff frequency as an integrator decreases as shown in Figure 3.
It rises like c′.

By reducing the DC gain of the integrator, the DC error component produced at the integrator output by bit errors in the delta modulation signal will be attenuated more rapidly.
Therefore, the accumulation (residual) of DC error components is reduced, the DC shift occurring at the connection point of the reproduced signal is reduced, and the quality of the reproduced signal is improved.

Incidentally, as shown in FIG. 3, the dynamic range of the integrator is larger at lower frequencies. Therefore, increasing the high-frequency cutoff frequency of the integrator reduces the low-frequency dynamic range of the reproduced analog signal, which impairs the advantages of delta modulation transmission. Therefore, in this embodiment, during normal delta modulation transmission, the switch 19 is opened and the cutoff frequency is lowered as shown in c in Fig. 3 to ensure the required dynamic range, thereby increasing the error rate of delta modulation. In the case of such transmission, the switch 19 is closed and the cut-off frequency is raised to c'.

The switch 19 can be opened and closed, for example, as shown in Figure 1.
This is done using the high-speed playback mode signal F from the VTR 9, and the switch 19 is closed during high-speed playback to cope with an increase in error bits. Alternatively, as shown in FIG. 1, an error increase signal E based on bit error detection may be obtained from the decoding circuit 12, and this signal E may also be used to change the integration time constant of the delta demodulator.

FIG. 4 is a block circuit diagram showing another embodiment of a delta demodulator in which the integral constant can be changed. In this example, CdS20 is connected in parallel with the capacitor C of the integrator feedback circuit 18, and this CdS20
The integral time constant is continuously changed by controlling the amount of light irradiated to the area. To change the integration time constant,
This is done based on the error frequency of the delta modulated PCM signal being processed within the decoding circuit 12 of FIG.
That is, the delta modulated PCM signal is supplied to the error detection circuit 21, and error bits are detected based on check bits such as parity and CRC attached to this PCM signal. The detected error is given to the error frequency counting circuit 22, and every time the count value reaches a predetermined number, a pulse signal indicating an increase in the error is generated. This pulse signal is the time constant circuit 2
3 and converted into an optical signal using an LED or the like, and this optical signal also controls the resistance value of the CdS 20. Through this control, the low cutoff frequency of the delta modulator is increased in accordance with the amount of increase in error, and the DC error in the D/A conversion output is quickly attenuated.

As shown in the above embodiments, the resistors R ₁ and R ₂ make the time constant of the integrator time constant feedback circuit 18 variable.
Alternatively, a time constant variable means such as CdS20 is provided, and the time constant variable means is controlled by the high speed reproduction mode signal F from the reproduction device (VTR 9) or the bit error increase signal E from the decoding circuit 12. A switching means consisting of a switch 19 switches the integrator.
The configuration is such that the amount of DC negative feedback is increased. This lowers the DC gain of the integrator and reduces the DC error component of the demodulated output.

Effects of the Invention The present invention reduces the DC gain of the integrator of the demodulation circuit that acts as a D/A converter in order to reduce the DC component of the demodulated output due to error bits in the delta modulated signal transmitted as described above. By providing a means for this, even in the reproduction (reception) state where there are many error bits and therefore DC errors tend to remain in the integral output, the DC component is quickly attenuated, creating a transmission system that connects discontinuous transmission signals. Even in this case, the DC shift occurring at each connection point is small and a good reproduced signal can be obtained. Furthermore, in a transmission system with a small error rate, by increasing the reduction gain of the integrator, regenerative demodulation can be performed without impairing the wide low-frequency dynamic range peculiar to delta modulation transmission.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a delta modulation transmission system to which the present invention is applied, FIG. 2 is a circuit diagram showing an embodiment of a delta modulation signal demodulation circuit according to the present invention, and FIG.
The figure is a graph showing the integral characteristics of the circuit in Figure 2,
The figure is a block circuit diagram of a delta modulation signal demodulation circuit showing another embodiment. In the symbols used in the drawings, 3, 4...delta modulator, 17...differential amplifier, 18...feedback circuit, 19...switch, 20...CdS.

Claims (1)

[Scope of Claims] 1. A delta modulation signal demodulation circuit that decodes and demodulates a reproduced delta modulation signal from a reproduction device using a decoding circuit, the circuit comprising: an integrator that integrates the decoded delta modulation signal to obtain an analog signal; A time constant variable means for varying the time constant of a time constant feedback circuit of an integrator; and a time constant variable means that is switched by a high-speed playback mode signal from the playback device or a bit error increase signal from the decoding circuit. and switching means for increasing the DC negative feedback amount of the integrator.