JPH05316496A - Encoding device - Google Patents

Abstract

PURPOSE:To compress image data to prescribed data by DCT conversion-processing image data at every block considering a DCT conversion coefficient to be zero data when the counted value of data encoded in a direction from DC and low frequency components toward a high frequency component for a conversion coefficient reaches a prescribed value. CONSTITUTION:A digital picture signal is divided into plural blocks in a DCT processing circuit 1 for respective pieces of picture data in one field and two-dimensional DCT is executed for the respective blocks. The DCT conversion coefficient is quantized in a quantization circuit 2, and the conversion coefficient is converted into sequence from a DC component toward the high frequency component so as output it in a processing circuit 3. Then, it is written into a memory 4. The conversion coefficients of the same frequency component are sequentially read from the low frequency component by signal from a control circuit 5, and they are inputted to an encoding processing circuit 6. The circuit 6 executes a run length encoding processing, and a processing circuit 29 Huffman-encodes the number of the differential bits of the conversion coefficient in the DC component and adds the number of the bits. An encoding data amount from the circuit 29 is compared with a prescribed data amount from a prescribed data amount circuit 10 in a comparison circuit 11. When it exceeds a value, a termination flag is outputted from a picture termination data circuit 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coding device applied to a device for sampling and quantizing an image signal in the time axis direction and converting it into a digital signal for transmission, or for recording / reproducing. The present invention relates to an apparatus for compressing an image data amount of one frame or one frame into a predetermined data amount and encoding the compressed image data amount.

[0002]

2. Description of the Related Art In an apparatus for converting an image signal into a digital signal and transmitting it, the number of quantization bits per sample is usually required to be 7 to 8 bits in the case of linear quantization. If the image signal is directly digitized by this linear quantization, the transmission rate of the digital signal is
Standard TV system (sampling frequency, luminance signal: 13.5
MHz color difference signal (Cr, Cb): 6.75MHz) 150Mbp
s or more is required. In a device for magnetically recording this image signal as a digital signal (hereinafter, this is referred to as a digital VTR), since the transmission rate is extremely high as described above,
Compared with the conventional analog VTR, the tape recording density is substantially reduced, a sufficient recording time cannot be obtained, and the signal to be handled becomes a very wide band, and the operation speed of the digital signal processing circuit becomes a problem. It is technically difficult, and it is a big obstacle for widely spreading this digital VTR for home use.

In order to improve such a problem, so-called high efficiency coding has been studied in the past, and one field or one frame of image data amount is set to a predetermined data amount.
As a means for reducing the amount of data, for example, JP-A-3-229
There is a method described in Japanese Patent No. 571. In this method, one digital image is divided into a plurality of blocks each consisting of 1 × n × n pixels, discrete cosine transform is performed for each block, and n × n transform coefficients obtained by the transform are obtained. Quantization is performed by dividing each threshold value of the quantization matrix composed of n × n threshold values. Then, the transform coefficient F (u, v) (u, v = 0,1,2,
,, n-1) is set to a specific variable k, and "k≤u + v"
After setting the value of the conversion coefficient F (u, v) that satisfies the following condition to zero,
The conversion coefficient F (u, v) is converted from a direct current component toward a high frequency component into a one-dimensional number sequence in a fixed order, and the number of consecutive zeros in this converted number sequence is encoded to perform data compression. At this time, the cumulative distribution of the sum of squares of the AC components of the discrete cosine transform coefficient is obtained for each block, and a function that is proportionally converted to the desired compression data amount is determined from this cumulative distribution, and this function and the actual compression data are determined. -Comparison with the cumulative value of the data amount for each block, and the value of the variable k is adjusted for each block so that the cumulative value follows the above function.

According to this method, it is possible to compress one piece of digital image data into a desired amount of data.

[0005]

In the above prior art, the AC of the transform coefficient is first block by block before encoding and recording.
The sum of squares of the components is obtained, and the cumulative distribution of the sum of squares of the AC components is obtained for all blocks of one image. Then, a data amount function is obtained which is proportionally converted so that the maximum value of the cumulative distribution corresponds to the desired data amount after compression. Then, at the time of encoding, this data amount function and the actual compressed data amount cumulative value are compared for each block, and if "data amount function <compressed data amount cumulative value", adjustment is made from the variable k. The value Δk is subtracted to reduce the number of consecutive zeros. If “data amount function> compressed data amount cumulative value”, the adjustment value Δk is added from the variable k to increase the number of consecutive zeros. , “Data amount function = compressed data amount cumulative value”
If so, it is left as it is. As described above, in addition to the required processing such as discrete cosine transform processing, quantization processing, difference coding processing, and zero run length processing, the above-described processing is required, and in the case of a still image with sufficient time, there is no need. Although no problem occurs, in the case of a moving image such as a TV signal that requires real-time processing, there is a problem that the processing time is insufficient and normal encoding processing cannot be performed.

In view of the above-mentioned conventional technique, an object of the present invention is to perform real-time processing even in the case of a moving image such as a TV signal, and to set a predetermined amount of data of one field or one frame. An object of the present invention is to provide an encoding device capable of compressing the data amount.

[0007]

SUMMARY OF THE INVENTION To achieve the above object, the present invention provides one field or one frame of digital image data into a plurality of blocks each consisting of n × n pixels. Divide and perform discrete cosine transform for each block, and the n × n transform coefficients obtained by the transform are
Quantization is performed by dividing each of the threshold values of a quantization matrix composed of predetermined n × n threshold values. Then, one field or N frames (N is one field, or the number corresponding to the total number of blocks in one frame), or the same frequency component quantized for one frame, respectively. The transform coefficients of the low frequency component are sequentially subjected to the zero run length coding process from the high frequency component, and at the same time, the output data amount from the coding process is counted and the predetermined data amount is reached. In this case, the output data from the encoding process is switched to the image data end flag indicating that the image data of the field or frame is finished and output. ..

[0008]

By the discrete cosine transform and the quantization process, the image data of each block is converted into the components decomposed into the spatial frequency, and the conversion coefficient F (u, v) becomes high → u and v → high. The conversion coefficient F (u, v) at which the value of the frequency component becomes zero increases. As a result, the amount of data can be compressed by the zero run length process performed in the next stage.

At this time, the zero run length processing is carried out in units of one field or one frame.
Alternatively, the low-frequency components to the high-frequency components of the quantized transform coefficients forming the frame are sequentially processed and output. When the output data amount reaches the predetermined data amount, all the data thereafter is regarded as zero data and is switched to the image data end flag and output.

As described above, almost no processing time is required other than essential processing such as discrete cosine transform processing, quantization processing, zero run length processing, and even in the case of a moving image, one field or one frame is required. The data of the memory can be compressed into a predetermined amount of data.

[0011]

Embodiments of the present invention will be described in detail below with reference to FIGS. FIG. 1 is a block diagram showing an embodiment of an encoding circuit according to the present invention, FIG. 2 is a block diagram showing one configuration example when the present invention is applied to a magnetic recording / reproducing apparatus such as a VTR, and FIG. 3 is according to the present invention. 5 is a block diagram showing an embodiment of a decoding circuit, FIG. 4 is a table showing an example of a luminance signal quantization matrix for explaining the operation of the quantization circuit of FIG. 1, FIG.
1 is a table showing an example of a quantization matrix of a color difference signal for explaining the operation of the quantization circuit of FIG. 1, and FIG. 6 is a zigzag scan table for explaining the operation of the zigzag scan processing circuit of FIG. FIG. 7 is a table showing an example of a quantization result by the quantization circuit of FIG. 1, FIG. 8 is a diagram showing an example of an output signal from the zigzag scan processing circuit of FIG. 1, and FIG.
2 is a table showing an example of memory contents for explaining the operation of the memory and the memory control circuit of FIG. 1.

First, an outline of a digital VTR to which this embodiment is applied will be described with reference to FIG. In FIG. 2, the image signal supplied through the terminal 120 is converted into a digital signal by the A / D conversion circuit 12 with the quantization bit number M bits. This digital signal is appropriately data-compressed as described later by signal processing in the encoding circuit 13 according to the present invention. The output A of this encoding circuit 13 (hereinafter abbreviated as data A) is the digital processor 1.
The data are sequentially written in the memory 14 via 5. Memory 1
When writing to 4, the address code indicating the address thereof, a so-called parity code for code correction, and the like are added to each block of the data A having a predetermined number of bits, and are sequentially added to the memory 14. Written.

After the writing to the memory 14 is completed, the data A, the address code, and the parity code that are read out successively are read by the digital processor 15 as a synchronizing signal for finding the beginning of a block, and if necessary. Error detection code for code error detection is added and output.

The output data train B from the digital processor 15 is modulated into a code suitable for magnetic recording by the modulation circuit 16, and its output is sequentially read by the magnetic head 18 via the recording amplifier circuit 17. -Recorded on page 19.

Next, in the reproducing system, the signal reproduced from the magnetic tape 19 by the magnetic head 18 is appropriately reproduced and equalized by the reproducing equalizer 20, and then demodulated by the demodulation circuit 21 to the modulation circuit 16 described above. A signal B'similar to the input data train B is output. The output data sequence B'from the demodulation circuit 21 is subjected to data cueing for each block by the digital processor 15 based on the synchronization code and code error detection based on the error detection code. , Are sequentially written in the memory 14. The data written in the memory 14 is sequentially code-corrected by the digital processor 15 based on the parity code, and then,
The redundant code is sequentially removed, and the same data A'as the output data A from the above-mentioned encoding circuit 13 is output and supplied to the decoding circuit 22.

The M-bit digital signal decoded by the decoding circuit 22 is converted into an analog signal by the D / A conversion circuit 23 to restore the original image signal and output to the terminal 130.

Next, details of the encoding circuit 13 of the present embodiment will be described with reference to the block diagram shown in FIG. 1 and FIGS. In FIG. 1, the A / D conversion circuit 12 of FIG.
The image signal converted into the digital signal having the number of bits M is supplied to the encoding circuit 13 via the terminal 100 and input to the discrete cosine transform processing circuit (hereinafter abbreviated as DCT processing circuit) 1. In the DCT processing circuit 1, for each image data of one field of the input image signal, 1 block n × n pixels in the horizontal and vertical directions, in the present embodiment, 1 block 8 × 8 pixels k × It is divided into a plurality of 1 blocks and two-dimensional DCT is performed for each block.

DCT (Discrete Cosine Transform) is a kind of orthogonal transform in the frequency domain, and the input image data is f (i, j).
(I = 0, ~, 7, j = 0, ~, 7), DCT transform coefficient is F (u, v)
(U = 0, ~, 7, v = 0, ~, 7),

[0019]

[Equation 1]

Is defined by DCT obtained by this
The transform coefficient F (u, v) represents each component obtained by decomposing the input image data for one block into spatial frequencies.

In the DCT transform coefficient F (u, v), the coefficient F
(0,0) indicates a value (DC component) proportional to the average value of 8 × 8 pixels of the input image data f (i, j), and as u, v increases, the component of higher spatial frequency (AC Component). Further, since the normal image data has energy concentrated at low frequencies, the high frequency component of the DCT transform coefficient F (u, v) has a low value.

The output D from the DCT processing circuit 1
The CT transform coefficient F (u, v) is supplied to the quantization circuit 2 and quantized. The quantization circuit 2 quantizes the DCT transform coefficient F (u, v) for each block by dividing the DCT transform coefficient F (u, v) by each threshold value of a quantization matrix composed of 8 × 8 threshold values shown in FIGS. 4 and 5, for example. .. Here, FIG. 4 shows a quantization matrix for a luminance signal, and FIG. 5 shows a quantization matrix for a color difference signal. This quantization matrix has a large threshold value for dividing the DCT transform coefficient F (u, v) of the high frequency component in which u, v increases. Therefore, in the output from the quantization circuit 2, that is, in the divided and quantized DCT transform coefficient, most of the high frequency components are zero, as shown in FIG. 7, for example. This divided and quantized DCT transform coefficient is
Next, the zigzag scan processing circuit 3 performs zigzag scan processing.

The zigzag scan processing circuit 3 converts the conversion coefficient for each block into a one-dimensional number sequence in the order of the numbers shown in the zigzag scan table of FIG. 6 and outputs it.
The order of the numbers shown in the zigzag scan table in FIG. 6 is the direct current component (DC component) of the transform coefficients of each block.
It is configured such that the higher frequency components are sequentially provided from the. For example, assuming that the quantized transform coefficient shown in FIG. 7 is the nth block of the input image data of one field, the output "DCn" from the zigzag scan processing circuit 3 of this nth block. , ACn1, ACn2, ACn3, …………, AC
n63 ”is“ 97, -18, -23, -7, ... …… as shown in FIG.
, 0 ”. Then, the quantized transform coefficients for one field are sequentially written from the low frequency component for each block into the memory 4 having a capacity of at least one field or more.

After writing the quantized transform coefficients for one field in the memory 4, the transform signals of the same frequency component are sequentially read out from the low frequency components by the control signal from the memory control circuit 5. Be done. That is, as indicated by the dashed arrow in the table of memory contents in FIG. 9, first, the conversion coefficient of the DC component of each block is “DC1, DC2, DC3, DC4, ...
"...", then the first low-frequency component conversion coefficient in the order of "AC11, AC21, AC31, AC41, ...", and then the second low-frequency component conversion coefficient. AC12, AC22, AC32, AC42, ...
...... ”in that order, in the order of higher frequencies,“ AC
13, AC23, AC33, AC43, ..., AC14, AC24, AC34, AC44, ...
.., AC15, AC25, AC35, ........, ..., "," are read out from the memory 4 and supplied to the encoding processing circuit 6.

In the encoding processing circuit 6, the DC component conversion coefficients "DC1, DC2, DC3, DC4, ..., DCm, ..." By the differential encoding (DPCM) processing, the DC in the block immediately before is converted. The difference between the conversion coefficient of the component and the conversion coefficient of the AC component is encoded with a bit number smaller than M, and the conversion coefficient of the AC component “AC11, AC21, ..., AC12,
AC22, ……, AC13, AC23, ……, AC14, AC24, ……, ………… ”
For, the run length coding (zero run length coding process) is performed to compress the number of consecutive zero data. Subsequently, by the Huffman coding processing circuit 29 of the next stage, the differentially encoded DC component transform coefficient is Huffman coded by the difference bit number, and the AC component transform coefficient is run-length-coded continuous zero data. Two-dimensional Huffman coding is performed using the number data of data and the bit number data of effective coefficients. Huffman coding does not use the coefficient values themselves that are quantized for both the DC component and the AC component, but Huffman codes the number of bits required to represent the values. Then, in addition to the Huffman code, the value of the number of bits is added as additional information. For example, when the value of the quantized transform coefficient is 3 (decimal number), it is expressed as "000 ... 011" in binary number, but the number of bits 2 required to express this is Huffman coded and 2 bits Data "11" is added as an additional bit.

The encoded data, which is the output signal from the Huffman encoding processing circuit 29, is output as the data A through the data selector circuit 7 and the terminal 110, and at the same time, the data is output.
Is supplied to the data amount counting circuit 9. The data amount counting circuit 9 counts the amount of Huffman-encoded data output from the DC component and the low frequency component to the high frequency component from the Huffman encoding processing circuit 29. And the de
This data amount from the data amount counting circuit 9 is compared in level with the predetermined data amount from the predetermined data amount generating circuit 10 in the comparison circuit 11. The output signal from the comparison circuit 11 is a data
It is supplied to the data selector circuit 7 and "counted data amount>
When the "predetermined amount of data" is detected, that is, more coding data than the predetermined amount of data is Huffman coding processing circuit 2
When the output from 9 is detected, the data selector circuit 7 is switched from the a side to the b side, the image end flag from the image end data generating circuit 8 is selectively output, and the terminal 110 is output. Is output via.

Therefore, the image data is sequentially output from the DC component and the low frequency component to the high frequency component of the image data of one field through the terminal 110 and can be recorded in the digital VTR. When a predetermined amount of data corresponding to the amount of data per field is reached, the image end flag is selected and output. Then, the encoded data of the high frequency component of the field output from the Huffman encoding processing circuit 29 thereafter is all judged as zero data and ignored. As a result, the amount of image data after compression is 1 file.
It becomes a fixed amount in units of fields, and it is fed to the digital VTR.
It is possible to record in units of fields.

Then, as described above, the data A obtained by compressing the data amount in the encoding circuit 13 of FIG.
0 from the digital processor 15 of FIG.
Is written to the memory 14 via. Memory 14
The image data that is compressed and written is sequentially read through the digital processor 15 as described above,
A synchronization signal and an error detection code are added and the data B is output from the digital processor 15. This data B
Is recorded on the magnetic tape 19 by the magnetic head 18 via the modulation circuit 16 and the recording amplification circuit 17.

Next, details of the decoding circuit 22 of the present embodiment will be described with reference to FIG. At the time of reproduction, the data recorded as described above is reproduced by the magnetic head 18 from the magnetic tape 19 as described above with reference to FIG.
The reproduction equalizer 20 and the demodulation circuit 21 appropriately reproduce and demodulate, and the demodulation circuit 21 obtains a data output B ′ similar to the above-described data output B. This data output B'is sequentially written in the memory 14 via the digital processor 15. The digital processor 15 outputs the same output data as the output data A from the encoding circuit 13.
Data A'is supplied to the terminal 140 of the decoding circuit 22 shown in FIG.

In FIG. 3, the output signal A'from the digital processor 15 input from the terminal 140 is supplied to the Huffman decoding processing circuit 30 and corresponds to the Huffman coding processing in the Huffman coding processing circuit 29. Decoding processing is performed. Then, in the decoding processing circuit 31 in the next stage, differential decoding is performed on the DC component and zero run length decoding is performed on the AC component. The output from the decoding processing circuit 31 is the same quantized DC as the output signal from the encoding processing circuit 6.
This is a signal corresponding to the T conversion coefficient, and the conversion coefficient for one field is sequentially output from the DC component and the low frequency component to the high frequency component. Direction to the memory 24. At this time, if the image end flag indicating the end of one field of image data is detected, the memory control circuit 25 causes the amount of data to be written in the memory 24 to be one field. -Zero data is continuously written to the memory 24 in place of the detected image end flag until "64 x k x 1" corresponding to the amount of data.

After the signal corresponding to the quantized DCT transform coefficient for one field is written in the memory 24, the transform coefficient in the same block is changed from the low frequency component to the high frequency component by the memory control circuit 25. The data is sequentially read out for each block. That is, in the table of memory contents shown in FIG. 9, the DC components of the transform coefficients of the first block of the image of one field are sequentially displayed in the horizontal direction from "DC1, AC11, AC12, AC1".
3, AC14, ………… AC1-63, DC2, AC21, AC22, AC23, AC24, ……
…… AC2-63, DC3, AC31, AC32, AC33, AC34, ………… AC3-63,
DC4, AC41, AC42, AC43, AC44, ………… AC4-63, …………… "
Are read out in this order and supplied to the zigzag scan decoding processing circuit 26.

In the zigzag scan decoding processing circuit 26, the conversion coefficients supplied in the one-dimensional numerical sequence in the order of the numbers shown in the zigzag scanning table of FIG. 6 are supplied to the zigzag scanning processing circuit 3. Rearrangement in the order of the conversion coefficients, that is, 2 consisting of 8 × 8 conversion coefficients
Construct a dimensional block. Then, the inverse quantization circuit 27
For each transform coefficient of one block, for example, each threshold value of a quantization matrix composed of 8 × 8 threshold values shown in FIGS. 4 and 5 is multiplied to perform inverse quantization processing. Further, an inverse discrete cosine transform processing circuit In (IDCT processing circuit) 28, inverse discrete cosine transform defined by the following equation is performed.

[0033]

[Equation 2]

The inverse discrete cosine transform processing circuit 28 restores the image data corresponding to the original image data supplied to the encoding circuit 13 via the terminal 100,
It is output to the terminal 150.

Although the above embodiments have shown the case where the present invention is applied to a magnetic recording / reproducing apparatus such as a VTR, the present invention is not limited to this, and a so-called digital television receiver or the like is used. Needless to say, the present invention can be applied to all systems that transmit image signals in the form of digital signals.

In the above embodiment, the case where the output signal from the encoding processing circuit 6 is supplied to the Huffman encoding processing circuit 29 and the transform coefficient data subjected to the Huffman encoding processing is recorded is described. The present invention is not limited to this, and the present invention can be applied to the case where the Huffman coding processing circuit is not provided and the output signal from the coding processing circuit 6 is output as it is and the amount of data is counted. However, in this case, the Huffman decoding processing circuit 30 in the decoding circuit 22
Is deleted.

In the above embodiment, the case where the discrete cosine transform process is applied as the orthogonal transform process has been described, but the present invention is not limited to this, and other orthogonal transform process such as Hadamard transform process is used. Needless to say, the present invention can be applied to cases.

In the above embodiment, the case where the differential encoding process is performed on the DC component of the DCT transform coefficient in the encoding processing circuit 6 has been described, but the present invention is not limited to this.
The present invention can also be applied to the case where the zero run length encoding process is performed on all DCT transform coefficients.

In the above embodiment, the case where the input image of one field is divided into a plurality of blocks of 8 × 8 pixels has been described, but the present invention is not limited to this, and n × m pixels (n It goes without saying that the present invention can be applied to the case of dividing into a plurality of blocks each of which is an arbitrary natural number. Furthermore, the above-mentioned embodiment is one-feed.
Although the case where the image data of the field is divided into a plurality of blocks has been described, it is needless to say that the present invention can be applied to the case where the image data of one frame is divided into a plurality of blocks composed of n × m pixels. Yes.

[0040]

As described above, according to the present invention, the DC component and the low frequency component of the DCT transform coefficient for one field can be obtained without requiring a particularly complicated process other than the orthogonal transform process and the coding process. The coded data from the component to the high frequency component is counted, and when a predetermined amount of data is reached, the DCT transform coefficient of the higher frequency component beyond that is regarded as zero data and the image is displayed. By performing the data compression, the image data of one field can be compressed to a predetermined data amount. Therefore, in a magnetic recording / reproducing apparatus such as a digital VTR, it is possible to record on a predetermined number of tracks for each field, and it is possible to substantially increase the recording density of the tape, so that a small cassette can be used. Sufficient recording time can be secured, the operating speed of the hardware can be reduced, and the cost of the device can be reduced and the reliability can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an encoding circuit according to the present invention.

FIG. 2 is a case where the present invention is applied to a magnetic recording / reproducing apparatus.
It is a block diagram which shows an example.

FIG. 3 is a block diagram showing an embodiment of a decoding circuit according to the present invention.

FIG. 4 is an explanatory diagram showing a luminance signal quantization matrix for explaining the operation of the quantization circuit of FIG. 1;

5 is an explanatory diagram showing a quantization matrix for color difference signals for explaining the operation of the quantization circuit in FIG. 1. FIG.

6 is an explanatory diagram showing a zigzag scan table for explaining the operation of the zigzag scan circuit of FIG. 1;

7 is an explanatory diagram showing an example of a quantization result by the quantization circuit in FIG. 1. FIG.

8 is an explanatory diagram showing an example of an output signal from the zigzag scan processing circuit in FIG. 1. FIG.

9 is an explanatory diagram showing the contents of the memories of FIGS. 1 and 3. FIG.

[Explanation of symbols]

1 Discrete Cosine Transform Processing Circuit (DCT Processing Circuit) 2 Quantization Circuit 3 Zigzag Scan Processing Circuit 4, 24 Memory 5, 25 Memory Control Circuit 6 Encoding Circuit 7 Data Select Circuit 8 Image End Data Generation Circuit 9 Data -Data amount counting circuit 10 Predetermined data amount generation circuit 11 Level comparison circuit 13 Encoding circuit 22 Decoding circuit 26 Zigzag scan decoding processing circuit 27 Inverse quantization circuit 28 Inverse discrete cosine transform processing circuit (IDCT processing circuit) 29 Huffman Coding Processing Circuit 30 Huffman Decoding Processing Circuit 31 Decoding Processing Circuit

Claims (5)

[Claims] 1. An encoding device used in a device for sampling / quantizing an image signal to convert it into a digital signal for transmission or recording / reproduction, wherein one field or one frame converted into a digital signal. Image data is divided into a plurality of blocks each consisting of n × m pixels (n and m are arbitrary natural numbers), and means for performing an orthogonal transformation process for each block and n obtained by the above transformation process. Means for dividing xm transform coefficients by each threshold of a quantization matrix composed of predetermined n × m thresholds for quantization, and divided by one field or one frame unit. Transform coefficients quantized by the means of each block,
Means for performing zero run length encoding processing in which a conversion coefficient of zero from the conversion coefficient of the low frequency component in a predetermined order is used as an encoding unit; and means for counting the amount of data from the encoding processing means. When the "counting means result = predetermined amount of data" is detected by the means for comparing the counting means result with a predetermined amount of data, the encoding processing means A coding device, comprising: means for switching the output data to an image data end flag indicating that the image data of the field or frame has been finished and outputting the same. .. 2. The means for performing zero run length encoding processing in the predetermined order according to claim 1, wherein the transform coefficients of each block for one field or one frame are stored in blocks within the block. A means for converting the quantized transform coefficient from a low frequency component to a high frequency component into an n × m one-dimensional sequence and writing the sequence into a memory sequentially for each block, and N means (N is 1 field). Alternatively, the quantized transform coefficient of the same frequency component for one field or one frame composed of a number corresponding to the total number of blocks in one frame) is transferred from the low frequency component to the high frequency component. An encoding apparatus comprising: a unit for sequentially reading from a memory; and a unit for performing a zero run length encoding process on output data from the memory. 3. The conversion coefficient of a DC component according to claim 1 or 2, when the quantized conversion coefficient is subjected to a zero run length encoding process from a conversion coefficient of a low frequency component in a predetermined order. An encoding apparatus is provided with means for performing a difference encoding process for encoding the difference between the previous and previous DC component conversion coefficient. 4. The means for performing Huffman coding on the data subjected to the zero run length encoding process, or the data subjected to the differential encoding process and the zero run length encoding process according to claim 1. An encoding device comprising: a means for counting the amount of data from the means for Huffman encoding. 5. The encoding device according to claim 1, wherein the means for performing the orthogonal transform processing is configured by means for performing a discrete cosine transform processing.