JPH05316095A - Frame synchronization circuit - Google Patents

Abstract

PURPOSE:To reduce the synchronization establishing time by discriminating whether or not a pattern of one frame is a pseudo pattern so as to generate a control signal thereby reducing the probability of locking the pseudo pattern at detection of synchronization. CONSTITUTION:A frame pattern detection circuit 2 stores the result of comparison by one frame to a frame pattern detection result storage section 3. When a frame received next is compared, the result of detection of a preceding frame is simultaneously read and a control section of a discrimination section 4 compares the detection results of the same location in a frame to discriminate whether or not the pattern is a pseudo pattern and a pattern detection timing generating section 1 and the storage section 3 are controlled. Thus, the probability of locking the pseudo pattern is decreased and the time till synchronization establishment is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization circuit in a time division multiplex transmission device. When a frame is formed and transmitted in the time division multiplex transmission system, the device receiving the data needs to compare the frame synchronization patterns to establish the frame synchronization in order to know the position of the frame.

[0002]

2. Description of the Related Art In a conventional frame synchronizing circuit, the received pattern is compared with the received frame pattern in the frame pattern detecting circuit shown in FIG. The timing expected to be present is given from the detection timing generation circuit and pattern comparison is performed. If they do not match, pattern comparison is performed at the position shifted by 1 bit in the received data at the timing given by the detection timing generation circuit.

Synchronization is achieved by repeating this operation until the number of protection stages matches. At this time, there is a possibility that a pseudo pattern having the same pattern as the frame pattern will occur in the received data, and if there is a pseudo pattern in the comparison of the frame patterns, the operation is regarded as matching. However, since it is the pseudo pattern that has been pulled in, when the patterns are compared at that position, a mismatch will eventually be detected. In other words, when the pseudo pattern is pulled in, the number of times pattern comparison is performed at the position one frame later is increased, and the time until the synchronization is finally established becomes long.

[0004]

Therefore, in the conventional frame synchronization circuit, it takes a long time to detect the synchronization when it is necessary to detect the synchronization when the device is started up or when the line is momentarily cut off. There was a problem that it interfered with the subsequent processing. The present invention has been made in consideration of the above circumstances, and provides a frame synchronization circuit capable of shortening the synchronization establishment time by lowering the probability of pulling in a pseudo pattern when performing synchronization detection.

[0005]

FIG. 1 illustrates the principle of the present invention. In the figure, 2 is a frame pattern detection circuit, which compares the received data with a frame pattern and outputs a comparison result, 1 is a pattern detection timing generation unit, which is a timing for pattern comparison to the frame pattern detection circuit 2. 3 is a frame pattern detection result storage unit, which stores a pattern detection result for one frame, 4 is a determination unit, which determines whether the pattern is a pseudo pattern or not, and determines the frame pattern detection result storage unit 3
Also, a control signal is given to the pattern detection timing generation section 1, and 5 is a detection result storage section counter, which gives an address for indicating a position in the frame to the frame pattern detection result storage section 3.

When the frame pattern detection result storage unit 3 is configured to store the pattern comparison results of a plurality of frames, the probability of pulling in the pseudo pattern can be further reduced.

[0007]

According to the present invention, the result of comparison of one frame by the frame pattern detection circuit 2 of FIG. 1 is stored in the frame pattern detection result storage unit 3 and the next frame is compared. The detection result of the previous frame is read at the same time, and the control unit of the determination unit 4 determines whether the pattern is a pseudo pattern by comparing the detection results of the same position in the frame with each other, and the pattern detection timing generation unit 1 and the frame pattern detection unit. The result storage unit 3 is controlled. Therefore, since the probability of pulling in the pseudo pattern is lowered, it is possible to shorten the time until the synchronization is established.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail based on the embodiments shown in the drawings. The present invention is not limited to this. FIG. 2 is a block diagram of an embodiment of the present invention, showing a frame synchronization circuit. In the figure, 6 is a clock extraction circuit, which generates a clock from the data received from the transmission path. Reference numeral 1 is a pattern detection timing generation unit, which supplies a timing for pattern comparison to the frame pattern detection circuit.

A frame pattern detection circuit 2 compares the received data with the frame pattern and outputs the comparison result. A frame pattern detection result storage unit 3 stores the pattern detection result for one frame. Reference numeral 4 denotes a determination unit that determines whether the pattern is a pseudo pattern and provides a control signal to the frame pattern detection result storage unit 3 and the pattern detection timing generation unit 1. Reference numeral 7 is a front protection circuit, and 8 is a rear protection circuit, which has the same structure as the conventional one. In this way, the output of the frame pattern detection circuit 2 is input to the protection circuits 7 and 8 after the determination unit 4 determines whether the output is a pseudo pattern.

In such a configuration, FIG. 3 shows a frame pattern comparison procedure in the frame pattern detection circuit 2. The frame synchronization pattern is "FFFF"
And When performing pattern comparison with the frame synchronization pattern from the position "1" of the first frame, in the case of the present embodiment, first, all positions "1" to "8" of the first frame are compared and the result is the frame pattern. Write to the detection result storage unit 3. In this example, the first frame is "2,6"
Since the position is a pseudo pattern and the position of "7" is the frame bit position, it is written in the frame pattern detection result storage unit 3 that the patterns match at the positions of "2, 6, 7".

Next, for the second frame, pattern comparison is sequentially performed from the position of "1". At this time, at the same time, the comparison result of the first frame is read from the frame pattern detection result storage unit 3 and the judgment unit 4 determines whether the pattern is a pseudo pattern. That is, even if the patterns match in the second frame (the position of “3”), they do not match in the first frame, so it is determined to be a pseudo pattern.

Similarly, since the position of "5" in the second frame is also determined to be a pseudo pattern, it becomes possible to detect the position of the frame bit (the position of "7") in the second frame.
If the comparison result of a plurality of frame patterns is stored in the frame pattern detection result, the probability of pulling in the pseudo pattern can be further reduced.

[0013]

As described above, according to the present invention, it is possible to shorten the time until the frame synchronization is established, and it is necessary to detect the synchronization when the apparatus is started up or when the line is momentarily disconnected. When it occurs, the subsequent processing can be promptly performed.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is an explanatory diagram showing a frame pattern comparison example of the embodiment.

FIG. 4 is a block diagram of a conventional frame synchronization circuit.

[Explanation of symbols]

 1 pattern detection timing generation unit 2 frame pattern detection circuit 3 frame pattern detection result storage unit 4 determination unit 5 detection result storage unit counter

Claims (2)

[Claims] 1. A pattern detection timing generation unit (1) for supplying a timing for frame pattern comparison.
And a frame pattern detection circuit (2) that compares the received data with the frame pattern based on the timing supplied from the pattern detection timing generation unit (1), and a frame pattern detection result that stores the pattern detection result for one frame. It is judged whether it is a pseudo pattern with the storage unit (3),
Frame synchronization including a frame pattern detection result recording unit (3) and a pattern detection timing generation unit (1), and a determination unit (4) for instructing reading and writing of the frame pattern detection result and controlling the pattern detection timing. circuit. 2. The frame pattern detection result storage unit
2. The frame synchronization circuit according to claim 1, wherein (3) further comprises means for storing pattern comparison results of a plurality of frames for reducing the probability of pulling in the pseudo pattern.