JPH05315451A - Mask pattern design method - Google Patents

Mask pattern design method

Info

Publication number
JPH05315451A
JPH05315451A JP11866392A JP11866392A JPH05315451A JP H05315451 A JPH05315451 A JP H05315451A JP 11866392 A JP11866392 A JP 11866392A JP 11866392 A JP11866392 A JP 11866392A JP H05315451 A JPH05315451 A JP H05315451A
Authority
JP
Japan
Prior art keywords
wiring
mask pattern
signal wiring
signal
wirings
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP11866392A
Other languages
Japanese (ja)
Inventor
Katsutoshi Yokoyama
勝利 横山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP11866392A priority Critical patent/JPH05315451A/en
Publication of JPH05315451A publication Critical patent/JPH05315451A/en
Withdrawn legal-status Critical Current

Links

Landscapes

  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To acquire a mask pattern of good characteristics and to realize a short TAT and a small number of processes which are advantages of automatic mask pattern design. CONSTITUTION:A step 11 which is a process for making a specific signal wiring recognized and steps 12, 13 which are processes for deciding a wiring path by eliminating wiring of other signal wiring in proximity to the signal wiring recognized in the process 11 are included.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はマスクパタン設計方法に
関し、特に自動マスクパタン設計方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask pattern design method, and more particularly to an automatic mask pattern design method.

【0002】[0002]

【従来の技術】従来の集積回路の自動マスクパタン設計
方法では、図6に示す様に、他の配線からの影響を特に
嫌う配線61、例えばアナログ信号を伝播する配線に対
しては、何の対策も取られていなかった。この為、自動
マスクパタン設計ツールに与えた最小配線間隔で配線6
3,64が他の配線の影響を特に嫌う配線61の上,下
に傍接していた。さらに、その上,下に、配線62,6
5が傍接していた。
2. Description of the Related Art In the conventional automatic mask pattern designing method for an integrated circuit, as shown in FIG. 6, what happens to a wiring 61 which is particularly liable to be influenced by other wiring, for example, a wiring which propagates an analog signal? No measures were taken. For this reason, wiring 6 is performed with the minimum wiring interval given to the automatic mask pattern design tool.
3 and 64 are adjacent to the upper and lower portions of the wiring 61, which is particularly disliked by the influence of other wirings. Furthermore, above and below the wiring 62, 6
5 was next to me.

【0003】また、自動マスクパタン設計後に、図7の
様に、人手により他の配線からの影響を特に嫌う配線7
1に傍接する配線間を広げることにより、クロストーク
による誤動作を防止していた。
Further, after the automatic mask pattern design, as shown in FIG. 7, the wiring 7 which is particularly disliked by the influence of other wiring by hand is used.
By widening the wiring adjacent to 1, the malfunction due to crosstalk was prevented.

【0004】即ち、図7では、他の影響を特に嫌う配線
71と離間させて配線73,74があり、さらにその
上,下に傍接して配線72,75がある。
That is, in FIG. 7, there are wirings 73 and 74 which are spaced apart from the wiring 71 which is particularly unfavorable to other influences, and wirings 72 and 75 which are adjacent to the wirings 73 and 74 above and below.

【0005】[0005]

【発明が解決しようとする課題】図6の従来の方法で
は、他の配線の影響を特に嫌う配線61に傍接する配線
63,64が、GNDレベルからVDDレベル,または
VDDレベルからGNDレベルへとスイッチングした時
に、傍接する配線とのクロストークにより、他の配線か
らの影響を特に嫌う配線61の電位が変化してしまい、
電位が正しく伝播されずに誤動作するという欠点を有し
ていた。
In the conventional method shown in FIG. 6, the wirings 63 and 64, which are adjacent to the wiring 61 which is particularly affected by the influence of other wirings, change from the GND level to the VDD level or from the VDD level to the GND level. At the time of switching, the potential of the wiring 61, which is particularly disliked by the influence of other wiring, changes due to crosstalk with the wiring adjacent to it,
It has a drawback that the potential does not propagate correctly and malfunctions.

【0006】図7の方法では、人手作業が入ることによ
って、自動マスクパタン設計の短TAT,小工数という
利点が薄れるという欠点があった。
The method shown in FIG. 7 has a drawback in that the advantages of short TAT and small number of man-hours in the automatic mask pattern design are diminished due to the manual work.

【0007】本発明の目的は、前記欠点を解決し、傍接
する配線に影響を与えず、また人手作業を加える必要の
ないようにしたマスクパタン設計方法を提供することに
ある。
An object of the present invention is to solve the above-mentioned drawbacks, to provide a mask pattern designing method which does not affect the wiring adjacent to it and does not require manual work.

【0008】[0008]

【課題を解決するための手段】本発明のマスクパタン設
計方法の構成は、特定の信号配線を設計ツールに認識さ
せる第1の工程と、前記第1の工程で認識した信号配線
に傍接して他の配線が配置されることを排除して配線経
路を決定する第2の工程とを含むことを特徴とする。
The structure of the mask pattern designing method of the present invention has a first step of causing a design tool to recognize a specific signal wiring and a signal wiring recognized in the first step. A second step of determining a wiring route by excluding the arrangement of other wiring.

【0009】[0009]

【実施例】図1は本発明の一実施例のマスクパタン設計
方法を示すフロー図である。
FIG. 1 is a flow chart showing a mask pattern designing method according to an embodiment of the present invention.

【0010】図2は、図1のステップ12に対応してい
る平面図である。図3は、図1のステップ13に対応し
ている平面図である。
FIG. 2 is a plan view corresponding to step 12 of FIG. FIG. 3 is a plan view corresponding to step 13 of FIG.

【0011】図1において、本発明の一実施例の設計方
法は、ステップ11で他からの影響を特に嫌う配線の名
前や配線幅等を自動マスクパタン設計ツールへ与える。
この時の配線幅は、なるべく太くする。
In FIG. 1, the designing method of one embodiment of the present invention gives the automatic mask pattern designing tool the name of the wiring, the wiring width, etc. which are particularly unfavorable to the influence of others in step 11.
The wiring width at this time is made as thick as possible.

【0012】ステップ12に(図2)に於いて、他から
の影響を特に嫌う配線は、電源・GND配線と同様に幅
広配線として扱い、他の電源・GND配線と同様に接続
情報に基ずき結線する。
In step 12 (FIG. 2), the wiring which is particularly unfavorable to the influence from the other is treated as a wide wiring like the power supply / GND wiring, and based on the connection information like the other power supply / GND wiring. Connect the wires.

【0013】ステップ13(図3)では、結線が終了し
た後、電源・GND配線と同様に配線した他の影響を特
に嫌う配線を削除し、その削除した経路に信号線を配線
する。これにより、隣接配線との距離を離し、他の配線
からの影響を特に嫌う配線に対する他の配線からのクロ
ストークにより影響を防止することにより、誤動作を防
止する。
In step 13 (FIG. 3), after the wiring is completed, other wirings which are particularly disliked by the influence of the power supply / GND wirings are deleted, and the signal lines are arranged in the deleted paths. As a result, a malfunction is prevented by increasing the distance from the adjacent wiring and preventing the influence of the cross-talk from the other wiring on the wiring that particularly dislikes the influence of the other wiring.

【0014】図4は、本発明の第2の実施例を示したフ
ロー図である。図5は、図4のステップ42に対応して
いる平面図である。
FIG. 4 is a flow chart showing the second embodiment of the present invention. FIG. 5 is a plan view corresponding to step 42 of FIG.

【0015】図4において、本実施例は、ステップ41
で他からの影響を特に嫌う配線の名前や配線間隔等を自
動マスクパタン設計ツールへ与える。この時の配線間隔
は、なるべく多くする。
In FIG. 4, this embodiment uses step 41.
Gives the automatic mask pattern design tool the name of the wiring, the wiring interval, etc. The wiring interval at this time is made as large as possible.

【0016】ステップ42に於いて、図5に示すよう
に、他からの影響を特に嫌う配線は他の配線とは異なる
配線間隔、すなわちステップ41で与えられた広い配線
間隔をとりながら、他の配線と同様に接続情報に基ずき
結線する。これにより、他の配線の影響を特に嫌う配線
に対して、他の配線からのクロストークによる影響を防
止することにより、誤動作を防ぐ。
In step 42, as shown in FIG. 5, wirings which are particularly unfavorable to influences from other wirings have a wiring spacing different from that of other wirings, that is, a wide wiring spacing given in step 41, and other wirings. Similar to wiring, it is connected based on the connection information. This prevents malfunction due to crosstalk from other wirings with respect to wirings that are particularly susceptible to the influence of other wirings.

【0017】本実施例のマスクパタン設計方法は、特定
の信号配線を設計ツールに認識させる工程と、前記工程
で認識した前記信号配線に傍接して他の配線が配線され
る事を排除して配線経路を決定する工程とを含む。
The mask pattern designing method of this embodiment eliminates the step of causing a design tool to recognize a specific signal wiring and the wiring of another wiring adjacent to the signal wiring recognized in the step. And a step of determining a wiring route.

【0018】[0018]

【発明の効果】以上説明したように、本発明は、自動マ
スクパタン設計ツール上で他の配線からの影響を特に嫌
う配線に対して傍接配線との間隔を広くすることによ
り、自動マスクパタン設計後に人手によりマスクパタン
ノ修正が無くなり、短TAT,小工数が実現できる効果
を有し、また自動マスクパタン設計のアルゴリズムの変
更が少なくてすむという効果も有する。
As described above, according to the present invention, the automatic mask pattern design tool is designed to widen the space between the adjacent wiring and the wiring which is particularly unfavorable to the influence of other wiring. There is an effect that the mask pattern correction is manually eliminated after designing, a short TAT and a small number of man-hours can be realized, and there is also an effect that the change of the algorithm of the automatic mask pattern design is small.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例のマスクパタン設計方法
の手順を示すフロー図である。
FIG. 1 is a flow chart showing a procedure of a mask pattern designing method according to a first embodiment of the present invention.

【図2】図1の第1の工程後を示す平面図である。FIG. 2 is a plan view showing a state after the first step in FIG.

【図3】図1の第2の工程後を示す平面図である。FIG. 3 is a plan view showing a state after the second step in FIG.

【図4】本発明の第2の実施例の手順を示すフロー図で
ある。
FIG. 4 is a flowchart showing a procedure of a second exemplary embodiment of the present invention.

【図5】図4の第2の工程後を示す平面図である。FIG. 5 is a plan view showing a state after the second step in FIG.

【図6】従来の自動マスクパタン設計後を示す平面図で
ある。
FIG. 6 is a plan view showing a state after a conventional automatic mask pattern design.

【図7】従来のマスクパタン設計後に人手修正を施した
後の平面図である。
FIG. 7 is a plan view after a conventional mask pattern is designed and manually modified.

【符号の説明】[Explanation of symbols]

21,31,51,61,71 他の影響を特に嫌う
配線 22〜23,32〜33,52〜53,62〜65,7
2〜75 他の影響を特に嫌う配線に影響を与える配
線 11,12,13,41,42 ステップ
21, 31, 51, 61, 71 Wirings 22 to 23, 32 to 33, 52 to 53, 62 to 65, 7 which particularly hate other influences
2 to 75 Wiring that affects wiring that particularly hate other influences 11, 12, 13, 41, 42 Steps

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 特定の信号配線を設計ツールに認識させ
る第1の工程と、前記第1の工程で認識した信号配線に
傍接して他の配線が配置されることを排除して配線経路
を決定する第2の工程とを含むことを特徴とするマスク
パタン設計方法。
1. A first step of causing a design tool to recognize a specific signal wiring, and a wiring route which excludes the wiring arranged adjacent to the signal wiring recognized in the first step And a second step of determining the mask pattern designing method.
【請求項2】 前記第2の工程が、前記信号配線を幅広
配線で扱い、前記他の配線と同様に結線するステップ
と、前記結線が終了した後、前記信号配線を削除し、そ
の削除した経路に沿って、信号線を配線するステップと
を有する請求項1記載のマスクパタン設計方法。
2. The step of treating the signal wiring as a wide wiring in the second step, and connecting the signal wiring in the same manner as the other wiring, and deleting the signal wiring after the wiring is completed, and deleting the signal wiring. The method of designing a mask pattern according to claim 1, further comprising the step of wiring a signal line along the path.
【請求項3】 前記第2の工程が、前記信号配線では傍
接する配線との間隔を広くとり、前記他の配線と同様に
結線するステップを有する請求項1記載のマスクパタン
設計方法。
3. The mask pattern designing method according to claim 1, wherein the second step has a step of widening a space between the signal wiring and a wiring adjacent to the signal wiring and connecting the wiring in the same manner as the other wiring.
JP11866392A 1992-05-12 1992-05-12 Mask pattern design method Withdrawn JPH05315451A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11866392A JPH05315451A (en) 1992-05-12 1992-05-12 Mask pattern design method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11866392A JPH05315451A (en) 1992-05-12 1992-05-12 Mask pattern design method

Publications (1)

Publication Number Publication Date
JPH05315451A true JPH05315451A (en) 1993-11-26

Family

ID=14742139

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11866392A Withdrawn JPH05315451A (en) 1992-05-12 1992-05-12 Mask pattern design method

Country Status (1)

Country Link
JP (1) JPH05315451A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5478523A (en) * 1994-01-24 1995-12-26 The Timken Company Graphitic steel compositions

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5478523A (en) * 1994-01-24 1995-12-26 The Timken Company Graphitic steel compositions

Similar Documents

Publication Publication Date Title
US6586292B2 (en) Guard mesh for noise isolation in highly integrated circuits
JP2001177067A (en) Integrated circuit and its manufacturing method
JPH05315451A (en) Mask pattern design method
KR100373568B1 (en) Chip layout of semiconductor integrated circuit and method for verifying the same
JPH05235168A (en) Method for designing mask pattern
JP3925679B2 (en) Semiconductor device and semiconductor design device
JP2833886B2 (en) Automatic layout method for semiconductor integrated circuits
JP2827721B2 (en) Semiconductor integrated circuit mask pattern error detection method
JPH1174644A (en) Multilayer printed wiring board and automatic wiring method therefor
JP2990173B1 (en) Reference potential supply wiring method for semiconductor integrated circuit
JPH11312738A (en) Automatic wiring laying out method of semiconductor integrated circuit
JP3003151B2 (en) Design method of semiconductor integrated circuit
US7035780B2 (en) Methods of and apparatus for routing ranked critical conductors in ranked preferred tracks
JPH07153844A (en) Semiconductor integrated circuit device
JP2002366601A (en) Electronic circuit analyzer
JPH0774258A (en) Automatic layout method for semiconductor integrated circuit
JPH07249065A (en) Wiring path search method
JPH11176939A (en) Automatic wiring method
JPH1140672A (en) Integrated circuit, its pattern designing method and the designing device
JPH0590257A (en) Integrated circuit device
JPH03177066A (en) Semiconductor integrated circuit device
JP2001176972A (en) Layout method for semiconductor integrated circuit
JPH06209045A (en) Analog semiconductor integrated circuit device
JPS61161735A (en) Semiconductor integrated circuit device
JPH05109897A (en) Pattern designing method of semiconductor device and pattern of semiconductor device

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19990803