JPH05314669A - Device for identifying digital signal and method therefor - Google Patents

Abstract

PURPOSE:To inexpensively constitute an identification circuit for regenerating and receiving a digital signal without using a high speed semiconductor by reducing the clock frequency of the identification circuit. CONSTITUTION:With respect to the output signal of a regenerative signal amplifier 2, by a reproducing and equalizing circuit 3, the unit pulse of a signal transfer interval T is equalized to a prescribed reproducing waveform and reproduction and equalization for compensating the transmission characteristic of a tape head system to a frequency characteristic by which a digital signal is identified easily are executed. Subsequently, by a ternary identification circuit 4, the signal is identified in the period of two folds of a signal transfer interval T and decoded to its original digital modulating signal by an arithmetic circuit 6. In such a manner, an identification clock can be decreased to a half, the circuit configuration can be available without using a high speed semiconductor, the cost can be reduced, and also, the device becomes profitable in a manufacturing process and a design stage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a case where a digital signal is digitally modulated and then recorded in a memory or transmitted to a remote place, when the memory information is reproduced, or when it is received by a receiving side of a transmission circuit. , A digital signal identifying apparatus and method capable of identifying a modulated signal with a relatively low-speed clock, and particularly for identifying a digital modulated signal whose minimum inversion signal interval is twice the signal transfer interval (clock period). The present invention relates to a digital signal identifying device and an identifying method for increasing the identification interval.

[0002]

2. Description of the Related Art Conventionally, when a digital signal is recorded in a memory, digital modulation is performed to facilitate identification during reproduction. Further, when a digital signal is to be transmitted to a remote place, it is first converted into a digital modulated signal in order to increase the signal noise ratio and then transmitted. When the recording wavelength or the transmission wavelength is shortened, the recording or transmission characteristics are severely deteriorated. Therefore, recently, a modulated signal having a minimum inversion signal interval twice the signal transfer interval is often used. For example, a 1-7 code modulation scheme as shown in FIG. 7A corresponds to this. In all the following explanations, the recording signal is high level when it is "1", and the recording signal is low level when it is "0". 1
With the -7 code, the signal is digitally modulated so that it always becomes "1" after the signal "1" and always "0" after "0" with respect to the clock cycle (indicating one division). .. As a matter of course, there are cases where three "1" s continue, "0"
There are cases where four are continued, but when there is only one in each, none. As a result, the minimum inverted signal interval becomes a modulated signal that is twice the signal transfer interval (clock cycle). Further, the maximum number of consecutive pieces is eight. When 9 or more '0's continue, inconvenience occurs in various circuits, so the number is limited to 8. In this way, in the case of digital modulation, two or more identical signals are continued, so when converting an original digital signal to a digital modulated signal, as shown in FIG.
As shown in, 2-3 conversion and 4-6 conversion are performed. The 2-3 conversion is, for example, a case where the signal bit of “01” is converted to “000” and the signal bit of “10” is converted to “110”. Also, 4-6
The conversion is, for example, "11100" for "1010".
Converted to 0 ', and in case of' 0101 ',' 00001
This is the case when converting to 1 '. Conventionally, both of the 2-3 conversion and the 4-6 conversion are used in combination, and by converting by viewing with 2 bits or 4 bits, conversion to 1-7 code is performed. There is.

On the other hand, in the case of image data, one pixel has 8
Since it is what to allocate to bits,
For example, the 4-6 conversion or 8-12 conversion code disclosed in Japanese Patent Laid-Open No. 63-261576 is used. Also, an 8-14 conversion code having no DC component of the code string is used together with doubling of the minimum interval. 8-12 conversion is
As shown in FIG. 7C, the original digital signal '10111000' is changed to '1100' at the same time interval.
111000 'or' 111111000011 '
Is converted into a modulated signal. In order to eliminate the direct current component, if the number of '1's and'0's is the same within a predetermined interval, the average value becomes 0 level and the direct current disappears. When these modulated signals are reproduced from the recording device or received by the transmission circuit, the conventional identification circuit performs identification at a time interval equal to the signal transfer interval (clock cycle). That is, in FIG. 3A, “001111001111100” is the signal value synchronized with the clock, and the arrow indicates the time of identification. The conventional identification method is as shown in FIG.
Identification of "1" or "0" was performed at the same time interval as the clock cycle.

[0004]

As described above, in the digital modulation, the original digital signal is converted into a signal string of n bits (n> m, m, n is a positive integer) every m bits (for example, 8 bits). To do. At this time, even if the code inversion interval is the narrowest in the converted signal sequence, it is devised so as to be twice the signal transfer interval. For example, in FIG.
In the 1-7 code shown in (a), the code is inverted from 1 to 0 or from 0 to 1 only when the signal is "1".
The inversion interval is twice the clock cycle or more.
However, since n> m, the signal transfer interval of the modulated signal is naturally narrower than the original digital signal transfer interval. That is, in the 8-12 conversion of FIG. 7C, the 8-bit signal transfer time and the converted 12-bit signal transfer time are the same, so that the 12-bit signal transfer interval is naturally 8 bits. It becomes narrower than the signal transfer interval. Therefore, in the case where a signal speed for recording such a modulation method as in a high-definition digital VTR is high or a high-definition signal is transmitted, the identification clock becomes high in the conventional identification method, which is a serious problem in practical use. .. For example, when a video signal of high-definition broadcasting is directly converted into a digital signal, it is about 150 Mbps, and when the 8-14 conversion code is used, it is 260
It becomes a Mbps modulated signal. When such a high-speed modulated signal is identified by the conventional identification method, the identification clock also has a high speed of 260 Mbps. The cost of the circuit device using the high-speed clock is also high. When selling a high-definition digital VTR as a household device,
In order to cope with such high speed, circuit parts, boards, etc. become expensive. An object of the present invention is to solve such conventional problems and to reduce the clock frequency of the identification circuit, thereby making it possible to inexpensively configure the identification circuit for digital signal reproduction and reception without using a high-speed semiconductor. An object is to provide an apparatus and a method thereof.

[0005]

In order to achieve the above object, (a) the digital signal discriminating apparatus of the present invention reproduces or receives a digital modulation signal whose minimum inversion signal interval is twice the signal transfer interval. , A reproduction equalization circuit having at least a predetermined reproduction equalization characteristic and compensating the amplitude frequency characteristic and the phase frequency characteristic of the reproduced or received signal, and a signal transfer interval of 2 with respect to the output signal of the reproduction equalization circuit. A discriminating circuit for discriminating three values of a high level, a low level, and a zero-cross point in a discriminating clock cycle twice, and a computing circuit for computing a discrimination result of the discriminating circuit to obtain an original digital modulated signal. Is characterized by. Also,
(B) The digital signal identifying method of the present invention is the minimum digital signal identifying method for identifying a digital modulated signal on the reproducing side or the receiving side when the digital modulated signal is recorded or transmitted after being digitally modulated. In identifying a digital modulation signal whose inverted signal interval is twice the signal transfer interval, first, a unit pulse on the recording side of the signal transfer interval T is reproduced waveform g (t) or g '(t which is characterized by the following equation. ), The reproduced waveform g (t) or g '(t) is discriminated at a cycle twice the signal transfer interval by a discriminating circuit having a ternary discriminating level, and the discrimination result is calculated to calculate the original It is characterized in that it decodes the digitally modulated signal of. Note g (0) = 1, g (± T) = α, g (± nT) = 0 (n is a positive integer of 2 or more, α is an arbitrary number between 0 and 1)
Alternatively, g '(0) = 1, g' (± T) = α ', g' (± 2n
T) = 0 (n is a positive integer of 1 or more, α'is an arbitrary number between 0 and 1)

[0006]

In the present invention, in order to make the cycle of the identification clock twice the signal transfer interval, that is, the cycle of the number of identification times twice the clock cycle, first, the transfer characteristic of the tape head system is identified by the digital signal. Reproduction equalization is performed to compensate for the frequency characteristics that are easily affected, then the ternary level is discriminated by the discriminating circuit at a period twice the clock period, and finally the original digital modulated signal is decoded. That is, (a) the reproduction equalizer circuit reproduces the unit pulse on the recording side of the signal transfer interval T from the reproduction waveform g characterized by the following equation (1).
(T), or equalized to a reproduced waveform g '(t) characterized by the following equation (2). g (0) = 1 g (± T) = α g (± nT) = 0 (where n is a positive integer greater than or equal to 2) (T is a pulse width) (1) g '(0) = 1 g' (± T) = α'g '(± 2nT) = 0 (where n is a positive integer of 1 or more) (T is pulse width) ················································································ (2) In the case of, the reproduced waveform is the same, but at other values, the waveforms are completely different. (B) The discriminating circuit discriminates the output signal of the reproduction equalizing circuit with a ternary discriminating level and discriminates at a cycle twice the signal transfer interval. (C) The arithmetic circuit decodes the result identified by the identifying circuit into the original digital modulated signal. This allows
Since the identification clock can be lowered, the identification circuit can be constructed without using a high-speed semiconductor, and there are advantages such as low cost and easy design.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The principle and embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 2 shows the principle of the present invention, and is a diagram showing a unit pulse waveform on the recording side and its reproduction waveform, and FIG. 3 shows a reproduction signal waveform after reproduction equalization and an identification point in the present invention and the related art. FIG. FIG. 2A shows a unit pulse (pulse width T) on the recording side.
The reproduced waveform g (t) of the unit pulse is shown in (b). The solid line in FIG. 2B is the present invention, and the broken line is the conventional reproduction waveform. The reproduced waveform in the present invention is shown in FIG.
As is apparent from the above, the response is zero at the point ± 2T away from the center of the response waveform. That is, if the center of the reproduced waveform is 0 and its crest value is 1, g (0) =
1, g (± T) = α (α is an arbitrary value of 1 or less), g (±
nT) = 0 (in FIG. 2B, n is 2) holds (see the above-mentioned formula (1)). In the waveform of the solid line in FIG. 2B, the response value is zero at the points 0, 2T, 4T, and 6T. On the other hand, as shown by the broken line, the conventional reproduced waveform is zero at ± T, and the response value is zero at T, 2T, 3T, 4T, ... Since the conventional pulse waveform is steep, the frequency band is extremely wide. on the other hand,
Since the reproduced waveform of the present invention is a blunted waveform, the band required for reproduction equalization is narrowed and noise increase due to equalization is small compared to the conventional case. For the modulated signal '1', FIG.
When the recording or transmission method in which the response waveform shown in FIG. 3B is associated is adopted, the characteristic shown in FIG. 3B is given.

FIG. 3 (a) is a diagram showing conventional identification points based on signal intervals, and FIG. 3 (b) is a diagram showing identification points based on signal intervals according to the present invention. In FIG. 3, arrows indicate identification points, 1, 1, 1, 0, 0, ... Represent signal values, and mutual intervals between signal values indicate signal transfer intervals (clock cycles). In the modulation method to which the present invention is applied, the minimum signal inversion interval is 2T, but the signal inversion interval is kT, which is not only an even multiple of T but also an odd multiple. Here, k is a positive integer of 2 or more, and the maximum value is given by the modulation method. As described above, in the present invention, the minimum signal inversion interval is 2T.
The signal value is identified by the identification point every 2T using the modulated signal of. Therefore, as is clear from FIG.
The discrimination level of each discrimination point consists of three values of + H level or higher, -L level or lower, and zero cross point. The phases of the identification clock and the equalized output signal are synchronized so that the time of the zero cross point of the reproduction output becomes the identification point. Figure 3 (b)
Since the zero-cross point occurs at the clock boundary, the clock boundary is used as the identification point. The discrimination output is "11" at + H, "00" at -L, and "01" at the zero cross point. When such a discrimination result is given, the outputs of "11" and "00" are directly used as signal outputs in the arithmetic circuit. Also, '01'
In the case of output, considering that the minimum inversion signal interval of the modulated digital signal is twice the signal transfer interval, the zero-cross point identification result should be given according to the output before the zero-cross point output was obtained. It turns out that is possible. That is, if the previous signal output is "0", it is "0".
If it is 1'or '1', it is converted to '10'. The arithmetic circuit as described above restores the original digital modulation signal.

Next, a magnetic tape for using the identification method of the present invention will be considered. The high definition television (hereinafter referred to as HDTV) broadcasting system in Japan is called MUSE system, and when the signal is converted into a digital signal, a data transfer rate of about 130 Mbps per second is required. When this is divided into two channels and recorded in parallel and an error correction code is inserted to cope with a code error occurring in the tape head system, the total data rate is 150 Mbps and 75 Mbps per channel. Become. 8
The −12 conversion code is used as the recording code, and the converted bit rate is 75 × 12/8 = 112.5 Mbps. V
If the TR drum has a diameter of 26.7 mm and the drum rotation speed is 150 rpm, the head tape relative speed v is 1
It is 2.58 m / sec. In the 8-12 conversion code, the minimum signal inversion interval is the signal transfer interval T (= 1 / 112.5 Mbp).
s = 8.9 ns). Since the shortest recording wavelength λ is considered to be a length on the tape corresponding to twice the minimum signal inversion interval, it is given by λ = v × 2 × 2T. That is, λ is 0.45 μm. Recent so-called evaporation table
It is possible to record enough.

FIG. 1 is a signal system diagram of an identification circuit showing an embodiment of the present invention, and FIG. 4 is a diagram showing an amplitude frequency characteristic including a tape head system and a reproduction equalization circuit. In FIG. 1, 1 is a magnetic head, 2 is a reproduction signal amplifier, 3 is a reproduction equalization circuit, 4 is a ternary identification circuit, 5 is a clock component extraction circuit, and 6 is an arithmetic circuit. The magnetic head 1 reproduces a signal from a recorded magnetic tape (not shown) and outputs the reproduction signal to the reproduction signal amplifier 2. The reproduction signal amplifier 2 amplifies the input reproduction signal, and the reproduction equalization circuit 3
Output to. The reproduction equalization circuit 3 compensates the amplitude frequency characteristic and the phase frequency characteristic of the tape head system. The output signal of the reproduction equalization circuit 3 is input to the ternary identification circuit 4 and the clock component extraction circuit 5. The ternary discriminating circuit 4 discriminates whether each of 2T is a + H, -L, or zero-cross point, and inputs its output signal to the arithmetic circuit 6.
The arithmetic circuit 6 performs arithmetic processing according to the output value of the three-value discrimination circuit 4 and outputs the original modulated digital signal. The clock component extraction circuit 5 receives the output of the equalization circuit 3 and
An identification clock at 2T intervals is generated and supplied to the ternary identification circuit 4. The reproduction equalization circuit 3 reproduces a unit pulse on the recording side at the signal transfer interval T by a reproduction waveform g'characterized by the above equation (2).
Equalize to (t). g '(0) = 1 g' (± T) = α 'g' (± 2nT) = 0 (where n is a positive integer of 1 or more) ... (2) To this end, the amplitude frequency characteristic including the tape head system and the reproduction equalization circuit 3 is 4 / T (= 2) as shown in FIG.
It has a response of 0.5 at a frequency of 8.125 MHz), and has a response n (fh) on the high frequency side and a response n on the low frequency side.
It is assumed that (fl) becomes the following expression (3). n (fh) + n (fl) = 1 (3) In the characteristics of FIG. 4, the response on the high frequency side is between 4 / T and 3 / T. And the response on the low frequency side is in the range between 4 / T and 5 / T. Since the characteristic between 3 / T and 5 / T is a straight line, the high frequency side and the low frequency side equidistant from 4 / T are 1's complements to each other.

FIG. 5 is a detailed configuration diagram of the identification circuit in FIG. 1, and FIG. 6 is a signal waveform diagram of each part in FIG. In FIG. 5, 4 is a ternary discrimination circuit, 6-1 is an exclusive-or (Ex-OR) circuit, 6-5 is an AND circuit, 6-2 and 6-3 are inverters, and 6-4 is a switch circuit. , 6-6 are latch circuits. The identification clock CK at the 2T (= 17.8 ns) interval generated by the clock component extraction circuit 5 is supplied to the identification circuit 4. As shown in FIG. 6 (E ₀ ), a high level corresponding to '11' data,
Low level corresponding to '00' data, and '10'
Or the zero cross level corresponding to '01' data is 3
It is detected by the value discrimination circuit 4. The three-value discrimination circuit 4 is 2
It is composed of two binary discrimination circuits 4-1 and 4-2, and respective discrimination levels S1 and S2 are obtained from a predetermined power source (not shown) and variable resistors 4-3 and 4-4. That is, in the output signal E ₀ of the equalization circuit 3, the variable resistor 4 is at a high level.
Since the potential level is higher than any of the potential levels of -3 and 4-4, the result of the subtraction by the identification circuits 4-1 and 4-2 is + output, and the two outputs O1 and O2 are both "1".
Further, at the low level of E ₀ , the variable resistors 4-3, 4-
Since it is lower than any of the potential levels of 4, the identification circuit 4
The result of subtraction at -1, 4-2 becomes the output of (-),
The two outputs O1 and O2 are both output “0”. When E ₀ is a zero cross, the discrimination circuit 4-1 is "0",
4-2 becomes an output of "1". Ex-OR circuit 6-1
Becomes high level when the outputs O1 and O2 of the two identification circuits 4-1 and 4-2 do not match, that is, when the zero-cross level is detected. The other input of the AND circuit 6-5 is the output D2 (6-8 terminal) of the latch circuit 6-6 and holds the data one clock before the identification time. Therefore, in the AND circuit 6-5, when the data one clock before is "1" and the zero-cross level is detected, the output C becomes high level. This means that when the zero-cross point is identified in FIG. 3B, it is '10' if + H at the immediately preceding identification point and '01' if -L. Can be determined.

In FIG. 5, the switch circuit 6-4 has 2
A switch circuit for simultaneously switching system signals,
Two input signals are switched by one system. As shown in FIG. 5, the output O1 and its inverted output (the output of the inverter 6-2) and the output O2 and its inverted output (the inverter 6-3).
Output) at the same time. The control signal of the switch circuit 6-4 is given from the AND circuit 6-5,
When the output of the circuit 6-5 is at the high level, the switch circuit 6-4 selects the inverted output. Therefore, when the zero-cross level is not detected, the identification circuits 4-1 and 4
-2 outputs O1 and O2 are sent to the latch circuit 6-6 as they are, and identification result data D1 and D2 are obtained. On the other hand, when the data one clock before is "1" and the zero-cross level is detected, the output C of the AND circuit 6-5 becomes high level, so the switch circuit 6-4 selects the inverted output. , D1 = 1, D2 = 0. The zero-cross level is detected and the data one clock before is detected.
When the data is "0", the output of the AND circuit 6-5 becomes low level, so the outputs O1 and O2 pass through the switch circuit 6-4 as they are, and D1 = 0 and D = 1. Become.
In FIG. 6, CK is a clock signal, and O1 and O2 are output signals of the two identification circuits 4-1 and 4-2. Here, the second and third clocks are “11”, and the fourth signal is The clock has a zero cross level of '01'.
A and B indicate the output of the Ex-OR circuit 6-1 and the previous discrimination level, and A = A at the third clock.
Since “0” and B = “1”, the output of the AND circuit 6-5 becomes a low level and cannot be switched by the switch circuit 6-4, and the output D of the discrimination circuit of the next fourth clock.
1 and D2 are "1" and "1". Further, at the fourth clock, A = '1' and B = '1', so C =
It becomes "1", and the switch circuit 6-4 switches to the inverted output, and the output D of the discrimination circuit of the next fifth clock.
1 and D2 are "1" and "0".

In the embodiment, the case of the reproduction equalized waveform given by the above equation (2) is explained. Compared to the equalization characteristic shown in FIG. 4, when equalization is performed with the low frequency component being emphasized, the equalization characteristic given by equation (1) is obtained.
The opening degree of the reproduction eye pattern becomes large. That is, in the reproduction eye pattern, in order to observe waveform distortion and jitter, the oscilloscope is synchronized with the clock signal,
When a signal to be measured is added to the vertical axis and observed, a square is displayed in the case of an ideal waveform, but if there is waveform distortion, it is rounded and the openness of the central blank part becomes small. The identification circuit after the equalization circuit is exactly the same. As described above, the present invention realizes the method of halving the clock frequency of the identification circuit by utilizing the property that the minimum inverted signal interval of the modulated digital signal is twice the signal transfer interval. The method can be applied without depending on the reproduction equalization method. Further, it goes without saying that the present invention can be applied to any signal as long as it is a digital modulation signal having the above-mentioned properties.

[0014]

As described above, according to the present invention,
Since the identification point of the identification circuit can be made twice the signal transfer interval and the clock frequency can be halved, the circuit can be configured without using a high-speed semiconductor and the cost can be reduced. In particular, when integrating the identification circuit into an integrated circuit, it is advantageous not to use a special high-speed semiconductor in the manufacturing process and the designing process.

[0015]

[Brief description of drawings]

FIG. 1 is a signal system diagram of an identification circuit showing an embodiment of the present invention.

FIG. 2 is a diagram of a unit pulse waveform on the recording side and a reproduction waveform thereof showing the principle of the present invention.

FIG. 3 is a diagram showing reproduced signal waveforms and identification points after reproduction equalization according to the present invention and the related art.

FIG. 4 is a diagram showing an amplitude frequency characteristic including a tape head system and a reproduction equalization circuit.

5 is a detailed signal system diagram of the identification circuit in FIG.

6 is a diagram showing a signal waveform of each part in FIG.

FIG. 7 is an explanatory diagram showing a conventional 1-7 code and various conversion codes.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 magnetic head 2 reproduction signal amplifier 3 reproduction equalization circuit 4 3-value discrimination circuit 5 clock component extraction circuit 6 arithmetic circuit 4-1 and 4-2 partial discrimination circuit 4-3 and 4-4 variable resistor 6-1 Ex- OR circuit 6-2, 6-3 Inverter 6-4 Switch circuit 6-5 AND circuit 6-6 Latch circuit 6-7, 6-8 Identification circuit output terminal CK Clock signal E ₀ Equalization circuit output

Claims (2)

[Claims] 1. A digitally modulated signal having a minimum inverted signal interval twice the signal transfer interval is reproduced or received, and therefore has at least a predetermined reproduction equalization characteristic, and the amplitude frequency characteristic and phase of the reproduced or received signal. A reproduction equalization circuit for compensating for frequency characteristics, and an output signal of the reproduction equalization circuit is discriminated between three levels of a high level, a low level, and a zero-cross point in an identification clock cycle twice the signal transfer interval. The discrimination circuit and the discrimination result of the discrimination circuit are calculated,
And a calculation circuit for obtaining an original digitally modulated signal. 2. A digital signal identifying method for identifying a digital modulated signal on a reproducing side or a receiving side when the digital modulated signal is recorded or transmitted after digitally modulating the digital signal, and the minimum inversion signal interval is signal transfer. In identifying a digitally modulated signal that is twice the interval, first the unit pulse on the recording side of the signal transfer interval T is equalized to a reproduced waveform g (t) or g '(t) characterized by the following equation. , The reproduced waveform g (t) or g '(t) is discriminated by a discriminating circuit having a three-level discriminating level at a cycle twice the signal transfer interval, and the discrimination result is calculated to obtain the original digital modulated signal. A method for identifying a digital signal, which comprises: g (0) = 1, g (± T) = α, g (± nT) = 0 (n is a positive integer of 2 or more, α is an arbitrary number between 0 and 1)
Alternatively, g '(0) = 1, g' (± T) = α ', g' (± 2n
T) = 0 (n is a positive integer of 1 or more, α'is an arbitrary number between 0 and 1)