JPH05314012A - Write protecting method for memory - Google Patents

Abstract

PURPOSE:To provide a write protecting method of a memory in which hardware need not be changed at the time of changing a write protection area and besides, there is no substantial burden on the hardware due to the number of the write protection areas. CONSTITUTION:The memory 2 is divided into arbitrary areas, and information to show the propriety of the write of every divided area is stored beforehand in the memory 3 in the form of a list, and at the time of the write, this stored information is referred to in accordance with a write address, and the propriety of the write corresponding to the address is determined.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory write protection method for a microcomputer, for example.

[0002]

2. Description of the Related Art In a microcomputer, RAM
Even in the case of a memory such as (random writing / reading memory) capable of freely writing, it is sometimes desired to protect (prohibit) writing in a specific area to protect the already stored contents. For this purpose, various write protection methods have been put into practical use. FIG. 5 shows an example thereof. In the figure, 61 is a microprocessor and 62 is a memory, and the memory 62 is accessed by an address given from the microprocessor 61 via an address bus 64. Data to be written in the memory 62 or data read from the memory 62 is transmitted via the data bus 65.

The upper bits of the address bus 64 are connected to one input terminal of the comparator 63. To the other input terminal of the comparator 63, an address setter 67 having the same number of bits, which is formed by using a wiring switch or the like, is connected,
The comparator compares the multi-bit signal provided thereby with the upper bits of the address input from the address bus 64. If they match, the comparator gives an error signal to the interrupt terminal of the microprocessor 61 via the signal line 66. For example, address 00000000 (hexadecimal) ~
To protect the 00FFFFFF (hexadecimal) area, do not give the upper 8 bits of the address bus to the comparator 63.
The address setter 67 sets 00000000. Then, the write address is 00000000 (hexadecimal) to 00FFFFFF (16
If it is a decimal number, the upper two digits 00 (hexadecimal) (= 0000 0000) matches the set value of the address setter 67, and an error signal is issued.

[0004]

In the case of the conventional method as described above, when it is necessary to change the protection area, it is necessary to change the set value of the address setter 67. Therefore, the wiring is changed and the parts are removed. Therefore, there is the annoyance that it is necessary to reattach it. Further, when a plurality of protection areas are provided, it is necessary to provide a plurality of address setting devices, which is a factor of reducing the space utilization efficiency. The present invention has been made in order to solve such a problem, and a protected area is stored in advance, and the write address is compared with the protected area so that the hardware cannot be changed when the protected area is changed. An object of the present invention is to provide a write protection method for a memory that does not require it and does not substantially increase the hardware load due to the number of protection areas.

[0005]

According to a write protection method of a memory according to the present invention, write enable / disable information defined for each memory area arbitrarily divided is stored in a predetermined area of the memory. The permission / prohibition information is referred to by the write address, and the permission / prohibition of writing is determined according to the permission / prohibition information corresponding to the area to which the write address belongs.

[0006]

The writing permission / prohibition information is stored for each divided area in the predetermined area. At the time of writing, the permission / prohibition information is referred to by the write address, and if writing is impossible, an error signal is issued to the microprocessor 61. When changing the area to be write-protected, the permission / prohibition information in the predetermined area is changed.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing the embodiments. FIG. 1 is a block diagram of a main part of a microcomputer to which a memory write protection method according to the present invention is applied. In the figure, 1 is a microprocessor and 2 is a first memory, which are connected by an address bus 4 and a data bus 5. The data bus 5 transmits 32-bit data D31 to D0. The address bus 4 is the lower 20 bits of the 32-bit address A31 to A0 output by the microprocessor 1.
A19 to A0 are transmitted to the memory 2. Reference numeral 3 denotes a second memory, which is used for storing list information of areas to be write-protected, that is, the above-mentioned write enable / disable information.

FIG. 2 is a map showing the address spaces of the memories 2 and 3, and the memory 2 has a range of 00000000 (hexadecimal) ...
00FFFFFF (hexadecimal) and FE000000 (16
Hex) to FE0003FF (hexadecimal) are assigned. Thus, the lower 10 bits A9 to A0 of the address output from the microprocessor 1 are input to the gate 6, and the 10 bits of the addresses A23 to A14 are input to the gate 7, respectively. Both gates 6 and 7 are controlled to be opened / closed by an output signal of an address decoder 8 which will be described below, and the gate 6 is opened when writing to the memory 3 and the gate 7 is opened when the memory 2 is selected. Each address is assigned to the address input terminals MA9 to MA0 of memory 3.
Give to.

The upper 22 addresses are sent to the address decoder 8.
Bits A31 to A10 are input. The address decoder 8 outputs the signal CS1 bar when the input address is FE000000 (hexadecimal) to FE0003FF, that is, when it is the address assigned to the memory 3, and the input address is 00000000 to 00.
When it is FFFFFF, that is, when it is the address assigned to the memory 2, the signal CS2 bar is output. Signal CS1 bar is the low-active open / close control terminal of gate 6, memory 3
Write enable terminal WE and one input terminal of a negative logic OR gate 9. The signal CS2 bar is
It is given to the other input terminal of the gate 9, the low active open / close control terminal of the gate 7, and the low active chip select terminal CS bar of the memory 2. The output of the OR gate 9 is given to the low active chip select terminal CS bar of the memory 3.

The data to be written in the memory 3 is given from the microprocessor 1, but the data is 1/0 1-bit data indicating whether writing is possible, and the data bus D31
One bit of D0 to D0 is connected to the data input terminal D _in of the memory 3. The data read from the memory 3 is of course also 1-bit data. The data output terminal D _out for outputting this data is connected to one input terminal of the NAND gate 10 of negative logic. The microprocessor 1 outputs a signal indicating whether writing / reading to / from the memory 2 from the terminal R / W bar, and supplies this to the terminal R / W bar of the memory 2 and the other terminal of the NAND gate 10. .. The signal directs a read when high and a write when low. NAND
The output of the gate 10 is designed to give a high level as an error signal to a predetermined terminal of the microprocessor.

Next, the operation of storing the write protection information as shown in FIG. 3 in the memory 3 will be described. Information about whether or not writing is possible for the area from 00000000 (hexadecimal) to 00003FFF (hexadecimal) in the memory 2 is stored in the address 000 (hexadecimal) of the memory 3
It will be written in. In this example, data "1" which allows writing is written. Memory 2 00004000 (hexadecimal) ~ 00007F
The memory availability information for the FF (hexadecimal) area is writable.
It will be written to address 001 (hexadecimal) of. Data "0" which prohibits writing is written here. In this way, the data writing area 00000000 (hexadecimal) to 00FFFFFF (hexadecimal) of the memory 2 is divided into a plurality of (1024 in the embodiment) areas, and the addresses 000, 001 of the memory 3 assigned to each of the areas. 002 ... 3
The write enable is written in the FF as “1” and the prohibition is written as “0”.

The row (a) of FIG. 4 shows addresses A31 to A0 output from the microprocessor 1 when writing to the memory 3. In the figure, X represents 0 or 1. Since the contents of these 32 bits are FE000000 (hexadecimal) to FE0003FF (hexadecimal), the address decoder 8 outputs the signal CS1 bar. As a result, the chip select terminal CS bar and the write enable terminal WE bar of the memory 3 become active, and writing to this becomes possible. Addresses A9 to A0 of the lower 10 bits indicated by X are given to address input terminals MA9 to MA0 of the memory 3 from the gate 6 opened by the signal CS1 bar. Therefore, this address 00 0000 0000 ~ 11 1111 1111,
In other words, the data input terminal D at the address from 000 to 3FF (hexadecimal)
The value of that given to the _in "0" or "1" is to be written.

Next, the address configuration for writing to the memory 2 is as shown in line (b) of FIG. Memory 2
Since the address is 00000000 (hexadecimal) to 00FFFFFF (hexadecimal), 8 bits of A31 to A24 are "0". Memory 3
The lower 10 bits A23 to A14 to be given to each specify each area of the memory 2 divided into 1024 areas.
It can be represented by X corresponding to the column (a). Bits A13 to A0 on the lower side indicate the addresses in the divided areas of the memory 2. This is represented by Y. When writing to the memory 2, the microprocessor 1 issues such an address signal from the terminals A31 to A0, the data to be written from the terminals D31 to D0, and the low level from the terminal R / W bar. Emit a signal. The upper bits A31 to A10 of the address signal are input to the address decoder 8. Since this content is the upper 22 bits of the address 00000000 (hexadecimal) to 00FFFFFF (hexadecimal) of the memory 2, the signal CS2 bar is output.
Therefore, the chip select terminals CS of the memories 2 and 3 are both active, and the open / close control terminal of the gate 7 is active.

Then, the gate 7 is opened and the address A23 is set.
.About.A14 is input to the memory 3, and the data of the corresponding address is read from the data output terminal D _out . Now
If A23 to A14 are 0000 0000 00, the address 000 (16
Data) "1" is read. Then, the output of the NAND gate 10 is low level, and the microprocessor 1 does not recognize this as an error signal. On the other hand, if the address signals A23 to A14 are 0000 0000 01, the memory 3
Data “0” at address 001 (hexadecimal) of
Given to gate 10. Since the other input of the NAND gate 10 is low level at this time, its output becomes high level, and the microprocessor 1 recognizes this as an error signal and stops the process for writing to the memory 2.
As a result, write protection for that address is performed.

[0015]

As described above, according to the present invention, the write protection area can be arbitrarily set by the data to be written in the memory 3. Therefore, there is no need to change the write-protected area on the hardware, and there is no trouble.
Further, write protection for a plurality of areas only requires an address to store them, and there is no substantial increase in hardware load due to the increase in the protected areas. Further, according to the present invention, the write protected area can be easily designated or changed by software, which is convenient for separating work at the time of software development and failure occurrence. The present invention has excellent effects.

[Brief description of drawings]

FIG. 1 is a block diagram of a main part of a microcomputer to which a method of the present invention is applied.

FIG. 2 is a map showing an address space of memories 2 and 3.

FIG. 3 is a conceptual diagram showing stored contents of a memory 3.

FIG. 4 is an explanatory diagram of each address when writing to the memory 3 and writing to the memory 2.

FIG. 5 is an explanatory diagram of a conventional write protection method.

[Explanation of symbols]

 1 Microprocessor 2 Memory 3 Memory 4 Address Bus 6 Gate 7 Gate 8 Address Decoder

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kuniichi Sawai 1-3-3 Shimaya, Konohana-ku, Osaka City, Sumitomo Electric Industries, Ltd. (72) Inventor Fumio Kamijo 1006 Kadoma, Kadoma, Osaka Prefecture Address Matsushita Electric Industrial Co., Ltd. (72) Inventor Tadaaki Kamiyama 1006 Kadoma, Kadoma-shi, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Masahiro Ikeuchi 10th, Hanazono Dodocho, Ukyo-ku, Kyoto Omron Corporation (72) ) Inventor Seiji Fujimoto, Omron Co., Ltd. 10 Hanazono Dodo-cho, Ukyo-ku, Kyoto

Claims (1)

[Claims] 1. A method of protecting writing to a part of a memory, wherein writability information defined for each area of the memory that is arbitrarily divided is stored in a predetermined area of the memory, and a write address is set. A write protection method for a memory, wherein the permission / prohibition information is referred to and the permission / prohibition of writing is determined according to the permission / prohibition information corresponding to the area to which the write address belongs.