JPH0531228B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a brake release signal generating device for a digital disc player.

[Technical background of the invention]

This invention provides a digital audio disk (DAD) which converts an audio signal into digital PCM as a digital data signal and records it on a disk using the unevenness of pit rows, and a digital disk player that detects the pit rows of this disk and reproduces the original audio signal. being developed.

Incidentally, on such a disc, pit rows are recorded using a constant linear velocity method (CLV). For this reason, when a pit row is tracked by an optical pickup element, for example, the disk is driven such that its rotational speed decreases as the optical pickup element moves from the inner circumference to the outer circumference of the disk. To control this rotational speed, a synchronization signal synchronized with each frame of the digital data signal is extracted from the frequency component of the digital data signal read from the disk, and the disk motor is rotated so that the frequency of this synchronization signal becomes a predetermined frequency. This is done by controlling the speed.

Here, if the above synchronization signal cannot be obtained, such as when the motor starts rotating or the pick-up element is moved at high speed, the period (one period or half period) of the digital data signal read from the disk is ) is detected and the rotation of the disk motor is controlled so that this value becomes a predetermined value, thereby making the linear velocity of the pit row constant.

In such a digital disc player, the rotating disc motor is stopped by driving the disc motor with a brake pulse having a polarity opposite to the drive pulse of the disc motor. In such a configuration, if the brake torque is not released at a predetermined timing after applying brake torque to the disc motor, the disc motor will rotate in reverse.

Conventionally, a circuit as shown in FIG. 6 has been used as a circuit for generating a brake release signal for releasing the brake torque. In the figure, disk 1
1, the frequency generator (FG) 13 generates a pulse P ₁ every time the motor 12 that rotationally drives the motor 1 rotates once.
N pieces (N is a positive integer) are output. This output pulse P ₁ (see Fig. 7a) is divided into 2 by the frequency dividing circuit 14.
The frequency is divided into a pulse _P2 shown in FIG. 7b.
The timing generating circuit 15 generates a clear pulse CL for the counter 16 (see FIG. 7c) and a latch pulse LP for the latch circuit 17 (see FIG. 7d) in synchronization with this pulse _P2 . When the counter 16 is cleared by the clear pulse CL, it counts the reference clock CK from the reference clock generation circuit 18. This count value is latched in the latch circuit 17 in accordance with the latch pulse LP. As a result, the count value for about one cycle of the clear pulse CL, in other words, the count value for about two cycles of the output pulse _P1 of the frequency generator 13 is latched in the latch circuit 17. When the count value N latched in the latch circuit 17 (see FIG. 7e) becomes larger than a predetermined value, that is, when the rotational speed of the motor 12 becomes low, the decoder 19 sends a brake release signal S _A ( (see Figure 7f).

[Problems with background technology]

However, the above configuration requires a frequency generator 13 and a circuit dedicated to generating a brake release signal, resulting in a problem that the number of components of the player increases.

[Purpose of the invention]

The present invention has been made to address the above-mentioned circumstances, and an object of the present invention is to provide a brake release signal generating device that does not require a frequency generator and in which most of the circuit can also be used as a motor rotational speed control device. With the goal.

[Summary of the invention]

This invention is configured to obtain a brake release signal when the period of the digital data signal read from the disk continues to be greater than a predetermined value for a predetermined period of time.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention. The output of an optical pickup element 23 for reading digital data signals from a disk 21 rotationally driven by a motor 22 is given to a recording signal processing circuit 24. A recording signal processing circuit 24 extracts a digital data signal (EFM signal) _SD from the output of the pickup element 23. This digital data signal S _D is input to a period detection circuit 25, and the time length of each period is measured using a reference clock CK having a period T from a reference clock generation circuit 26. The period detection circuit 25 then sets the time length of each period to a predetermined value MT (where M is a positive integer).
The pulse P _a is outputted as a high level in the following cases, and as a low level in the case of (M+1)T or more. In addition,
The details of the operation of this period detection circuit 25 will be described later.

The output pulse P _a of the period detection circuit 25 is applied to the RS flip-flop circuit 27 as a reset input R. As a set input S of this RS flip-flop circuit 27, a pulse LP ₁ outputted from a timing generation circuit 28 is applied.

The timing generation circuit 28 is the recording signal processing circuit 2.
The digital data signal S _D output from 4 is frequency-divided by N ₁ (for example, N ₁ =128) to obtain pulses LP ₁ and LP ₂ (see FIGS. 2a and 2b). Furthermore, the timing generation circuit 28 converts these pulses LP ₁ and LP ₂ into N ₂ (for example, N ₂
=16) to obtain pulses LP ₃ and LP ₄ (see Figure 2 c, d). Here, the pulses LP ₂ and LP ₄ are delayed in phase by about one cycle with respect to the pulses LP ₁ and LP ₃ , respectively.

The output of the RS flip-flop circuit 27 and pulse LP ₂ are input to an AND circuit 29, and the output of this AND circuit 29 is input to the RS flip-flop circuit 30.
It becomes the reset input R of The Q output of the RS flip-flop circuit 30 is connected to the D flip-flop circuit 31.
This becomes the D input. RS flip-flop circuit 30
The set input S of the D flip-flop circuit ₃₁ is a pulse LP3, and the clock input CK of the D flip-flop circuit 31 is a pulse
It is LP ₄ . And D flip-flop circuit 3
The Q output of 1 becomes the brake release signal S _A.

The operation in the above configuration will be explained. The RS flip-flop circuit 27 is set to the pulse LP ₁ , and the RS flip-flop circuit 30 is set to the pulse LP1.
The set state is achieved by pulse _LP3 output at the same timing as _LP1 .

Here, if the RS flip-flop circuit 30 is held in the set state over one period T _B of the pulse LP ₃ , the D flip-flop circuit 30 is turned on at the timing of the pulse LP ₄ , which is approximately one period later in phase than the pulse LP ₃ . The Q output of No. 31 becomes high level. D
The Q output of the flip-flop circuit 31 is used as a brake release signal as described above, and the brake torque is released at the timing when this Q output becomes high level.

The reason why the RS flip-flop circuit 30 maintains the set state for one cycle T _B of the pulse LP ₃ is as follows.
During this period, the output pulse P _a of the period detection circuit 25 is always at a low level. That is, R.S.
The flip-flop circuit 27 is brought into a set state by the pulse LP ₁ , and one period of this pulse LP ₁
If the output of the period detection circuit 25 is at a low level during _TA , the RS flip-flop circuit 27 maintains the set state. As a result, the AND circuit 29
closes the gate, and pulse LP ₂ closes this AND circuit 2
9, the RS flip-flop circuit 30 is never reset. If this state continues for _N2 times the period T _A , that is, the period T _B , the Q output of the RS flip-flop circuit 30 is kept at a high level during this period, so the Q output of the D flip-flop circuit 31 becomes the pulse LP ₄ It reaches a high level at the timing of .

On the other hand, if the output pulse Pa of the period detection circuit 25 becomes high level even once during one period T _A of the pulse LP ₁ , that is, one period of the digital data signal becomes MT during the period T _A. If the following conditions occur even once, the RS flip-flop circuit 2
7 is kept in the reset state until the next pulse _LP1 is output. As a result, at the timing of generation of pulse _LP2 , the output of RS flip-flop circuit 27 becomes high level and the gate of AND circuit 29 is open, so that RS flip-flop circuit 30 is reset by pulse _LP2 . Once the RS flip-flop circuit 30 is reset, it will not be put into the set state until the next pulse LP ₃ is output, so the Q output of the D flip-flop circuit 31 becomes high level at the timing of the generation of the pulse LP ₄ . Never.

In this way, in the circuit shown in FIG. 1, a state in which one cycle of the digital data signal becomes less than or equal to MT does not occur even once in _N1 cycles _TA of the digital data signal _SD .
Furthermore, when this continues _N2 times, a brake release signal S _A is output. That is, when the time length of each cycle is equal to or greater than (M+1)T over N ₁ ×N ₂ cycles of the digital data signal S _D , the brake release signal S _A is output.

Now, if the minimum period of the digital data signal when the disk 21 rotates normally is 6T, and M is 22, then
When 6T expands to 23T or more, that is, when the rotation period of the disk 21 becomes 23/6=3.8 times the normal time, the brake release signal S _A is output.

Here, the configuration of the period detection circuit 25 will be explained using FIG. 3.

In FIG. 3, pulses CLA and SPA input to terminals 1a and 2a are signals synchronized with the rise of the digital data signal S _D as shown in FIGS. 4a, b, and c. The pulses CLB and SPB input to the terminals 3a and 4a are signals synchronized with the falling edge of the digital data signal _SD , as shown in FIG. 4a, d, and e.

The counter 5a is cleared by the pulse CLA and the reference clock given from the terminal 6a (Fig. 4).
Count fCK. Similarly, counter 7a is cleared by pulse CLB and counts reference clock CK. That is, the counter 5a measures one cycle from one rising edge to the next rising edge of the digital data signal S _D , and the counter 7a measures one cycle from one falling edge to another falling edge. Judgment circuits 8a and 9a output high-level signals if the time-converted outputs of the count values of counters 5a and 7a, respectively, are less than or equal to MT.

By the way, in the mode in which one period of the digital data signal S _D is measured, the pulse CNT applied to the terminal 10a is at a high level. As a result, the pulses SPA and SPB are connected to the gate circuits 11a and 11a, respectively.
12a to AND circuits 13a and 14a. In this case, if the time length of one cycle of the digital data signal S _D is less than or equal to MT, the outputs of the determination circuits 8a and 9a are at high level at the timing of the pulses SPA and SPB, so the pulses SPA and SPB are output from the AND circuits 13a and 13a, respectively. 14a. The output of these AND circuits 13a and 14a is an OR circuit 15a.
It is applied to the RS flip-flop circuit 27 as an output pulse P _a of the period detection circuit 25 through the RS flip-flop circuit 27 to reset it.

Although the case where the time length of a cycle is measured in units of one cycle has been described above, it may be measured in units of half a cycle. In this case, the pulse CNT applied to the terminal 10a is set to low level. As a result, the pulses SPA and SPB pass through the gate circuits 12a and 11a, respectively, and the AND circuits 14a and 13.
given to a. If the half cycle from the rise to the fall of the digital data signal S _D is less than or equal to MT, the pulse SPB passes through the AND circuit 13a since the output of the determination circuit 8a becomes high level. On the other hand, pulse SPA is a digital data signal S _D
If the half cycle from falling to rising is less than MT, the output of the discrimination circuit 9a becomes high level, and therefore passes through the AND circuit 14a.

In this way, even when measuring a half period of the digital data signal S _D , the period detection circuit 25 shown in FIG. 1 measures two types of half periods, just as it measures one period. ing.

Now, if the minimum anti-period of the digital data signal S _D when the disk 21 rotates normally is 3T and M=22,
When 3T expands to 23T or more, that is, when the rotation period of the disk 21 becomes 23/3=7.7 times the normal time, the brake release signal S _A is output.

Incidentally, in a digital disc player, when the motor 22 starts rotating or when the pickup element 23 is moving at high speed, the motor 22 is rotated so that the period (one period or half period) of the reproduced digital data signal becomes a predetermined value. As mentioned above, the linear velocity of the pit row is kept constant by controlling the rotational speed of the pit row.

The brake release signal generating device of the present invention can be constructed very simply by using the rotational speed control device for keeping the linear velocity of the pit row constant.

This will be explained below. FIG. 5 is a circuit diagram showing the configuration of the rotation speed control device. Period detection circuit 3
When the maximum cycle of 1 is greater than or equal to KT (T is one cycle of the output clock CK of the reference clock generation circuit 32), the output pulse _Pb becomes high level. Pulse LP ₁ output from the timing generation circuit 33,
LP ₂ , LP ₃ , LP ₄ are the previous timing generation circuit 28
This is the same as the output from .

The RS flip-flop circuit 34 is reset by the pulse _LP1 , and is set to the set state if the maximum period exceeds K(T) even once during the period _TA . R.S.
The flip-flop circuit 36 is set by the pulse LP ₃ , and if the output of the RS flip-flop circuit 34 is at a high level even once during the period T _B , the pulse LP ₂ passes through the AND circuit 35, so that it is reset. The Q output of the RS flip-flop circuit 36 is applied to the D flip-flop circuit 37 as the D input. The fact that the Q output of this D flip-flop circuit 37 is at a high level means that the digital data signal
This means that the maximum period of S _D is greater than or equal to KT. When the period of the digital data signal becomes extremely long due to noise or the like, the RS flip-flop circuit 34 is mistakenly set to the set state, but when it returns to normal, the RS flip-flop circuit 34
The output becomes low level. Noise etc. is periodic
The RS flip-flop circuit 36 is not set unless it continues during T _B , reducing the influence of noise.

Note that the rotational speed of the motor 22 is controlled by the Q output of the D flip-flop circuit 37.

Here, if the output pulse of the period detection circuit P _b is halved, this inverted output becomes a high level below (K-1)T, so this halved output is used as the output of the period detection circuit 25 in FIG. Can be used in place of pulse P _a .

Therefore, the period detection circuit 25 in FIG.
Since the cycle detection circuit 31 and the timing generation circuit 33 shown in FIG. 5 can be used together, the circuits actually required to realize the brake release signal generation device shown in FIG. 1 are three flip-flop circuits and an AND circuit. You only need one.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a brake release signal generating device that does not require a frequency generator and can also use most of the circuit as a motor rotational speed control device.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of FIG. 1, and FIG. 3 is a specific configuration of the period detection circuit in FIG. 2. A circuit diagram showing an example, Fig. 4 is a timing chart to explain the operation of Fig. 3, Fig. 5 is a circuit diagram to explain the effect of Fig. 1, and Fig. 6 is a conventional brake release. FIG. 7 is a circuit diagram showing the signal generating device, and is a timing chart for explaining the operation of FIG. 6. 21...Disk, 22...Motor, 23...
Pickup element, 24... recording signal processing circuit,
25... Period detection circuit, 26... Reference clock generation circuit, 27, 30... RS flip-flop circuit, 29... AND circuit, 28... Timing generation circuit, 31... D flip-flop circuit.

Claims (1)

[Claims] 1. In a digital disc player that reads the digital data signal from a disc on which the digital data signal is recorded, it is detected whether the cycle of the digital data signal read from the disc is larger than a predetermined value. a period detection means; a second detection means for detecting whether or not a detection output indicating that the period is greater than the predetermined value is continuously obtained from the period detection means over a predetermined period; When a detection result is obtained from the detection means that a detection output indicating that the period is greater than the predetermined value is obtained continuously over the predetermined period,
A brake release signal generating device comprising brake release signal generating means for generating a brake release signal for releasing the brake torque of the motor that rotationally drives the disk.