JPH05304635A - Picture storage circuit and video processor using same - Google Patents

Abstract

PURPOSE:To freely select the number of horizontal scanning lines, and the number of dots in a horizontal direction by storing picture data for one field in a memory when the number of display dots on the screen of a display corresponds to the storage capacity of the memory, or it is less than the storage capacity. CONSTITUTION:A dot clock is continuously counted in one field period by using a single counter, or making two counter single. Then, at the time of designating an address by using the count value, the number of horizontal and vertical sampling dots is not limited by 2 to the (n)th power just like a conventional picture storage device by using the two horizontal and vertical address counter constitution, so that the increase of the number of wiring can be prevented even when the number of the horizontal scanning lines is increased. This device is constituted of a memory 2, address counter 4, serial/parallel converter 6, and parallel/serial converter 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image storage circuit and a video processing apparatus using the same, and more particularly to a camera-integrated video capable of synthesizing a title image into a general image and recording and reproducing it. The present invention relates to improvement of a title memory in a video processing device such as a video camera).

[0002]

2. Description of the Related Art FIG. 8 is a block diagram centering on a title control circuit of a video camera as a specific example of a video processing apparatus. There are mainly two types of methods for combining the title image 50 with the general image 60 in the video camera 10. In the first method, the image 60 is recorded on a video tape by the recording circuit 70, the video tape is rewound and reproduced, and the title image 50 is photographed while confirming the reproduced image of the image 60. The image 50 is synthesized. According to this method, an appropriate title image can be superimposed and edited at an arbitrary timing after confirming the content that has been shot and recorded. However, due to the high cost at present, it is limited to devices for enthusiasts.

In the second method, first, the title image 50 is photographed, digitized as a still image, temporarily stored in the memory 20 composed of SRAM or the like, and later, the image 60 is displayed.
During shooting, the title image stored in the memory 20 is read out according to an instruction from the photographer, and the image 60 is displayed.
To superimpose and record. Although this method reduces editing flexibility but does not cost much, it is becoming popular in almost all devices for general users. Therefore, in the following description, a video camera adopting the second method will be described as a specific example.

The video camera 10 has a title control circuit 40, and a microprocessor (MPU) 30 around this circuit 40 for monitoring and controlling the entire video camera.
And a memory 20 for storing the title image 50 and an image 60.
And a recording circuit 70 for synthesizing the title image 50 and recording it on a video tape. First, the operation of storing the title image 50 in the memory 20 in the block diagram of FIG. 8 will be described. The title picture 50 is the video camera 10.
Of the title control circuit 4 as an input signal I for a title, which is captured by an image capturing unit (not shown) of FIG.
Sent to 0. The title control circuit 40 receives an instruction according to the signal CC from the microprocessor 30 according to the operation of the photographer, generates the address signal AD and the data signal DT from the title input signal I, and stores the memory 20 by the memory control signal MC. It controls and stores the title image 50 in the memory 20. By storing the title image 50 in the memory in this way, it becomes possible to insert the title into the captured image at any time thereafter.

Next, while the image 60 is being photographed, the title image 5
The operation when superimposing 0 will be described. When the photographer presses the title insertion switch while a signal (not shown) of the image 60 is sent to the recording circuit 70 and recorded on the video tape, the microprocessor 30 responds to this operation by the title insertion switch. The image reading instruction is output as a signal CC. In response to this instruction, the title control circuit 40 generates the address signal AD in synchronization with the signal obtained by photographing the image 60, and controls the memory 20 by the memory control signal MC. Then, the data of the title image 50 stored in the memory 20 is read from the memory 20 as a data signal DT, and the title output signal TT restored and generated from this data is sent to the recording circuit 70. In response to this, the recording circuit 70 combines this signal G with the signal of the image 60 and records it on the video tape.

Incidentally, the title control circuit 40 and the memory 20 are usually treated as an integrated image storage circuit. FIG. 5 shows the main part of this image storage circuit. In addition,
In the figure, the portion corresponding to the memory 20 is referred to as the memory 2. The memory 2 includes a horizontal address counter 41 and a vertical address counter 4 which are part of the title control circuit 40.
2 receives image data write / read addresses. Here, CLK is a dot clock. The dot clock has a cycle corresponding to the horizontal scanning time of each display dot on the display screen. The dot clock CLK is input to the horizontal address counter 41, and the horizontal synchronizing signal HD is applied to the vertical address counter 42. A horizontal synchronizing signal HD is applied to the reset input (RESET) of the horizontal address counter 41, and a vertical synchronizing signal VD is applied to the reset input (RESET) of the vertical address counter 42.

Note that R / * W of the memory 2 is a read / write control terminal, and is a read / write control signal R / * W.
Is entered. When the image data is stored, this signal causes the memory 2 to be in the write state, and when the image data is read out, this signal causes the memory 2 to be in the read state.

6A and 6B are timing charts showing the operation of the image storage circuit. FIG. 6A is a dot clock CLK, FIG. 6B is a vertical synchronizing signal VD, and FIG. 6C is a horizontal synchronizing signal HD. ) Indicates each signal (each digit signal) A1, A2, ... Of the horizontal address line, and (E) indicates the first signal (first digit signal) V0 of the vertical address line. And t1, t2
Is a horizontal address reset time, t3 is a vertical address reset time , and "H" is a HIGH level.
"L" represents a LOW level.

As is clear from the configuration of FIG. 6 and this timing chart, the horizontal address counter 41 counts the dot clock CLK, and the counted value becomes the horizontal address Ah of the memory 2, and the counted value is horizontally synchronized. It is reset by the signal HD. The vertical address counter 42 counts horizontal scanning lines, and the counter value becomes the vertical address Av of the memory 2. The count value of the vertical address counter 42 is reset by the vertical synchronizing signal. In this way, in the memory 2, the horizontal and vertical addresses are specified by the dot clock and the counting of the horizontal scanning lines, and the image data representing the title is stored for each dot at the specified address.

[0010]

In such an image storage circuit, a horizontal address count 41 and a vertical address counter 42 are provided as means for designating addresses of the memory 2, and horizontal and vertical addresses are provided. Are configured with two separate counters. Therefore, the number of samples in the horizontal direction and the number of samples in the vertical direction are limited to 2 to the n-th power corresponding to the number of digits of these counters that perform digital counting.

FIG. 7 shows a screen stored in this image storage circuit. H is horizontal, V is vertical, Nn is NTS
The number of horizontal scanning lines in the C method is usually about 243 lines. , Np is the number of horizontal scanning lines in the PAL system, which is normally 28.
It is about 0 lines. A square represents one dot. As shown in the figure, regarding the number of screen scanning lines, PAL system and NTSC
Comparing with the system, the number of horizontal scanning lines in the PAL system is large, and the number of sampling in the vertical direction is larger than that in the NTSC system. That is, in the PAL method, the number of vertical samplings exceeds the count value 256 of the 8-digit counter. Therefore, the number of digits in the counter is increased by one, and NTSC
The number of vertical address lines is increased by one as compared with the method. Therefore, the storage capacity of the memory 2 for storing images is also increased. Storage capacity in NTSC system 6
When the 4 kBIT memory 2 is used as it is for the PAL system, the PAL system has a shortage of storage capacity, resulting in a loss of a stored image. To prevent the loss of the stored image, set the storage capacity or PAL corresponding to the broadcasting system.
It is necessary to install a storage means having a storage capacity corresponding to the system. Such setting of the storage capacity or storage means causes an increase in design cost and manufacturing cost.

An object of the present invention is to provide an image storage circuit capable of suppressing an increase in the number of wirings due to an increase in the number of horizontal scanning lines. Another object of the present invention is to provide an image storage circuit capable of preventing the loss of stored images due to lack of storage capacity.
Still another object of the present invention is to provide a video processing device capable of preventing the loss of a stored image due to lack of storage capacity.

[0013]

The features of the present invention include a memory for storing image data and a so-called dot clock as a clock having a cycle corresponding to the horizontal scanning time of each display dot on the display screen of the display. The counter is provided with a counter which counts this clock and is reset by a vertical synchronizing signal, and which designates the address of the memory by the count value, so that the image data for one field displayed on the display is continuously displayed. The image data for one field stored in the memory is continuously read according to the clock.

[0014]

By doing so, if the number of display dots on the screen of the display corresponds to the storage capacity of the memory or is less than or equal to the storage capacity, the image data for one field can be stored in the memory. it can. Therefore, the number of horizontal scanning lines and the number of horizontal dots in one field can be freely selected within the storage capacity of the memory.
Therefore, even if the standard television system is different and the number of horizontal scanning lines is different, the image data for one field can be stored without changing the memory.

The number of samplings in the horizontal direction can be easily changed by the period (frequency) of the dot clock, so that it is easy to change the number of samplings according to the number of horizontal scanning lines. If the number of sampling dots in the horizontal direction is reduced, the number of horizontal scanning lines can be increased, and image data for one field can be stored without increasing the storage capacity. As a result, even in the PAL system, which has more horizontal scanning lines than the NTSC system,
The memory used in the method can be used without replacing it with another memory having a large capacity. In such use, it is possible to prevent the loss of the stored image as in the conventional case. Moreover, in this case, if there is a vertical address counter, it is necessary to increase the number of wirings on the vertical address counter side as the number of horizontal scanning lines increases, but this is not necessary.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the image storage circuit shown in FIG. 1, a memory 2 is installed as a storage means for storing image data representing a title, and an addressing input side of this memory 2 is a counting means as an addressing means. An address counter 4 as a means is installed.

The address counter 4 is composed of a conventional horizontal address counter and vertical address counter as a single counter. Dot clock CLK, ENABLE (enable) at its clock input terminal
A horizontal blanking signal HBLK is applied to the terminal and a vertical synchronizing signal VD is applied to the reset terminal, and the dot clock CLK is continuously counted for one field period of the image. This count value represents the access address of the memory 2. as a result,
The memory 2 sequentially stores the image data in units of one field period, or the image data is read from the image data.

Serial image data SD is input to the input section (I / O) of the memory 2 as data to be stored when the memory 2 is in the writing state, and serially from this point when the memory 2 is in the reading state. The data SD is read. The part indicated by the dotted line is an embodiment in the case of storing the image data in 1-byte units, and such a configuration is usually better. When storing in 1-byte units, the lower 3 bits of the address counter 4 do not become the address signal of the memory 2. The upper digit from the address line A3 is used as an address signal for accessing the memory 2. Next, an embodiment in this case will be described.

A serial / parallel converter 6 as a first data conversion means for converting data to be stored is connected to an input section of the memory 2. A dot clock CLK is added to the serial-parallel converter 6 together with the image data SD as serial data. The serial-parallel converter 6 synchronizes with the dot clock CLK to generate serial data in 8-dot clock units. Image data SD is converted into image data PD which is parallel data. Therefore, the image data PD, which is parallel data, is stored in the memory 2 at the address designated by the address counter 4. In this case, the lower 3 bits of the counter 4 are invalid for accessing the memory 2.

Further, since the image data PD which is parallel data is stored in the memory 2, the image data PD read from the memory 2 is of course also parallel data when the data is read. Therefore, memory 2
A parallel / serial converter 8 serving as a second data conversion means is connected to the input / output unit of (2) in order to reproduce the read parallel data as serial data again. A dot clock CLK is added to the parallel-serial converter 8 together with image data PD as parallel data read from the memory 2 whose address is designated by the address counter 4. Therefore, the parallel / serial converter 8 reads the image data PD as parallel data in units of 8 dot clocks from the memory 2 in synchronization with the dot clock CLK, converts it into serial data in units of dot clocks, and outputs it as a read output DO. Is output.

In both the former embodiment and the latter embodiment in which data is stored in byte units, in each image storage circuit, the storage capacity of the memory 2 is M, the number of horizontal samplings is Hs, and the vertical direction. The capacity M of the memory 2 is selected so that Hs × Vs ≦ M (1) when the sampling number is Vs. If this condition is satisfied, the same memory can be used by the above circuit even if Hs and Vs are different, as in the PAL system and the NTSC system.

Next, the operation will be described with reference to FIG. FIG. 2A shows the dot clock CLK, which is used by the address counter 4
Is a unit of counting. In the latter embodiment, the dot clock CLK is the basis of the synchronization timing of data conversion of the serial / parallel converter 6 and the parallel / serial converter 8.

The address counter 4 has a dot clock CLK as a clock input, a vertical synchronizing signal VD shown in FIG. 2B as a reset input, and a C shown in FIG. 2 as an enable input.
The horizontal blanking signal HBLK ("L" significant) shown in is added. Then, the address counter 4 continuously counts the dot clock CLK through one field, and as shown in FIG. 2D, data (each digit data) A0, A1, A2 of the address line of the memory 2 is obtained. A3 ...
Is obtained. In the latter embodiment, the digits after A3 are address signals.

As can be understood from this timing chart, the address counter 4 operates the dot clock C during the period between the vertical synchronizing signal VD and the next vertical synchronizing signal VD.
LK is counted, the count value becomes an address (each digit value = A0, A1, A2, A3 ...), and the count value is 0, 1, 2, 3, ..., m + 1, m + 2, m
Change to +3, m + 4, ... At this time, A0, A
The level of each signal of 1, A2, A3 ..., As shown in the figure, changes to "H", "L" according to each value.

By the way, since "H" of the horizontal blanking signal HBLK is used as the enable signal here,
The counter 4 operates only when this signal is "H". Therefore, while the horizontal blanking signal HBLK is "L", the count value of the counter 4 indicating the last dot position of horizontal scanning is held. For example, the count value “m + 1” of the first line is not incremented during the horizontal blanking period even when receiving the dot clock CLK. Therefore, the image data of the entire screen is stored at consecutive addresses. In other words, the image data is stored corresponding to the length of the horizontal scanning line, and the image data in one field is continuously stored for the number of horizontal scanning lines. As a result, the data stored in the memory 2 is 1
It depends on the product of the horizontal sampling number Hs and the vertical sampling number Vs inside the field, and does not depend on the respective numerical values.

Therefore, for example, the NTSC system and PA
In order to be shared with the L system, it suffices to simply provide a memory having a storage capacity corresponding to the number of dots for one field of these systems, and it becomes a title memory capable of storing image data of both systems. Specifically, the storage capacity M of the memory 2 may be determined as follows.

Hns × Vns ≦ M in NTSC system, where Hns: horizontal sampling number, Vns: vertical sampling number Hns × Vns ≦ M in PAL system, Hps: horizontal sampling number, Vps: vertical sampling number Thus, if the horizontal and vertical samplings continue, the number of horizontal and vertical samplings is not limited to 2 to the nth power.

FIG. 3 shows an image display area corresponding to the memory 2, where a0 ... aE represent addresses on the screen. In FIG. 3, HD is a horizontal synchronizing signal, HBLK is a horizontal blanking signal, and VD is a vertical synchronizing signal. 2 and 3 are displayed in correspondence with each other, the address line data A0, A1, A2, A3 ...
Each address value 0, 1, 2, 3, ...
, M + 1, m + 2, m + 3, m + 4, ... And the addresses a0 ... aE on the screen shown in FIG. 3 have a correspondence relationship as shown in the bottom row of FIG. Then, such a relationship is the same when the image data PD is read out from the memory 2 as serial data. It should be noted that the display dot is not assigned to the address "0", and it has no special meaning, and the address "0" may be associated with a0.

Since the operation of the former embodiment and the latter embodiment of storing in byte units are almost the same, the operation of the latter embodiment will be described. As for the overall operation of the image storage circuit, first, the read / write control signal R / * W is set to the write state, and the image data SD, which is serial data to be stored, is serialized in synchronization with the dot clock CLK. It is added to the parallel converter 6. The image data SD is converted into image data PD which is parallel data through the serial / parallel converter 6, and then the address counter 4 continuously counts the dot clock CLK every one field period to obtain an address obtained. It is accessed based on the designation and stored in the memory 2.

Further, the stored data PD from the memory 2
In order to read the data, first, the read / write control signal R / * W is set to the read state, and the memory is based on the address designation obtained by continuously counting the dot clock CLK every one field period by the address counter 4. 2 is accessed. The image data PD, which is parallel data read from the memory 2, is the dot clock C.
It is converted into serial data by the parallel / serial converter 8 in synchronization with LK and is taken out as a read output DO. Then, this output data is sent to the recording circuit 70 as the title output signal of FIG.

FIG. 4 shows an embodiment in which the number of horizontal samplings is changed by changing the period of the dot clock CLK. As a result, the storage capacity M of the memory 2 is, for example, NT.
Even if it is compatible with the SC system, it is possible to store image data of another system, for example, the PAL system, without changing the memory 2.

In this embodiment, the memory 2 is a memory having a serial input / output port, and the serial / parallel converter 6 and the parallel / serial converter 8 shown in FIG.
In the case of storing in byte units provided with and, these may be similarly added. Also, in this embodiment, PAL
When the system is selected, the conventional horizontal address counter 41 and vertical address counter 42 are connected instead of the address counter 4 and switched to one counter. Therefore, in the PAL system, the circuit is similar to that of the embodiment of FIG.

The PAL / NTSC dot clock generation circuit 9 responds to a PAL / NTSC switching signal (PAL / NTSC) for instructing switching between the PAL system and the NTSC system, and corresponds to the dot clock CLK corresponding to each of the PAL system and the NTSC system. To occur. Here, it is assumed that the memory 2 has a storage capacity of 64 kbits and is designed corresponding to the NTSC system.

By thus providing the PAL / NTSC dot clock generation circuit 9 for generating a clock having a frequency corresponding to each method, the number of horizontal samplings can be changed according to each method. As a result, it is possible to realize a circuit that can be shared by the PAL system and the NTSC system. Moreover, the number of wires of the counter does not increase.

On the other hand, the horizontal address counter 41 and the vertical address counter 42 are connected to each other by the switching circuits 9a, 9b, when the PAL / NTSC switching signal indicates PAL.
9c, the carry signal of the horizontal address counter 41 is input to the enable terminal of the vertical address counter 42 in synchronization with the dot clock CLK, and the carry signal is counted. If the capacity of the memory 2 is determined according to the number of horizontal scanning lines of the PAL system, NTSC
In the case of the method, the number of horizontal samplings can be further increased.

Although the principle of the present invention is as described above, it is assumed that a memory of 64 k bits (actually 65,536 bits) is actually used. It is practical that the count value of the counter in digital processing is a multiple of 2 or 8 or close to this. Therefore, in the NTSC system, if a number close to a multiple of 2 and 8 and a number of horizontal scanning lines near 243 is used, it becomes 256. As a result, NTSC
The number of samplings in the horizontal direction of the method is 65,536 / 2.
56 = 256 gives 256. As can be understood from the above, NTS determines the number of horizontal sampling
The frequency of the C dot clock generation circuit 9 is 50 μsec ÷
256≈0.195 μsec≈5 MHz. 5
0 μsec is the effective screen scanning period excluding the blanking period. This is because the blanking period is not sampled.

On the other hand, in the PAL system, since there are 625 horizontal scanning lines in one screen, one field is 31
It will be 2.5. When a 64 kbit memory is used, the substantial number of vertical samplings is about 280 considering the blanking period. The number of horizontal samplings is 65,536 ÷ 280≈234. Therefore, if the horizontal sampling number is set to 224 in consideration of the margin, the frequency of the clock generated by the PAL / NTSC dot clock generation circuit 9 when the PAL / NTSC switching signal indicates PAL is 50 μsec ÷ 224≈
0.223 μsec ≈4.45 MHz.

Therefore, when the PAL / NTSC dot clock generation circuit 9 receives the PAL selection signal,
The 45 MHz dot clock is sent to the counter 41 or the like, and when the NTSC selection signal is received, the 5 MHz dot clock is sent to the counter 41 or the like.

By the way, the output of the PAL / NTSC dot clock generation circuit 9 is normally supplied to the A / D conversion circuit as a sampling signal in order to sample the video signal and generate the serial video data SD.

[0040]

As is apparent from the above description, according to the present invention, a single counter is used or two counters are made single, so that the dot clock is continuously performed in one field period. When counting CLK and designating an address by the counted value, n of which the number of horizontal and vertical sampling dots is 2 is used as in a conventional image storage circuit having two counters of a horizontal address counter and a vertical address counter. The number of wirings is not increased even if the number of horizontal scanning lines is increased. Also, the degree of freedom in setting the number of sampling dots is increased, and the dot clock C
By changing the frequency of LK, it is possible to set an arbitrary number of sampling dots so as not to cause a shortage of storage capacity in the memory 2.

Therefore, in this image storage circuit, for example, the memory having the storage capacity of 64 kBIT is used, and the relationship of the formula (1) and the address count system by one address counter are adopted, whereby the image storage of the NTSC system is performed. Of course, even in the PAL method in which the number of horizontal scanning lines is large, the binarized image can be stored and reproduced without causing the loss of the stored image due to the lack of the storage capacity.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of an image storage circuit of the present invention.

FIG. 2 is a timing chart showing the operation of the image storage circuit shown in FIG.

3 is an explanatory diagram of image formation by the image storage circuit shown in FIG.

FIG. 4 is a block diagram of another embodiment of the image storage circuit of the present invention.

FIG. 5 is a block diagram of a conventional image storage circuit.

6 is a timing chart showing an operation of the image storage device shown in FIG.

FIG. 7 is a diagram showing image configurations of a PAL system and an NTSC system.

FIG. 8 is an explanatory diagram of a basic configuration centering on a title control circuit in a video camera.

[Explanation of symbols]

2 ... Memory, 4 ... Address counter, 6 ... Serial / parallel converter, 8 ... Parallel / serial converter, 9 ... P
AL / NTSC dot clock generation circuit, 9a, 9b,
9c ... Switching circuit, 41 ... Horizontal address counter, 42 ...
Vertical address counter, PAL / NTSC ... switching signal,
CLK ... Dot clock, R / * W ... Read / write control signal, VD ... Vertical sync signal, HBLK ... Horizontal blanking signal.

Claims (3)

[Claims] 1. A memory for storing image data and a clock having a cycle corresponding to a horizontal scanning time of each display dot on a display screen of a display, the clock is counted, and the clock is reset by a vertical synchronizing signal. An image storage circuit, comprising: a counter for designating an address of the memory by a count value, and continuously storing image data for one field displayed on the display in the memory. 2. A display 1 further displayed on the display
2. The image storage circuit according to claim 1, wherein the image data for one field is continuously stored in the memory, and the image data for one field is continuously read according to the clock. 3. A memory for storing image data and a clock having a cycle corresponding to the horizontal scanning time of each display dot on the display screen of the display, the clock is counted, and the clock is reset by a vertical synchronizing signal. A video processing device, comprising: a counter for designating an address of the memory by a count value; and an image storage circuit for continuously storing image data for one field displayed on the display in the memory.