JPH05304279A - Optical-electronic integrated circuit - Google Patents

Abstract

PURPOSE:To realize a change into a wide band, improvement in sensibility, miniaturization and the reduction of power consumption by forming a photo-diode and a field-effect transistor in OEIC structure. CONSTITUTION:Semiconductor multilayer-film reflecting mirrors 12 are formed onto a semiconductor substrate 17, and optical absorption layers 11 and channel layers 10 are formed onto the reflecting mirrors 12. The channel layer 10 also functions as the optical absorption layer in a PD region A. The optical absorption layer 11 in a FET region B functions as a buffer layer. Incident light 4 is reflected by the semiconductor multilayer-film reflecting mirrors 12, and absorbed by the optical absorption layers 11 and the channel layers 10 again, thus improving sensibility.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical / electronic integrated circuit (hereinafter referred to as OEIC) used in the fields of optical communication, high speed information processing, parallel information processing and the like.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram of a conventional signal output circuit from a photodiode. Photodiode 21
An optical receiver is configured so that a reverse voltage is applied from a bias power source through a resistor 22, its output is amplified by a preamplifier circuit 23, and an output signal is obtained through a limiter circuit 24.

In such a conventional optical receiver, the individual component type photodiode and the peripheral electronic circuit such as the amplifier are separately formed and are connected by, for example, hybrid coupling. In the case of the hybrid type in which the optical element and the electronic element are individually combined, the parasitic capacitance and parasitic inductance of the package, bonding wire, etc. are large, which deteriorates the high-speed signal waveform and limits the bandwidth and reception sensitivity. There is. Furthermore, there are limits to miniaturization and low power consumption.

In order to solve the problem of the conventional hybrid coupling between the light receiving element and the electronic element in the optical receiver, a monolithic integration technique of the light receiving element and the electronic element has been devised and is currently being developed. In the conventional light-receiving OEIC, a step is generated between the photodiode and the electronic element such as a field effect transistor, when the above and the electronic element are independently optimized.
This lowers the yield of OEIC production, and consequently hinders higher performance and lower cost.

On the other hand, in the light receiving OEIC, the crystal structure which does not cause the above step simplifies the process and improves the manufacturing yield, but the light receiving sensitivity becomes small because the light absorption layer in the photodiode cannot be made thick. There is a problem.

[0006]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and by adopting an OEIC structure, parasitic capacitance and parasitic inductance are eliminated, and a semiconductor multilayer film reflecting mirror is provided. It is an object of the present invention to provide a small-sized, wide-band and high-sensitivity optical receiver at a low price by integrating a photodiode and an electronic element on the epitaxial crystal that they have without any step difference.

[0007]

According to the present invention, in an optoelectronic integrated circuit, a semiconductor multilayer film reflecting mirror is provided as a lower layer on a semiconductor substrate, a light absorption layer is provided in a photodiode region in an intermediate layer, and a field effect transistor region is provided. Is an epitaxial layer in which a buffer layer and a channel layer are formed and a cap layer is formed on the upper layer, and a photodiode region and a field effect transistor region are integrated on the crystal thereof. ..

[0008]

According to the optoelectronic integrated circuit of the present invention, since the photodiode region and the field effect transistor region have a common crystal structure, no step is formed between the photodiode region and the field effect transistor region. ..

However, in the structure having only the common crystal structure, since the PD light absorbing layer is located under the channel layer of the FET, if the light absorbing layer is thickened to increase the sensitivity, the inside of this layer is increased. The pinch-off voltage is increased due to the current leakage at.

According to the present invention, by disposing the semiconductor multilayer mirror on the semiconductor substrate, the optical path length in the light absorbing layer can be doubled to increase the light receiving sensitivity. Therefore, the light receiving sensitivity can be increased without making the light absorption layer too thick.

[0011]

1 is a sectional view for explaining an optical / electronic integrated circuit of an embodiment of the present invention. In the figure, an A region on the left side is a region of a photodiode (hereinafter referred to as PD), a B region on the right side is a region of a field effect transistor (hereinafter referred to as FET), 1 is a wiring metal (or a bonding pad), 2 is a surface protective film, 3 is an n-side electrode, 4 is incident light, 5 is a light receiving window, 6 is a p ⁺ region, 7 is a light path, 8 is a p-side electrode, 9 is an n-type InP layer, 10, 11 Is n-type InG
a as layer, 12 a semiconductor multilayer film reflecting mirror, 13 a drain electrode, 14 a gate electrode, 15 a source electrode, 16 p
^{A +} region, 17 is a semi-insulating InP substrate, and 18 is an isolation groove for electrically isolating the PD region and the FET region.

The crystal layer structure is common to the PD region and the FET region. Therefore, the crystal for manufacturing the integrated device can be manufactured by continuously growing the PD layer and the FET layer once.

The PD area A will be described. The lowermost semiconductor multilayer film reflecting mirror 12 is for reflecting incident light as described later. At the same time, the semiconductor multilayer film reflecting mirror 12 also functions as a buffer layer for preventing the propagation of dislocations from the semi-insulating InP substrate 17 to the n-type InGaAs layer 11 that functions as a light absorption layer. Next n-type InG
aAs layer 11 and subsequent n-type InGaAs layer 10
Is a light absorption layer. Although the InGaAs layer 10 is a layer provided as a channel layer in the FET region in this embodiment, it acts as a light absorption layer for the PD. The n-type InP layer 9 acts as a cap layer.

An example of a semiconductor multilayer film having a quarter wavelength thickness will be described. InGaAsP (wavelength corresponding to bandgap is λ _g
= 1.3 μm) and InP, their refractive indices are 3.36 and 3.1 at λ = 1.5 μm, respectively.
Since it is 5, its thickness is 1120Å and 11 respectively.
If 90Å is selected, the thickness will be λ / 4 in either case, and a multilayer-film reflective mirror made of a semiconductor multilayer film can be obtained. When both the incident side layer and the emitting side layer are made of InP, the number of layer pairs is 35
The reflectance of about 90% is obtained as a pair.

The FET region B will be described. The semiconductor multilayer film reflecting mirror 12 as the lowermost layer and the n-type InGaAs layer 11 provided as the light absorption layer of the PD function here as a buffer layer. These buffer layers have a role of blocking the leakage of the current flowing in the active layer of the FET to the substrate side, and are important for obtaining good saturation characteristics in the drain current-voltage characteristics. n-type InGaAs layer 10
Is a layer serving as a current path, which is called an active layer or a channel layer, and is an epitaxial layer doped with impurities by a high mobility material. The n-type InP layer 9 thereon is an epitaxial layer having a large band gap and acts as a cap layer. P ⁺ region 1 for forming gate junction
6 is formed inside the n-type InP layer 9, and the front thereof enters the active layer of the n-type InGaAs layer 10. The surface protection film 2 of the n-type InP layer 9 is the drain electrode 1
3 and the source electrode 15 are removed by etching, and the drain electrode 13 is reduced in order to reduce the ohmic resistance that seriously affects the performance of the FET.
The source electrode 15 is directly provided on the surface of the n-type InGaAs layer 10.

The operation will be described. Incident light 4 from the light receiving window 5 in the PD region A is n provided as a channel layer.
-Type InGaAs layer 10 and n-type InG that is a light absorption layer
The light is absorbed by the aAs layer 11 and is reflected by the semiconductor multilayer film reflection mirror 12, and as shown in the light path 7, the n-type InG is again detected.
It is absorbed in the aAs layers 10 and 11. Due to this light absorption, electron-hole pairs are generated in the n-type InGaAs layers 10 and 11, which are separated by the internal electric field and travel toward the p-side electrode 8 and the n-side electrode 3 to generate photocurrent. Occurs.

This photocurrent is connected to F through a resistor.
The potential of the gate electrode 14 in the ET region B is changed, so that the width of the depletion layer formed in the n-type InGaAs layer 10 which is the channel layer of the FET region is changed by the p ⁺ region 16 forming the gate junction. Therefore, the current flowing in the channel layer is controlled.

Next, an example of a manufacturing process of the optical / electronic integrated circuit of the embodiment described in FIG. 1 will be briefly described. First, on the semi-insulating InP substrate 17, a semiconductor multilayer film reflecting mirror 12 having a quarter wavelength thickness, an n-type InGaAs layer 11,
The n-type InGaAs layer 10 and the n-type InP layer 9 are formed by using a metal organic vapor phase epitaxy method (MOVPE method), a molecular beam epitaxial growth method (MBE method), or the like.
An epitaxial crystal having the crystal layer structure shown in is produced. Using the SiN film formed on the upper surface of the n-type InP layer 9 as a diffusion mask, P ⁺ regions 6 and 16 are formed by selective diffusion of Zn therethrough. After removing the SiN film diffusion mask, the isolation region 18 for element isolation is electrically isolated from the PD region A and the FET region B by mesa etching using a chemical etching method or the like, and then the epitaxial crystal surface is further formed. The surface protection film 2 is formed on the upper surface by a plasma CVD method or the like. The n-side electrode 3 in the PD region, the drain electrode 13 and the source electrode 15 in the FET region are simultaneously formed by photowork and vapor deposition. In this embodiment, the n-side electrode 3 is patterned in an annular shape. A contact hole for the p-side electrode 8 is formed in the PD region. In this embodiment, the contact hole for the p-side electrode is also patterned in an annular shape. A contact hole for the gate electrode 14 is formed in the FET region. A p-side electrode in the PD region, a gate electrode in the FET region, and a wiring metal / bonding pad are formed at the same time. Although the InGaAs type photodiode has been described above as a photodiode, it is obvious that the present invention can be applied to photodiodes of other types.

[0019]

As is apparent from the above description, according to the present invention, the following effects can be expected. Since the photodiode and the field effect transistor are integrated on the same substrate, the parasitic inductance and the parasitic capacitance are reduced, and the optical receiver can have a wide band and high sensitivity. Since a common layer is used as an epitaxial layer necessary for the operation of the photodiode and the field effect transistor, a step is not generated between the photodiode and the field effect transistor, so that the manufacturing yield is high and the cost can be reduced. Since the semiconductor multi-layered film reflecting mirror is installed on the semiconductor substrate, it can be expected that the photodiode has high light receiving sensitivity. The crystal required for manufacturing the integrated element has a crystal layer structure that can be manufactured by performing crystal growth once.

[Brief description of drawings]

FIG. 1 is a cross-sectional view for explaining an optical / electronic integrated circuit of an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional signal output circuit from a photodiode.

[Explanation of symbols]

A photodiode (PD) area B field effect transistor (FET) area 1 wiring metal 2 surface protective film 3 n-side electrode 4 incident light 5 light-receiving window 6 p ⁺ area 7 light path 8 p-side electrode 9 n-type InP layer 10 n-type InGaAs layer 11 n-type InGaAs layer 12 semiconductor multilayer film reflecting mirror 13 drain electrode 14 gate electrode 15 source electrode 16 p ⁺ region 17 semi-insulating InP substrate 18 isolation groove

Claims (1)

[Claims] 1. On a semiconductor substrate, a semiconductor multilayer film reflecting mirror is provided as a lower layer, an intermediate layer is a light absorbing layer in a photodiode region and an epitaxial layer serving as a buffer layer and a channel layer in a field effect transistor region, and an upper layer is a cap layer. An optoelectronic integrated circuit having an epitaxial structure in which a photodiode region and a field effect transistor region are integrated on a crystal thereof.