JPH0530084A - Digital diversity equipment - Google Patents

Abstract

PURPOSE:To obtain the digital diversity equipment which can absorb surely a gridge, and also, can cope enough with a data transmission of a high speed. CONSTITUTION:In the case OR outputs of demodulation clocks of two sets of digital radio receivers 1a, 1b, or one of them is 'in the course of non- reception', only the demodulation clock of the other digital radio receiver is inputted to a digital PLL circuit 14 and stabilization of a frequency is performed, by which a new reproducing clock is generated. In such a way, it does not occur that a gridge is generated in the outputted reproducing clock and generation of step-out caused by twice read of the same data, etc., can be prevented, and also, a filter, etc., is unnecessary, therefore, the digital diversity equipment which can adequately cope with a data transmission of a high speed, as well.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention selects digital data and clocks received by two digital radio receivers on the side having a higher reception level, and outputs them as received data and a recovered clock. The present invention relates to a diversity device.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a conventional digital diversity apparatus. In the figure, 1a and 1b are two digital radio receivers to which the digital diversity apparatus is connected. 2a and 2b are antennas connected to the digital radio receiver 1a or 1b,
For example, there are two sets of antennas for leaky coaxial cables installed in a moving body such as a train on which the digital radio receivers 1a and 1b are mounted.

Reference numeral 3 is a comparison circuit for comparing the reception levels of the digital radio receivers 1a and 1b. Reference numerals 4a and 4b are comparison results from the comparison circuit 3 and the digital radio receivers 1 respectively.
The latch circuit receives the demodulation clocks from a and 1b and generates a switching signal at the rising edge of the demodulation clock.

Reference numeral 5 is a coincidence prohibiting circuit for preventing the switching signals output from the respective latch circuits 4a and 4b from being coincident with each other, and 6a and 6b are glitches due to the jitter of the demodulated clocks from the respective digital radio receivers 1a and 1b. Is a filter for absorbing.

Reference numerals 7a and 7b denote AND gates which gate the demodulated data output from the digital radio receiver 1a or 1b by the outputs of the filters 6a and 6b, respectively.
Similarly, a and 8b are AND gates that gate the demodulation clock output from the digital radio receiver 1a or 1b by the outputs of the filters 6a and 6b.

Reference numeral 9a is an OR gate which takes the logical sum of the outputs of the AND gates 7a and 7b and outputs it as received data, and 9b takes the logical sum of the outputs of the AND gates 8a and 8b and outputs it as a reproduction clock. It is an OR gate that outputs as.

Next, the operation will be described. The two digital radio receivers 1a and 1b demodulate the radio waves taken in from the antennas 2a and 2b connected to the digital radio receivers 1a and 1b, and output demodulated data and a demodulated clock, respectively. This time,
At the same time, a DC voltage proportional to the strength of the received radio wave is also output as each reception level.

The comparison circuit 3 is used for both digital radio receivers 1.
The reception levels of a and 1b are compared, and a switching signal for selecting the demodulation data and the demodulation clock of the digital radio receiver on the higher reception level side is output. This switching signal is output from the latch circuits 4a and 4b in synchronization with the rising edges of the demodulation clocks from the digital radio receivers 1a and 1b, and is sent to the filter 6a or 6b via the match prohibiting circuit 5.

The switching signal from the latch circuit 4a is sent to the filter 6a after being prevented from coincidence with the switching signal from the latch circuit 4b by the coincidence prohibiting circuit 5, and the glitch due to the jitter of the demodulated clock is absorbed. It is input to the gates 7a and 8a. Similarly, the switching signal from the latch circuit 4b is also subjected to matching prevention by the matching prohibiting circuit 5, the glitch is absorbed by the filter 6b and input to the AND gates 7b and 8b.

The demodulated data from the digital radio receivers 1a and 1b are input to the other terminals of the AND gates 7a and 7b, and the digital radio reception is input to the other terminals of the AND gates 8a and 8b. The demodulation clocks from the machines 1a and 1b are input.

Therefore, each of the AND gates 7a and 7b.
And the digital radio receiver 1 by 8a and 8b.
Demodulated data and demodulated clock from one of a and 1b are selected. The selected demodulated data and demodulated clock are
It is output as received data or a reproduction clock via the OR gate 9a or 9b.

In this way, the demodulated data and the demodulated clock received and demodulated on the side of the higher reception level in the two digital radio receivers 1a and 1b are automatically selected as the received data and the regenerated clock. It

As a document describing the technique related to such a conventional digital diversity apparatus,
For example, there is JP-A-63-43438.

[0014]

Since the conventional digital diversity device is constructed as described above, when the data transmission speed becomes high, switching is performed by the action of the time constant of the filters 6a and 6b for absorbing the glitch of the switching signal. The speed becomes slower and the diversity effect decreases, and the filter 6
When the time constants of a and 6b are made small, there is a problem that glitch remains in the reproduced clock and the same data is read twice, resulting in loss of synchronization.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a digital diversity apparatus capable of reliably absorbing glitches and capable of sufficiently coping with an increase in data transmission speed. And

[0016]

According to a first aspect of the present invention, there is provided a digital diversity apparatus for determining whether the two digital radio receivers are "receiving" or "not receiving" with a first comparator. , An OR gate that synthesizes the demodulation clock of the corresponding side when it is determined to be “receiving” by one of the first comparators, and combines both demodulation clocks when both are determined to be “receiving” Select the output of the first selection circuit,
A reproduction clock is generated based on the output of the first selection circuit and a reference clock generated by the internal oscillator, and a second comparator is used based on a switching signal output by comparing the reception levels of both digital radio receivers. The selection of demodulated data by the selection circuit 2 is performed asynchronously with the reproduction clock, and the reception data is output at the rising edge of the reproduction clock at the final stage.

Further, in the digital diversity apparatus according to the present invention as defined in claim 2, the second comparator compares the reception levels of the two digital radio receivers and outputs the switching signal in synchronization with the reproduction clock. Then, the switching signal is used to control the second selection circuit to output the reception data.

[0018]

The clock recovery circuit according to the present invention generates the demodulation clock from the digital radio receiver or the composite clock from the OR gate, which is selected by the first selection circuit and is determined to be "receiving", and the internal oscillator. By generating the recovered clock based on the reference clock
(EN) A digital diversity device capable of reliably absorbing a glitch by switching and outputting received data by this reproduced clock without switching a clock by a switching signal, and sufficiently corresponding to an increase in data transmission speed.

[0019]

EXAMPLES Example 1. Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the invention described in claim 1. In the figure, 1a and 1b are digital radio receivers and 2a and 2b are antennas.
Since they are the same as or equivalent to those of the conventional one denoted by the same reference numeral, detailed description thereof will be omitted.

Reference numerals 10a and 10b compare the reception levels of the digital radio receivers 1a and 1b with reference levels for reference, and the digital radio receivers 1a and 1b are "receiving" or "not receiving". 11a and 11b are reference level generators that give the reference levels to the first comparators 10a and 10b.

Reference numeral 12 denotes each digital radio receiver 1a, 1b.
Is an OR gate that synthesizes the demodulation clock from
Indicates that only one of the first comparators 10a and 10b is "receiving"
If it is determined that the corresponding digital wireless receiver 1a
Alternatively, it is a first selection circuit that selects the demodulated clock from 1b and selects the combined clock output from the OR gate 12 when both of the first comparators 10a and 10b determine "receiving".

Reference numeral 14 denotes a digital phase-locked loop circuit (hereinafter referred to as a digital PLL circuit) as a clock reproducing circuit for generating a reproduced clock based on the output of the first selection circuit 13 and a reference clock inside the digital diversity device. Numeral 15 is an internal oscillator for generating the reference clock and supplying it to the digital PLL circuit 14.

Reference numeral 16 denotes each digital radio receiver 1a, 1b
Is a second comparator for generating a switching signal by comparing the reception levels of the digital radio receivers 1a and 1b on the high reception level side based on the switching signal output from the second comparator 16. 2 is a second selection circuit for selecting the demodulated data output by.

Reference numeral 18 synchronizes demodulated data from the digital radio receiver 1a or 1b selected by the second selection circuit 17 with the rising edge of the reproduced clock output from the digital PLL circuit 14 and outputs it as received data. It is a D-type flip-flop circuit.

Next, the operation will be described. As in the conventional case, the radio waves taken in from the antennas 2a and 2b are demodulated by the digital radio receivers 1a and 1b and output as demodulated data and demodulated clocks. At the same time, the digital radio receivers 1a and 1b also output a DC voltage proportional to the strength of the received radio wave as their respective reception levels.

The second comparator 16 compares the reception levels of the digital radio receivers 1a and 1b, generates a switching signal based on the comparison result, and sends the switching signal to the second selection circuit 17. The second selection circuit 17 operates according to the switching signal and selects the demodulated data output by the digital radio receiver 1a or 1b on the side where the reception level is high.

The first comparators 10a and 10b are also provided.
Compares the reception level of each of the digital radio receivers 1a and 1b with a reference reference level generated by the reference level generator 11a or 11b, and determines that each of the digital radio receivers 1a and 1b is "receiving". It is determined whether there is or is not receiving. The reference levels generated by the reference level generators 11a and 11b are usually the same level.

Here, when the output of the first comparator 10a indicates "receiving" and the output of the first comparator 10b indicates "not receiving", the first selection circuit 13 Selects and outputs the demodulation clock of the digital radio receiver 1a. Similarly, when the output of the first comparator 10a indicates "not receiving" and the output of 10b indicates "receiving", the first selection circuit 13 demodulates the digital radio receiver 1b. Select and output the clock.

On the other hand, when the outputs of the first comparators 10a and 10b both indicate "receiving", the first selection circuit 13 synthesizes the demodulated clocks of the digital radio receivers 1a and 1b. , The output of the OR gate 12 is selected and output. Also, when both outputs indicate "not receiving", both demodulation clocks are invalid,
The first selection circuit 13 selects and outputs the ground level.

The signal thus selected by the first selection circuit 13 is input to the digital PLL circuit 14.
The digital PLL circuit 14 compares the phase of the demodulated clock generated by dividing the reference clock generated by the internal oscillator 15 with an internal clock having the same frequency, generates a reproduced clock, and outputs it.

The reproduced clock is also input to the D-type flip-flop circuit 18, and the flip-flop circuit 18 outputs the demodulated data of the digital radio receiver 1a or 1b selected by the second selection circuit 17 to the concerned data. The received data is output in synchronization with the rising edge of the reproduction clock.

Example 2. In the above embodiment, the case where the demodulated data is selected / switched asynchronously with the reproduction clock and is output as the reception data at the timing of the reproduction clock at the final stage has been described, but the switching signal is output at the timing of the reproduction clock. The second selection circuit may be controlled by this switching signal, and the same effect as that of the above-described embodiment can be obtained.

FIG. 2 is a block diagram showing an embodiment of the invention described in claim 2, and the reference numerals of the respective parts are the same as those of the embodiment shown in FIG. . In this case, the switching signal generated by the second comparator 16 is sent to the flip-flop circuit 18, and is input from the flip-flop circuit 18 to the second selection circuit 17 at the timing of the reproduction clock generated by the digital PLL circuit 14. Has been done.

[0034]

As described above, according to the present invention, the OR outputs of the demodulation clocks of the two digital radio receivers, or when one of them is "not receiving", the other digital radio receiver is used. By inputting the demodulation clock alone of the digital PLL circuit to the digital PLL circuit,
Since the LL circuit is configured to generate a new reproduction clock by stabilizing the frequency, a glitch does not occur in the output reproduction clock, and synchronization loss occurs due to double reading of the same data. Not only is it possible to prevent this, but also a filter or the like is not necessary, so that there is an effect that a digital diversity device can be obtained which can sufficiently cope with an increase in data transmission speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a digital diversity device according to an embodiment of the invention described in claim 1. FIG.

FIG. 2 is a block diagram showing an embodiment of the invention described in claim 2.

FIG. 3 is a block diagram showing a conventional digital diversity device.

[Explanation of symbols]

1a, 1b Digital radio receiver 10a, 10b First comparator 12 or gate 13 First selection circuit 14 Clock recovery circuit (digital PLL circuit) 15 Internal oscillator 16 Second comparator 17 Second selection circuit 18 Flip-flop circuit

Claims (2)

[Claims] 1. The reception level of each of the two digital radio receivers is compared with a reference reference level to determine whether each of the digital radio receivers is "receiving" or "not receiving". Two first comparators, an OR gate for synthesizing demodulated clocks of the digital radio receivers, and one of the first comparators, if only one is determined to be “receiving”, the corresponding digital radio A first selection circuit that selects the output of the OR gate when the demodulation clock from the receiver is selected and both of the first comparators determine that "there is receiving"; A clock recovery circuit for generating a recovered clock based on an output and a reference clock generated by an internal oscillator; a second comparator for comparing reception levels of the digital radio receivers to generate a switching signal; A second selection circuit for selecting demodulated data output from the digital radio receiver on the higher reception level side based on a switching signal output from the second comparator; and an output from the second selection circuit, A digital diversity device including a flip-flop circuit that outputs as reception data in synchronization with a rising edge of a recovered clock output from a clock recovery circuit. 2. The reception level of each of the two digital radio receivers is compared with a reference standard level to determine whether each of the digital radio receivers is "receiving" or "not receiving". Two first comparators, an OR gate for synthesizing demodulated clocks of the digital radio receivers, and one of the first comparators, if only one is determined to be “receiving”, the corresponding digital radio A first selection circuit that selects the output of the OR gate when the demodulation clock from the receiver is selected and both of the first comparators determine that "there is receiving"; A clock recovery circuit for generating a recovered clock based on an output and a reference clock generated by an internal oscillator; a second comparator for comparing reception levels of the digital radio receivers to generate a switching signal; A flip-flop circuit that outputs a switching signal from the comparator 2 in synchronism with the rising edge of the reproduction clock output from the clock reproduction circuit, and a switching signal that is synchronized with the reproduction clock in the flip-flop circuit. And a second selection circuit for selecting the demodulated data output from the digital radio receiver having the higher reception level and outputting the demodulated data as reception data.