JPH0530051B2 - - Google Patents
Info
- Publication number
- JPH0530051B2 JPH0530051B2 JP57143210A JP14321082A JPH0530051B2 JP H0530051 B2 JPH0530051 B2 JP H0530051B2 JP 57143210 A JP57143210 A JP 57143210A JP 14321082 A JP14321082 A JP 14321082A JP H0530051 B2 JPH0530051 B2 JP H0530051B2
- Authority
- JP
- Japan
- Prior art keywords
- gate
- film
- layer
- insulating film
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 7
- 230000001590 oxidative effect Effects 0.000 claims 1
- 239000010410 layer Substances 0.000 description 31
- 238000000034 method Methods 0.000 description 14
- 229910004298 SiO 2 Inorganic materials 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 239000011521 glass Substances 0.000 description 9
- 238000001020 plasma etching Methods 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 238000006243 chemical reaction Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- RMAQACBXLXPBSY-UHFFFAOYSA-N silicic acid Chemical compound O[Si](O)(O)O RMAQACBXLXPBSY-UHFFFAOYSA-N 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- -1 arsenic ions Chemical class 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 235000019441 ethanol Nutrition 0.000 description 1
- 238000005111 flow chemistry technique Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に係り、特にオ
ーバハング構造の発生を防止する、あるいは消滅
させるに好適な半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device suitable for preventing or eliminating overhang structures.
従来の単層Siゲートプロセスにおいては、第１
図ａのようにSi基板２１上のゲート酸化膜２２上
に形成されたゲート２３端部にオーバーハング構
造が生じていた。Al配線の断線防止の意味でこ
のオーバーハング構造を消滅させるために、第１
図ｂに示すように一般的にはグラスフロー２６等
が用られてきた。 In the conventional single-layer Si gate process, the first
As shown in Figure a, an overhang structure was formed at the end of the gate 23 formed on the gate oxide film 22 on the Si substrate 21. In order to eliminate this overhang structure in order to prevent disconnection of the Al wiring, the first
As shown in FIG. b, a glass flow 26 or the like has generally been used.
しかしながら、これらの方法は、従来、トラン
ジスタ等を形成した後の工程でしか用いることが
できなかつた。例えば、２層シリコンゲートプロ
セスにおいて、第１層のシリコンゲート形成後第
２層目でもトランジスタを形成しようとすると、
第２層目のゲートを形成前にグラスフロー等は使
えなかつた。なお、２４はゲートライト酸化膜、
２５はソース・ドレイン領域である。 However, conventionally, these methods could only be used in a process after forming a transistor or the like. For example, in a two-layer silicon gate process, if you try to form a transistor in the second layer after forming the silicon gate in the first layer,
Glass flow etc. could not be used before forming the second layer gate. In addition, 24 is a gate light oxide film,
25 is a source/drain region.
従つて、第２図ａに示すように、２層シリコン
ゲートプロセスで、第１層のシリコンゲート３３
形成後、第２ゲート酸化膜３４を形成、第２層多
結晶シリコン膜３６を堆積し、加工する場合、パ
ターン変換差の小さいすなわちサイドエツチング
の少ないマイクロ波プラズマエツチング等で加工
すると、上記第２層多結晶シリコン膜３６のう
ち、上記第２ゲート酸化膜３４の側部上に形成さ
れた部分は、上記オーバーハング構造のためエツ
チされない。そのため、第２図ｂのように第１ゲ
ート３３端部にエツチング残り３６′が生じ、第
２ゲート間短絡等の原因になる。一方、エツチン
グ残りが生じないように、等方性のプラズマエツ
チングで加工すると、第２図ｃのように、第２ゲ
ート３６が細つてしまうという欠点があつた。 Therefore, as shown in FIG. 2a, in the two-layer silicon gate process, the first layer silicon gate 33 is
After the formation, the second gate oxide film 34 is formed and the second layer polycrystalline silicon film 36 is deposited and processed by microwave plasma etching or the like with a small pattern conversion difference, that is, with little side etching. The portions of the layered polycrystalline silicon film 36 formed on the sides of the second gate oxide film 34 are not etched due to the overhang structure. Therefore, as shown in FIG. 2B, an etching residue 36' is left at the end of the first gate 33, which may cause a short circuit between the second gates. On the other hand, when etching is performed using isotropic plasma etching to avoid etching residues, the second gate 36 becomes narrower, as shown in FIG. 2c.
本発明の目的は、オーバーハング構造による欠
陥のない半導体装置の製造方法を提供することに
ある。 An object of the present invention is to provide a method for manufacturing a semiconductor device free from defects due to overhang structures.
このような目的を達成するための本発明の構成
は、多層ゲートの最上層を除く多結晶シリコンあ
るいは高融点金属電極に、加工あるいは加工後の
絶縁膜形成等により生じたあるいは生じる可能性
があるオーバーハング構造を、その上に被覆性の
よい低圧あるいは高温CVD（Chemical Vapour
Deposition）法グラスフロー、SOG（一般にスピ
ン・オン・グラス）等のよう絶縁膜あるいは絶縁
化しうる半導体あるいは導電膜を被着した後、サ
イドエツチングの少ない反応性イオンエツチング
（一般にRIE）等の方法で上記被着した膜を除去
することで消滅させるあるいは発生を防止するこ
とにある。 The structure of the present invention to achieve such an object is produced or may be produced by processing or forming an insulating film after processing on polycrystalline silicon or high-melting point metal electrodes other than the top layer of a multilayer gate. The overhang structure is coated with low-pressure or high-temperature CVD (Chemical Vapor
After depositing an insulating film or a semiconductor or conductive film that can be made into an insulator, such as glass flow or SOG (generally spin-on glass), etching is performed using a method such as reactive ion etching (generally RIE), which causes less side etching. The objective is to eliminate or prevent the occurrence of such defects by removing the deposited film.
以下、本発明の実施例を詳細に述べる。なお、
本発明は、後述する実施例のみに限定されるもの
ではない。 Examples of the present invention will be described in detail below. In addition,
The present invention is not limited to the examples described below.
実施例 １
第３図ａ〜ｄは本発明の一実施例としての半導
体装置の製造方法を示した概略工程図である。Embodiment 1 FIGS. 3a to 3d are schematic process diagrams showing a method of manufacturing a semiconductor device as an embodiment of the present invention.
第３図ａに示すように、抵抗率10〜15Ω・cm、
Ｐ型（100）のシリコン基板１に分離用酸化膜２
を形成した後、第１ゲート酸化膜３を約50nmの
厚さに形成した。この後、第３図ｂに示すよう
に、約350nmの燐ドープされた第１層多結晶シリ
コン膜を加工、酸化して第１層MOSトランジス
タのゲート４およびこのゲート４を覆う第１の
SiO2膜５を形成した。この状態で低圧CVD
（Chemical Vapour Deposition）法あるいは高
温CVD法で厚さ約300nmの第２のSiO2膜６を全
面に堆積した。 As shown in Figure 3a, resistivity is 10~15Ω・cm,
Isolation oxide film 2 on P-type (100) silicon substrate 1
After forming, a first gate oxide film 3 was formed to a thickness of about 50 nm. Thereafter, as shown in FIG. 3b, the first layer polycrystalline silicon film doped with phosphorus of approximately 350 nm is processed and oxidized to form a gate 4 of the first layer MOS transistor and a first layer covering the gate 4.
A SiO 2 film 5 was formed. Low pressure CVD in this state
A second SiO 2 film 6 with a thickness of approximately 300 nm was deposited on the entire surface by a chemical vapor deposition (Chemical Vapor Deposition) method or a high temperature CVD method.
これら、CVDに限らずガラスフローおよび
SOGによつても全く同様に適用できた。この後、
第３図ｃに示すように、H2を10％程度含むCF4雰
囲気中で上記第２のSiO2膜６をRIEで加工する
と、ゲート端部にのみ上記第２のSiO2膜６が残
る。次いで、第３図ｄに示すように、この状態で
第２ゲート酸化膜７約35nmの厚さに形成、約
350nmの燐ドレープされた第２層多結晶シリコン
膜をマイクロ波プラズマエツチングで加工して第
２層MOSトランジスタのゲート８を形成した。
この後、シリコン基板１表面に砒素イオンAs +を
約10101cm2打ち込んでソース−ドレイン領域９を
形成した後、燐硅酸ガラス膜１０を約600nmの厚
さに形成、Al配線１１との電気的コンタクトを
とるため、ソース−ドレイン領域９上に孔あけを
行ない、グラスフローを実施した後Al配線１１
を設けた。 These are not limited to CVD, but also glass flow and
It could be applied in exactly the same way to SOG. After this,
As shown in FIG . 3c, when the second SiO 2 film 6 is processed by RIE in a CF 4 atmosphere containing about 10% H 2 , the second SiO 2 film 6 remains only at the gate edge. . Next, as shown in FIG. 3d, a second gate oxide film 7 is formed to a thickness of about 35 nm in this state.
A second layer polycrystalline silicon film doped with 350 nm phosphorus was processed by microwave plasma etching to form the gate 8 of the second layer MOS transistor.
Thereafter, approximately 10 10 1 cm 2 of arsenic ions A s + are implanted into the surface of the silicon substrate 1 to form source-drain regions 9, and then a phosphosilicate glass film 10 is formed to a thickness of approximately 600 nm, and Al wiring 11 and In order to make electrical contact with the Al wiring 11, a hole is made on the source-drain region 9 and a glass flow is performed.
has been established.
本実施例によれば、通常第２ゲート酸化膜形成
時に生じる第１層目ゲート端部のオーバーハング
が形成されないので、第１層MOSトランジスタ
のゲート耐圧が向上する、断線・シヨートが生じ
難くなるために、第２層多結晶シリコン膜、Al
配線膜の加工に、パターン変換差の小さいマイク
ロ波プラズマエツチング、RIE（一般に反応性イ
オンエツチング）等が採用できるので第２ゲート
の過剰エツチングが阻止される等の効果がある。 According to this embodiment, an overhang at the end of the first layer gate, which normally occurs when forming the second gate oxide film, is not formed, so the gate breakdown voltage of the first layer MOS transistor is improved, and disconnections and shorts are less likely to occur. Therefore, the second layer polycrystalline silicon film, Al
Microwave plasma etching, RIE (generally reactive ion etching), etc., which have a small difference in pattern conversion, can be used to process the wiring film, so that there are effects such as preventing excessive etching of the second gate.
実施例 ２
実施例１で、第１層目のゲート形成後の低圧あ
るいは高温CVD法によるSiO2膜堆積を、R2O5が
10モル％程度の燐硅酸ガラスの堆積1000℃程度の
グラスフロー処理とに置き換えて実施した。Example 2 In Example 1, the SiO 2 film was deposited by low-pressure or high-temperature CVD after the first layer gate was formed, but R 2 O 5
This was carried out by replacing the deposition with glass flow treatment at about 1000°C with deposition of about 10 mol% phosphosilicate glass.
実施例１では、第１層目ゲート端部のオーバー
ハング発生は防止できる。しかし、そこでの傾角
が大きく、その制御に工夫が要る。第２層目ゲー
トあるいはAl膜の加工には、傾角がある程度小
さい方が望ましいからである。本実施例では、実
施例１を改良しより傾角が小さく、またグラスフ
ロー処理の条件により傾角の制御もより容易にな
る。 In the first embodiment, the occurrence of overhang at the end of the first layer gate can be prevented. However, the angle of inclination there is large and requires some ingenuity to control. This is because it is desirable that the inclination angle be small to some extent for processing the second layer gate or Al film. In this example, the inclination angle is smaller as an improvement over the first example, and the inclination angle can be controlled more easily depending on the glass flow processing conditions.
実施例 ３
実施例１で、第１層目のゲート形成後の低圧あ
るいは高温CVD法によるSiO2膜堆積を硅酸Si
（OH）4溶液の塗布に置き換えて実施した。Example 3 In Example 1, the SiO 2 film was deposited using low-pressure or high-temperature CVD after the first layer gate was formed using silicate Si.
(OH) 4 solution was applied instead.
硅酸溶液としては、SiO2に換算して5.9％の硅
酸を含むエチルアルコール溶液を用いて5000rpm
で回転塗布した。硅酸は次の反応式に従い常温で
SiO2に変化して、膜厚は200nm程度となつた。 As the silicic acid solution, an ethyl alcohol solution containing 5.9% silicic acid in terms of SiO 2 was used at 5000 rpm.
It was applied by rotation. Silicic acid is produced at room temperature according to the following reaction formula.
It changed to SiO 2 and the film thickness became about 200 nm.
Si（OH）4→SiO2＋2H2O
本実施例によれば、前記実施例２よりも低温で
第１層目ゲート端部のオーバーハング発生を防止
することができる。 Si(OH) 4 →SiO 2 +2H 2 O According to this embodiment, it is possible to prevent the occurrence of overhang at the end of the first layer gate at a lower temperature than in the second embodiment.
以上述べた通り、本発明によれば、多層ゲート
の最上層を除くゲートのオーバーハング構造の発
生を防止できるので、最上層を除くゲートの耐圧
が向上する。第２層目以上のゲート、金属配線の
断線・シヨートが生じ難くなるために、パターン
変換差の小さい加工法を採用できる等の効果があ
る。 As described above, according to the present invention, it is possible to prevent the occurrence of an overhang structure in gates other than the top layer of a multilayer gate, so that the withstand voltage of the gates other than the top layer is improved. Since disconnections and shorts in gates and metal wiring in the second and higher layers are less likely to occur, there are effects such as the ability to employ processing methods with small pattern conversion differences.
また、以上の実施例では、多結晶シリコン膜に
よる交互配線を例示したが、多結晶シリコンのか
わりに、高融点金属、あるいはそれらのシリサイ
ドなども用いても全く同様の効果が得られた。こ
れら、高融点金属、あるいは、それらのシリサイ
ドの形成方法は周知の製法により設ければよいの
で、詳細な説明は省略する。 Further, in the above embodiments, alternate wiring using polycrystalline silicon films was exemplified, but the same effect could be obtained by using high melting point metals or their silicides instead of polycrystalline silicon. Since these high melting point metals or their silicides may be formed by well-known manufacturing methods, detailed explanations will be omitted.
第１図ａ，ｂは、従来の単層シリコンゲートプ
ロセスを説明するための断面図、第２図ａ〜ｄ
は、従来の２層シリコンゲートプロセスを説明す
るための断面図、第３図ａ〜ｂは、本発明の一実
施例としての半導体装置の製法を説明するための
概略工程断面図である。
１，２１，３１…シリコン基板、２…分離用酸
化膜、３，２２，３２…第１ゲート酸化膜、４，
２３，３３…第１層目ゲート、５，２４，３５…
第１層目ゲートライト酸化膜、６…CVDSiO2膜、
７，３４…第２ゲート酸化膜、８，３６…第２層
目ゲート、９，２５…ソース−ドレイン層、１
０，２６…燐硅酸ガラス、１１…Al配線、３
６′…第２層目ゲートの第１層目ゲート端部のエ
ツチング残り。
Figures 1a and b are cross-sectional views for explaining the conventional single-layer silicon gate process, and Figures 2a-d
3A and 3B are cross-sectional views for explaining a conventional two-layer silicon gate process, and FIGS. 3A and 3B are schematic process cross-sectional views for explaining a method for manufacturing a semiconductor device as an embodiment of the present invention. 1, 21, 31...Silicon substrate, 2...Isolation oxide film, 3,22,32...First gate oxide film, 4,
23, 33...first layer gate, 5, 24, 35...
1st layer gate light oxide film, 6...CVDSiO 2 film,
7, 34... Second gate oxide film, 8, 36... Second layer gate, 9, 25... Source-drain layer, 1
0,26...Phosphorsilicate glass, 11...Al wiring, 3
6'... Remains of etching at the end of the first layer gate of the second layer gate.
Claims (1)
された上面および側部を酸化して、当該多結晶シ
リコン膜の上面および側部を覆う第１の絶縁膜を
形成する工程と、第２の絶縁膜を全面に形成する
工程と、当該第２の絶縁膜を異方性エツチして、
当該第２の絶縁膜のうち、上記多結晶シリコン膜
の側部上に上記第１の絶縁膜を介して形成されて
いる部分を残し、他の領域上に形成されている部
分を除去することにより、上記第１の絶縁膜のオ
ーバーハング構造を消滅させる工程を少なくとも
含むことを特徴とする半導体装置の製造方法。1 A step of oxidizing the exposed top surface and side portions of a polycrystalline silicon film having a predetermined shape to form a first insulating film covering the top surface and side portions of the polycrystalline silicon film, and a step of forming a second insulating film. A step of forming a film on the entire surface and anisotropic etching of the second insulating film,
Of the second insulating film, a portion formed on the side of the polycrystalline silicon film via the first insulating film is left, and a portion formed on other regions is removed. A method of manufacturing a semiconductor device, comprising at least the step of eliminating the overhang structure of the first insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14321082A JPS5933829A (en) | 1982-08-20 | 1982-08-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14321082A JPS5933829A (en) | 1982-08-20 | 1982-08-20 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5933829A JPS5933829A (en) | 1984-02-23 |
| JPH0530051B2 true JPH0530051B2 (en) | 1993-05-07 |
Family
ID=15333444
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14321082A Granted JPS5933829A (en) | 1982-08-20 | 1982-08-20 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5933829A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5444482A (en) * | 1977-09-14 | 1979-04-07 | Matsushita Electric Ind Co Ltd | Mos type semiconductor device and its manufacture |
| JPS57199221A (en) * | 1981-06-02 | 1982-12-07 | Toshiba Corp | Manufacture of semiconductor device |
-
1982
- 1982-08-20 JP JP14321082A patent/JPS5933829A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5444482A (en) * | 1977-09-14 | 1979-04-07 | Matsushita Electric Ind Co Ltd | Mos type semiconductor device and its manufacture |
| JPS57199221A (en) * | 1981-06-02 | 1982-12-07 | Toshiba Corp | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5933829A (en) | 1984-02-23 |
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