JPH05300195A - Line state monitoring system - Google Patents

Abstract

PURPOSE:To prevent the interruption of a program except for disconnecting instructions and to reduce the load of a program processing by separately detecting the entire 24-bit continuation states of an R line and a 1 line and the times of the 24-bit continuation and the disconnecting instruction. CONSTITUTION:A communication controller 200 for connecting line by an X21 interface and performing transmission/reception is provided with line controllers 500-50n. Then, the state of the R and 1 lines from a line terminating equipment 600 is detected, an interruption signal for indicating the same 24-bit state and the interruption signal for indicating only the disconnecting instruction state are outputted, and also the suppression of the interruption by the interruption signal in each state is set and released by the control program. When the state of the lines turns to the state in which the monitoring is unnecessary except for the disconnecting instructions, the detection and the interruption of the same 24-bit state are suppressed by a control program, and only by detecting disconnecting instruction, 24-bit identification and the disconnection instruction can be separately detected.

Description

Detailed Description of the Invention

[0001]

The present invention relates to CCITT Recommendation X2.
The present invention relates to a system for performing data communication using DCE with one interface, and particularly to a line state monitoring method.

[0002]

2. Description of the Related Art Generally, in a system in which digital data communication is performed by a digital communication network, communication is performed between a communication control processing unit (DTE) and the digital communication network via a line terminating device (DCE).

The communication control processor and the DCE connected to the digital communication network are generally connected by the CCiTT recommended X21 interface. In the X21 interface, between the communication control processing device and the DCE, a T line that is a data output line, an R line that is a data input line, and a control (state)
They are connected by a C line which is a transmission line and an I line which is a control (state) input line.

According to the CCiTT recommendation, the binary state "1" or "0" of the T-line or the i-line lasts at least 24 dots with the combination of the states of the c-line or the i-line, and the detection of the disconnection instruction signal is I It is specified that it is desirable that the line = OFF and the R line = 0 be 10 ms or more.

With respect to this, in the conventional apparatus, a 24-bit detection circuit is provided to detect by a state combination of the R line and the I line at the time of interruption, or the R line and the I line are viewed as 24 bits as data using a data receiving circuit. ..

For example, as a technique related to this kind of technique, there is provided a method for detecting by providing a counter for counting the same state of the signal lines as in "state detecting device" of Japanese Patent Laid-Open No. 55-50762, and Japanese Patent Laid-Open No. 64-64. -78056 publication, "DTE state transmission method and its state" and the like.

[0007]

Signal line (R line, I line)
In the state monitoring of, it is necessary to monitor the state of the signal line other than the disconnection instruction during the connection control processing, so the state of the R line and the I line is
If the same for 24 bit time or more, or 2 if disconnection instruction
It continues for 4 bit time or more, and monitors for 10 ms or more, and if detected, executes the signal control processing of the X21 interface by the program.

However, in the interrupt-time processing method provided with only the 24-bit detection circuit described above, transmission / reception is possible even when there is no need to monitor anything other than a disconnection instruction while the line is connected after communication is detected (I line = ON). If the state of the R line and the I line during transmission / reception is the same for 24 bits or more during transmission / reception, an interrupt will always be input to the program even if a command other than a disconnection instruction is given, which causes a problem that the processing of the program is burdened. In addition, it is difficult to detect during data reception by the method of observing 24 bits of R line and I line as data.

An object of the present invention is to provide a disconnection instruction such that all 24-bit continuation states of the R line and I line and 24-bit continuation and disconnection instruction can be detected separately in transmission / reception control after connection control by the X21 interface. In other states, the processing load of the program can be reduced by not interrupting the program.

[0010]

In order to achieve the above object, according to the present invention, a line terminating device (DC) is used in a device that performs line connection by an X21 interface to perform transmission / reception.
2) by detecting the status of the signal line (R line, I line) from E)
A circuit that outputs an interrupt signal indicating the same state of 4 bits and an interrupt signal indicating only the disconnection instruction state is provided, and a circuit that can set and cancel the inhibition of the interrupt by the interrupt signal in each state is provided by a control program.

[0011]

According to the present invention, when the line state becomes a state where it is not necessary to monitor other than the disconnection instruction (connected state), the control program suppresses the 24-bit same state detection interrupt to detect the disconnection instruction. By performing only this, it is possible to detect the same 24-bit and disconnection instructions separately and reduce the load on the program.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a communication control processing device according to an embodiment of the present invention. The communication control device 200 is
Host computer 100 and line termination equipment (DCE) 6
The DCE 600 connected to 00 is connected to a T line which is a data output line, an R line which is a data input line, a C line which is a control (state) transmission line, and an I line which is a control (state) input line,
A channel control processor 300 for controlling a channel connection 150 with the host computer 100, a line controller (hereinafter referred to as LC) 500, ..., A processor 400 for managing 50n, an LC 500 for transmitting / receiving data and controlling a line interface ,. , 50n.

FIG. 2 shows a block diagram of an LC500 for the X21 interface embodying the present invention.
Line interface control processor 530 (hereinafter referred to as LCP), which is a processor for controlling 500, LCP5
Local memory 52 in which 30 programs are stored
0, a transmission / reception controller 540 that transmits / receives data and disassembles / assembles characters, an LCP 530, and a bus 57.
A line control unit 510 for 0 control, an interval timer 560 for clock generation and LC internal control, and a line interface controller 550 (hereinafter referred to as LiC) for controlling and monitoring the line interface signal line.

LiC550 is constructed as follows. The transmission data from the transmission / reception controller 540 is sent to the line, or the X21 interface control line T line,
In order to control the C line, the control circuit 552 that switches or outputs the contents of the register 551 (hereinafter referred to as LCTL) that specifies the states of the T line and the C line, the state of the R line and the I line is 24 bits continuously and the R line , A circuit 554 for detecting a state where the I line is 0 and not OFF, R line = 0, I line = OFF (disconnect instruction)
Register 556 (hereinafter referred to as XiNT) that interrupts or prohibits the program when the detection signals of the circuit 555, the circuit 554, and the circuit 555 that detect whether the state of 24 bits continues for 10 ms or more are output,
Register 5 in which the state of R line and I line at that time is set
57 (hereinafter referred to as STAT).

The present invention will be described by taking control from line connection (incoming control) to disconnection as an example.

When receiving the instruction of the incoming control, the LCP 530 sets the value of the register LCTL551 in the LiC550 to the T line =
After setting the C line = OFF and setting the DTE ready state,
In order to detect the CE ready (R line = 1, I line = OFF) state, the circuit 556 is configured so that the state of the R line and the I line is the same for 24 bits or an interrupt is generated when the disconnection instruction is detected.
3. Designate to allow the output interrupt signal of the circuit 555. The circuit 554 is a 24-bit same-state circuit and the R line =
When the state where 0 and I line are not OFF is detected, when the state of R line and I line is the same for 24 bits, a signal 571 is output and an interrupt is generated to the LCP 530 via the register XiNT 556. At this time, the LCP 530 is set to the register STAT.
If the contents of 557 are read and DCE is ready, DCE
In order to receive the "incoming call signal" from the transmission / reception controller, a reception instruction is issued to the transmission / reception controller 540. Upon receipt of the "incoming call signal", the LCP 530 sets the register LCTL551 to "incoming call acceptance" (T line = 1, C line = ON) and waits for communication (R line = 1, I line = ON) to wait for detection. Become. Since the state is connected after the communication is detected, the register 5 is used to monitor the state of the R line and the I line thereafter so that only the disconnection instruction is given.
56 output signal 571 of 24-bit same state detection 554
Specifies that only interrupts due to are suppressed. As a result, even if the state of the R line and the I line is the same for 24 bits or more except for the disconnection instruction, and the signal 571 is output from the circuit 554, the interrupt is suppressed by the register 556, so the LCP.
No interrupt occurs in the program of 530.

If the state of R line = 0 and I line = OFF is the same state for 24 bits and 10 ms, the disconnection instruction detection circuit 55
5 outputs the disconnection instruction detection signal 572 to output the register XiN.
An interrupt is generated in the LCP 530 via T556, and the content of the register STAT557 at this time is read to detect the disconnection instruction from the DCE.

[0019]

As described above, according to the present invention, the R line,
The interrupt for detecting the state of the I line can be detected separately for the case of 24-bit state continuation detection and the case of disconnection instruction, and the inhibition of the interrupt can be arbitrarily set and released. As a result, after the line is connected, the interrupt due to the state detection of the R line and the I line is set to the disconnection instruction only, and even if the state of the R line and the I line is the same for 24 bits time or more during the transmission / reception processing, the LCP 530 Since the program is not interrupted, it has the effect of reducing the processing load of the program.

[Brief description of drawings]

FIG. 1 is a block diagram of a communication control processing device according to an embodiment.

FIG. 2 is a block diagram of a line controller for an X21 interface adopted in implementing the present invention.

[Explanation of symbols]

 500 ... Line controller, 550 ... Line interface controller, 553 ... R line and I line state detection register, 554 ... 24-bit same state detection circuit, 555 ... Disconnection instruction detection circuit, 556 ... X21 state monitoring interrupt suppression register.

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Claims (1)

[Claims] [Claim 1] International Telegraph and Telephone Advisory Committee (CCITT
In the system that performs data communication using the recommended X21 interface line terminator (hereinafter referred to as DCE), the state of the signal line (R line, I line) from DCE is monitored and the same state continues for 24 bits or more. And a circuit that generates an interrupt signal indicating only a disconnection instruction state, and a circuit that can set and release interrupt suppression by an interrupt signal for each state detection by a control program, This interrupt signal is used as a trigger to analyze the state of the signal line (“0” state or “1” state), and when the line state becomes a state where there is no need to monitor other than a disconnection instruction (connected state) Is
A line status monitoring method characterized in that the control program suppresses the 24-bit same-state detection interrupt so that only the disconnection instruction is given so that the same 24-bit state and the disconnection instruction state can be detected separately.