JPH05300187A - Modem with bit interleaving function for digital multiple radio system - Google Patents

Abstract

PURPOSE:To perform the appropriate demodulation of signals at a demodulator by flattening out spectrums of signals outputted after bit interleaving processing at a modulator. CONSTITUTION:A modulator 51 outputs modulated signals after inserting auxiliary signals S supplied from the outside to the overhead parts of plural data frames inputted in parallel from the outside, performing the bit interleaving processing, and further by performing the modulation with a prescribed frequency carrier. The modulated signal is demodulated at a demodulator, and the plural numbers of data inputted to the modulator 51 is obtained. When the auxiliary signals S are supplied, the auxiliary signals S are outputted to the modulator 51. When the auxiliary signals S are interrupted, the detection of the interruption is performed, and an auxiliary signal generating means 41 to output the arbitrarily varying signals to the modulator 51 at the time of this interruption detection is connected to the modulator 51. Thus, even when the auxiliary signals S are interrupted, the substituted signals are inserted to the overhead parts, so that the spectrums of the modulated signals outputted from the modulator 51 are flattened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a modulator / demodulator with a bit interleaving function in a digital multiplex radio system.

In the digital multiplex radio system, a multi-level modulation technique is adopted in order to improve the frequency utilization efficiency and increase the capacity of the line, and the 256QAM system is currently put into practical use. As the number of values increases, it becomes an important issue to improve the resistance to distortion such as fading and overcome the deterioration factors (amplitude / delay distortion) of the device itself.

In order to overcome the problem, transversal automatic equalization technology and error correction technology have been introduced. However, those techniques basically target random errors and cannot expect much effect on continuous errors (burst errors).

In particular, a burst error may occur due to the radar of a ship or the like in the offshore section, and application of the bit interleaving technique is being considered as a coping method.

[0005]

2. Description of the Related Art FIG. 5 is a block diagram of a conventional modulator with a bit interleave function, and FIG. 6 is a block diagram of a demodulator with a bit interleave function. However, the modulator is used in the transmitter and the demodulator is used in the receiver.

The modulator shown in FIG. 5 includes a speed conversion circuit 1 and
The transmission signal processing circuit 2, the overhead bit insertion circuit (OH insertion circuit) 3, the FEC (Forward Error Control)
l) Encoder 4 and transmission side bit interleave circuit 5
, D / A converters 6, 7 and low-pass filters 8, 9
, Mixers 10 and 11, and 90-degree hybrid circuit 12
, Local oscillator 13, and in-phase hybrid circuit 14
And an amplifier 15 are provided.

The speed conversion circuit 1 converts the speed of the first data D1 and the second data D2 input in frame units according to the clock signal CLK. Here, high-speed conversion is performed to insert more bits in one frame.

Further, assuming that the first data D1 is of the 16QAM system, it becomes I1 channel and I2 channel data out of four values, and the second data D2 becomes Q1 channel and Q2 channel data.

The transmission signal processing circuit 2 performs a summation process on the data output from the speed conversion circuit 1 and outputs the data. O
The H insertion circuit 3 inserts an auxiliary signal into the overhead bit (OH bit) of the data frame output from the speed conversion circuit 2 and outputs it.

However, it is assumed that, for example, 2 bits of overhead bits are prepared per frame. Further, the auxiliary signal is used for a DSC (digital service channel) signal, an ID code (route identification code), etc. used for device monitoring and meetings of the wireless system.

The FEC encoder 4 receives data bits and OH in the data frame output from the OH insertion circuit 3.
An FEC encoding operation is performed on the bits, and a check bit is added after the OH bit and output.

The bit interleave circuit 5 on the transmission side is provided with an FE.
A multi-frame in which a predetermined number of one frame (FEC word) sent from the C encoder 4 is collected is rearranged into a predetermined data string by using a RAM or the like and output.

The operation performed by the transmitting side bit interleave circuit 5 will be described with reference to FIGS. 7 and 8. Figure 7 (a)
Shows a schematic configuration of a multi-frame input to the bit interleave circuit 5. As can be seen from this figure, the multi-frame is composed of m × N bits, and
Frames each consisting of m bits up to 2, 3, ..., M are arranged in N number of # 1, # 2, ..., #N.

This multi-frame is arranged by the bit interleave circuit 5 in the concept as shown in FIG.
One frame (FEC word) is I1, Q1, I2, Q
4 values of 2 are arranged horizontally (horizontally), and 1
Data bit area, OH bit area,
It is arranged with the FEC check bit area.

Further, each of the frames # 1, # 2, ..., #N is vertically arranged in order from the first frame # 1. The number N of frames arranged in the vertical direction will be referred to as the interleaving depth.

In the case of reading in frame units from the array configuration shown in FIG. 8, the first bit is read in the vertical direction. That is, 4 bits of I1, Q1, I2, Q2 of the first bit
Values are read sequentially from # 1 to #N, which is shown in FIG.
As shown in (b), it becomes the data of the first frame. Similarly, the four values of I1, Q1, I2, and Q2 of the second bit are sequentially read from # 1 to #N, which becomes the data of the second frame, ... Finally, I1 and Q of the m-th bit.
The four values of 1, 1, 2 and Q2 are sequentially read from # 1 to #N, and this becomes the data of the m-th frame.

The data shown in FIG. 7B read from the transmission side bit interleave circuit 5 in this manner is N ×.
It has m bits, and has the same data length as the multi-frame shown in FIG.

The data output from the transmission side bit interleave circuit 5 is input to the D / A converters 6 and 7, converted into an analog signal, and then input to the mixers 10 and 11 via the low pass filters 8 and 9. To be done.

The local oscillator 13 outputs a signal in the intermediate frequency band, and the 90-degree hybrid circuit 12 shifts the phase of the signal in the intermediate frequency band by 90 degrees, and outputs one to the mixer 10 and the other to the mixer 11.

The mixers 10 and 11 modulate the signals output from the low pass filters 8 and 9 with the signals in the intermediate frequency band output from the 90-degree hybrid circuit 12 and output the modulated signals.

The in-phase synthesis hybrid circuit 14 synthesizes the modulation signals output from the mixers 10 and 11 and outputs the synthesized signals. Here, quadrature amplitude modulation will be performed. The signal output from the hybrid circuit 14 is amplified by the amplifier 15 and output. This output IF signal S
Since 1 is an intermediate frequency band, it is then converted into a radio frequency by a transmission circuit (not shown) and output from an antenna (not shown).

Next, the demodulator shown in FIG. 6 will be described. This demodulator demodulates the signal modulated by the modulator shown in FIG. 5, and includes a signal branching hybrid circuit 21 and
Mixers 22 and 23, a 90-degree hybrid circuit 24,
Local oscillator 25, low-pass filters 26, 27, A
/ D converters 28 and 29, a waveform equalizing circuit 30, a receiving side bit interleaving circuit 31, and a word synchronizing circuit 32.
, FEC decoder 33, overhead bit sampling circuit (OH sampling circuit) 34, and received signal processing circuit 35
And a speed conversion circuit 36.

The signal branching hybrid circuit 21 has an I
The F signal S1 'is input, but the IF signal S1' is
The radio signal sent from the transmitter having the above-mentioned modulator is obtained by being received by an antenna (not shown) of the receiver and then converted into an intermediate frequency band by a receiver circuit (not shown). is there.

The signal branching hybrid circuit 21 has an IF
The signal S1 'is branched and output to the mixers 22 and 23.
Since the mixers 22 and 23 are supplied with the signals in the intermediate frequency band output from the local oscillator 25 having a 90-degree phase difference in the 90-degree hybrid circuit 24, I1, Q
Signals of four-valued components of 1, I2, Q2 are demodulated.

These demodulated signals are input to A / D converters 28 and 29 via low-pass filters 26 and 27, converted into digital signals, that is, data, and input to a waveform equalizing circuit 30.

The waveform equalization circuit 30 corrects the distortion caused by the effect of fading in the wireless communication section and outputs it to the receiving side bit interleaving circuit 31. The receiving side bit interleaving circuit 31 performs the reverse data processing to that of the transmitting side bit interleaving circuit 5. That is, since the data string shown in FIG. 7B is input to the receiving side bit interleave circuit 31, the data string shown in FIG. 7A is converted and output to the word synchronization circuit 32.

The word synchronizing circuit 32 has I1, Q1, I
The four-valued word synchronization of 2 and Q2 (frame synchronization) is obtained and output to the FEC decoder 33. FEC decoder 33
Are the data bits and OH in the synchronized frame.
The FEC decoding operation is performed on the bits to remove the check bits and output to the OH extracting circuit 34.

The OH extracting circuit 34 extracts the auxiliary signal S'inserted in the overhead bit (OH bit) of the data frame and outputs it to the reception signal processing circuit 35.
The reception signal processing circuit 35 performs data difference processing and the like, and outputs it to the speed conversion circuit 36.

The speed conversion circuit 36 inputs the data into the speed conversion circuit 1 shown in FIG.
The output is reduced to the same speed as D2. By this speed conversion, the first data D1 ', the second data D2' and the clock signal CLK 'are output.

[0030]

In the modulator / demodulator with the bit interleaving function described above, when the frame overhead input to the transmitting side bit interleaving circuit 5 shown in FIG. 5 is fixed data, the bit interleaving process is performed. N bits of continuous fixed data are generated in the frame which is output from the bit interleave circuit 5 on the transmitting side.

This occurs when the auxiliary signal S is not input to the OH insertion circuit 3. If the auxiliary signal S is not input, the auxiliary signal S is not inserted in the overhead of the frame. In this case, the overhead data is fixed data of "0" or "1".

When a frame in which fixed data is inserted into the overhead is input to the transmission side bit interleave circuit 5, as can be seen from the data configuration shown in FIG. 8, N fixed data are arranged in the vertical direction in the OH bit portion. become.
When reading this, since the OH bit is read in the vertical direction, N bits of continuous fixed data are generated in the read frame.

When such continuous fixed data exists in the frame, the IF signal S1 output from the modulator
A flat spectrum may not be obtained due to protrusions in the spectrum. When demodulating the IF signal S1 having such a non-flat spectrum, there is a problem that a proper signal cannot be obtained.

Further, as the interleave depth N shown in FIG. 8 becomes deeper, fixed data becomes continuous. In this case,
Since the spectrum of the IF signal S1 becomes less flat, proper demodulation of the signal becomes more difficult.

The present invention has been made in view of the above point, and it is possible to flatten the spectrum of the signal output after the bit interleaving processing in the modulator, whereby the demodulator can obtain a proper signal. An object of the present invention is to provide a modulator / demodulator with a bit interleaving function in a digital multiplex radio system capable of demodulating.

[0036]

FIG. 1 shows the principle of the present invention. In the figure, reference numeral 51 denotes a modulator, which inserts an auxiliary signal S supplied from the outside into the overhead parts of a plurality of data frames input in parallel from the outside, performs bit interleaving, and further uses a predetermined frequency carrier. A modulation signal is output by performing modulation.

The modulated signal is demodulated by a demodulator (not shown) to obtain a plurality of data input to the modulator 51. The characteristic part of the present invention is that the auxiliary signal S
Is supplied, the auxiliary signal S is supplied to the modulator 5
1 and the auxiliary signal S is interrupted, the disconnection is detected, and a signal that changes arbitrarily at the time of the disconnection is detected by the modulator 5
This is because the auxiliary signal generating means 41 for outputting to 1 is connected to the modulator.

[0038]

According to the present invention described above, when the auxiliary signal S is supplied to the auxiliary signal generating means, the auxiliary signal S is supplied from the auxiliary signal generating means 41 to the modulator 51, and the auxiliary signal S is interrupted. In this case, the signal that changes arbitrarily is the modulator 51.
Is supplied to.

Therefore, even if the auxiliary signal S is interrupted, a signal in place of the auxiliary signal S is inserted into the overhead portion of a plurality of data frames input in parallel to the modulator 51.
Conventionally, when the auxiliary signal S is disconnected, the data in the overhead section is fixed data, so the same data is continuously output after the bit interleaving process. In this case, the modulation output from the modulator 51 is performed. In some cases, the spectrum of the signal became flat and disappeared, making it impossible to properly demodulate.

However, in the present invention, since some data is always inserted in the overhead section, such a problem can be eliminated.

[0041]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram of a modulator with a bit interleaving function according to an embodiment of the present invention. In this figure, parts corresponding to those of the conventional example shown in FIG.

The modulator of the embodiment shown in FIG. 2 is different from the modulator of the conventional example shown in FIG. 5 in that an auxiliary signal generating circuit 41 is provided and a signal S ″ output from this auxiliary signal generating circuit 41 is provided.
Is input to the OH insertion circuit 3.

An example of the configuration of the auxiliary signal generation circuit 41 is shown in FIGS. The auxiliary signal generation circuit shown in FIG. 3 includes a signal disconnection detection circuit 42, a random signal generator 43, and a selector 44.

The signal disconnection detection circuit 42 detects the disconnection state when the auxiliary signal S described in the conventional example is no longer supplied and outputs the disconnection detection signal S2 to the selector 44.

The random signal generator 43 is for generating a random signal R. The selector 44 uses the auxiliary signal S
Is supplied, the auxiliary signal S is selected and
The H signal S ″ is output to the OH insertion circuit 3, the random signal R is selected when the disconnection detection signal S2 is supplied, and this is output as the OH signal S ″.

According to the auxiliary signal generating circuit having such a configuration, normally, when the auxiliary signal S is supplied, the auxiliary signal S is selected by the selector 44 and output to the OH inserting circuit 3 as the OH signal S ″. To be done.

On the other hand, when the auxiliary signal S is interrupted, the disconnection of the signal S is detected by the signal disconnection detection circuit 42 and the disconnection detection signal S2 is supplied to the selector 44, so that the selector 44 causes the random signal generator 43. The random signal R from is selected and is output to the OH insertion circuit 3 as the OH signal S ″.

The auxiliary signal generating circuit shown in FIG. 4 is composed of a signal disconnection detecting circuit 42, a selector 44, and a data flip-flop (DFF) 45. DFF
The main signal data, which is the first and second data D1 and D2 shown in FIG. 2, is supplied to 45, which is the clock signal CL.
When triggered by K, it is supplied to the selector 44 as the signal R1.

Normally, when the auxiliary signal S is supplied, the auxiliary signal S is selected by the selector 44 and output as the OH signal S ″ to the OH insertion circuit 3. On the other hand, when the auxiliary signal S is interrupted. The disconnection of the signal S is detected by the signal disconnection detection circuit 42, and the disconnection detection signal S2 is output to the selector 4
4, the output signal R1 of the DFF 45 is selected by the selector 44, and this is O as the OH signal S ″.
It is output to the H insertion circuit 3.

As described above, in any of the auxiliary signal generation circuits shown in FIGS. 3 and 4, when the auxiliary signal S is interrupted, the OH signal S ″ is supplied to the OH insertion circuit 3 instead, so that it is the same as the conventional one. The OH bit of the data frame never becomes fixed data.

That is, unlike the conventional case, the overhead of the frame input to the transmission side bit interleave circuit 5 does not become fixed data. Therefore, even when the bit interleaving process is performed, N bits of continuous fixed data are not generated in the frame output from the transmission side bit interleaving circuit 5, and the spectrum of the IF signal S1 output from the modulator is When the IF signal S1 having a flat spectrum is demodulated, a proper signal can be obtained.

[0052]

As described above, according to the present invention,
The spectrum of the signal output after the bit interleaving process in the modulator can be flattened, and thus the demodulator can demodulate the signal appropriately.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a block diagram of a modulator with a bit interleaving function according to an embodiment of the present invention.

FIG. 3 is an internal configuration diagram of an auxiliary signal generation circuit shown in FIG.

FIG. 4 is another internal configuration diagram of the auxiliary signal generation circuit shown in FIG.

FIG. 5 is a block diagram of a conventional modulator with a bit interleaving function.

FIG. 6 is a block configuration diagram of a demodulator with a bit interleaving function.

[Fig. 7] Fig. 7 is an explanatory diagram of a frame configuration after pre-processing of bit interleaving processing.

FIG. 8 is a data configuration diagram for explaining bit interleaving.

[Explanation of symbols]

 41 auxiliary signal generating means 51 modulator S auxiliary signal

Continuation of the front page (72) Inventor Satoshi Aikawa 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation

Claims (4)

[Claims] 1. A bit interleaving process is performed after an auxiliary signal (S) externally supplied to a modulator (51) is inserted into an overhead part of a plurality of data frames input in parallel to the modulator (51). A modulator / demodulator with a bit interleaving function in a digital multiplex radio system that outputs a modulated signal by performing modulation with a predetermined frequency carrier and demodulates the modulated signal with a demodulator to obtain a plurality of data input to the modulator In, if the auxiliary signal (S) is supplied, the auxiliary signal
(S) is output to the modulator (51), if the auxiliary signal (S) is interrupted, the disconnection is detected, and a signal that arbitrarily changes when this disconnection is detected is output to the modulator (51). Auxiliary signal generating means (41) is provided, and the signal output from the auxiliary signal generating means (41) is inserted into the overhead part of a plurality of data frames input in parallel to the modulator (51). A modulator / demodulator with a bit interleaving function in a digital multiplex radio system characterized by the above. 2. The auxiliary signal generating means (41) includes a signal disconnection detection circuit for detecting a disconnection state of the auxiliary signal (S) and outputting the detection signal, and a random signal generator for generating a random signal. , The random signal is selected and output when the detection signal is supplied, and the auxiliary signal in other cases
2. A modulator / demodulator with a bit interleaving function in the digital multiplex radio system according to claim 1, further comprising a selecting means for selecting and outputting (S). 3. The auxiliary signal generating means (41) detects a disconnection state of the auxiliary signal (S) and outputs a detection signal, and a signal disconnection detection circuit triggered by a clock signal. Output from the flip-flop, and a selecting means for selecting and outputting the output signal of the flip-flop when the detection signal is supplied, and selecting and outputting the auxiliary signal (S) in other cases. A modulator / demodulator with a bit interleaving function in the digital multiplex radio system according to claim 1, which is configured. 4. A speed conversion circuit for converting the speed of a plurality of data input in parallel to the modulator (51) in accordance with a clock signal, and a parallel output from the speed conversion circuit. The signal output from the auxiliary signal generation means (41) is inserted into the transmission signal processing circuit that mainly performs the summation processing on the data and the overhead portion of the parallel data frame output from the speed conversion circuit. An overhead bit insertion circuit for outputting as an output, an FEC encoder for performing FEC encoding operation on data bits and overhead bits in the parallel data frame output from the overhead bit insertion circuit, and adding a check bit for output, and the FEC Bit data that performs bit interleaving that converts parallel data output from the encoder into a predetermined array and outputs the converted data. Talive circuit, first and second D / A converters for converting parallel data output from the bit interleave circuit into analog signals, and interruption of analog signals output from the first and second D / A converters First and second low-pass filters that pass a frequency component lower than the frequency, a first mixer that mixes a signal output from the first low-pass filter with a signal in an intermediate frequency band, and a second low-pass filter A second mixer that mixes the output signal with a signal that is 90 degrees out of phase with the signal in the intermediate frequency band that is supplied to the first mixer and outputs the mixed signal, and a signal that is output from the first and second mixers. A bit interleaving function in the digital multiplex radio system according to claim 1, characterized in that it is configured by including an in-phase combining hybrid circuit for combining and outputting. Demodulator.