JPH05300137A - Data repeating device - Google Patents

Abstract

PURPOSE:To provide the data repeating device which enables multistage repetition even when the accuracy of reception and transmission system is a little adverse. CONSTITUTION:A repeater station is provided with a transmitting clock generator 3 to generate peculiar transmitting clocks, and a first conversion timing generator 2 generates a first conversion timing signal synchronized with a received clock based on a break timing signal obtained from received serial data by an unblined detector 1. Similarly, a second conversion timing signal generator 4 generates a second conversion timing signal synchronized with the transmitting clock based on the break timing signal and at a buffer 5, transmitting serial data are obtained by a serial/parallel converter 6 and a parallel/serial converter 7 controlled by the first and second conversion timing signals respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data relay device for handling digital data surrounded by delimiters for identifying effective data.

[0002]

2. Description of the Related Art A LAN is a communication network generally used by a single organization, and bit serial data communication is performed between devices interconnected via this network. There are a ring-type network and a bus-type network as LAN configuration methods. In the ring type network, as shown in FIG. 5A, a plurality of terminals 52 are connected by a transmission medium 51 in a ring shape. A signal transmitted from a certain terminal is reproduced and relayed by an adjacent terminal, sequentially transferred, and finally returned to the original terminal. Normally, all terminals share the transmission medium 51 by distributed control in an equal relationship,
Data can be transferred between arbitrary terminals.

As shown in FIG. 5B, serial data transferred in such a ring type network is composed of a token representing an access right to a transmission medium and a frame representing information to be transferred. As shown by the slanted lines in the figure, the token and the frame are surrounded by a delimiter code 53 composed of 2 bits or more for identifying valid data, and this is transferred with a preamble (invalid period) 54 of a predetermined number of bits interposed. To be done. For the token access operation, the terminal that captures the token and sends the frame
There are a method of collecting the frame returned after making a round of the transmission medium and sending the token to the transmission medium at the same time, and a method of releasing and sending the token immediately after sending the frame.

Usually, in such a ring type network,
A specific station has a transmission clock generator stabilized by a crystal oscillator, and other relay stations use the reception clock as it is as a transmission clock. In other words, if we focus on the clock system, there is a master-slave relationship (for example,
JP-A-58-150346 and JP-A-60-226.
249).

[0005]

However, if transmission is performed with the reception clock, the number of relay stations is limited by the accuracy of the reception / transmission system of the relay station, or the number of relay stations of high accuracy is set according to the required number of relay stations. A reception and transmission system is required. Further, if the received data is converted as serial data from the received clock synchronization to the transmitted clock synchronization, the circuit configuration becomes complicated (see US Pat. No. 4,674,086, FIG. 10). The present invention has been made in view of such circumstances, and an object of the present invention is to provide a data relay apparatus capable of multistage relay even if the accuracy of the receiving and transmitting systems is somewhat poor.

[0006]

SUMMARY OF THE INVENTION The present invention provides a data relay apparatus for receiving, relaying and transferring serial data surrounded by a delimiter code for identifying valid data via a transmission medium. A delimiter code detecting means for extracting the delimiter code from the synchronized received serial data to generate a delimiter timing signal, and a delimiter timing signal obtained by this means for generating a first conversion timing signal synchronized with the received clock. Means, a transmission clock generating means for generating a transmission clock having expected accuracy in a normal state, and a delimiter timing signal obtained from the delimiter code detecting means for generating a second conversion timing signal synchronized with the transmission clock. Means for parallelizing the received serial data with the first conversion timing signal. It is characterized in that a buffer having a parallel / serial converter for converting serial / parallel converter, and the parallel data obtained again serial data at the second conversion timing signal to be converted.

[0007]

In the present invention, the transmission at the reception clock is stopped and the transmission clock generating means unique to the relay station is provided. Then, a delimiter timing signal is generated from the reception serial data, and a first conversion timing signal synchronized with the reception clock and a second conversion timing signal synchronized with the transmission clock are generated.
The conversion timing signal is generated, the received serial data is once converted into parallel data by the first conversion timing signal, the serial data is converted again by the second conversion timing signal, and the converted serial data is transmitted. There is. With this method, the accuracy of the receiving and transmitting systems is independent of the number of relay stations.
It is sufficient that the accuracy up to the upstream or downstream relay station is guaranteed. Therefore, it is possible to construct a data transmission system capable of multistage relay even if the accuracy of the receiving and transmitting systems is somewhat poor.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of a data relay device according to an embodiment of the present invention. This data relay device includes a delimiter code detector 1 which detects a delimiter code of received serial data and generates a delimiter timing signal, a delimiter timing signal obtained from the delimiter code detector 1 and a reception clock CK1.
From the conversion timing signal generator 2 for generating the first conversion timing signal, the transmission clock generator 3 for generating the transmission clock CK2 stabilized by the crystal oscillator, and the second from the transmission clock CK2 and the delimiter timing signal. It is composed of a conversion timing generator 4 for generating a conversion timing signal, and a buffer 5 for initializing and transmitting the received serial data in frame units.

The buffer 5 comprises a serial / parallel converter 6 for once converting the received serial data into parallel data in 8-bit units, and a parallel / serial conversion for converting the obtained parallel data into serial data again synchronized with the transmission clock. It is composed of a container 7. It is the first conversion timing signal obtained from the first conversion timing signal generator 2 that controls the serial / parallel converter 6. The first conversion timing signal generator 2 is specifically,
It is a frequency dividing circuit that divides the reception clock CK1 by 1/8. Further, it is the second conversion timing signal obtained from the second conversion timing signal generator 4 that controls the parallel / serial converter 7, and the second conversion timing signal generator 4 is specifically, It is a frequency divider circuit that divides the transmission clock CK2 obtained from the transmission clock generator 3 by 1/8.

FIG. 2 is a diagram for explaining the operation of the circuit of this embodiment. Ideally, the first conversion timing signal and the second conversion timing signal have the same constant period, but there is a phase difference δ as illustrated. Although not shown in FIG. 1, this phase difference δ is, for example, the second conversion timing signal generator 4
It is obtained by providing a predetermined delay circuit inside. The magnitude of this phase difference δ is preferably set to about half the cycle of the first and second conversion timing signals. In that case, the phase difference δ is initialized every time a delimiter code is input, so that a shift between the first and second conversion timing signals that allows a half cycle to be accumulated between frames can be allowed.

As shown in FIG. 2, the reception clock CK1 is
The received serial data is converted from serial data to parallel data every 8 bits by the first conversion timing signal divided by 1/8, and the transmission clock CK2 is further reduced by 1/8.
The parallel data is converted into transmission serial data by the frequency-divided second conversion timing signal.

In the case of this embodiment, since the transmission clock peculiar to the relay station is used, the clock cycle deviation is not accumulated by the multistage relay unlike the conventional system in which the reception clock is used as the transmission clock as it is. In the case of this embodiment, since initialization is performed in frame units, if the frame length is limited, the accuracy of the receiving and transmitting systems is required. For example, in a transmission code differential Manchester format with a data length of 146 bytes, the maximum allowable range of the phase difference δ between the first conversion timing signal and the second conversion timing signal is 8 bits for the transmission code. (Byte) × 8 (bit) × 2 = 0.34 [%]. Accuracy of general crystal oscillator is 100 [ppm]
Then, in this embodiment, the maximum error between the reception clock and the transmission clock is 200 [ppm] = 0.02 [%], which means that there is a sufficient margin.

There may be a case where the frequency error between the transmission clock and the reception clock is large and the frame length is large, and initialization cannot be performed by serial / parallel conversion or parallel / serial conversion in units of 8 bits as in the above embodiment. FIG. 3 shows the situation. Cycle T1 of the first conversion timing signal and cycle T1 of the second conversion timing signal
When the error of 2 is large, this is accumulated in one frame, and when the phase difference δ becomes larger than the period T1 of the first conversion timing signal, the serial / parallel converter 6 overflows in the buffer 5 and correct transmission is performed. No data can be obtained. In such a case, it is desirable to be able to variably control the size of serial / parallel conversion and parallel / serial conversion of the buffer.

FIG. 4 shows a relay station configuration of such an embodiment. The parts corresponding to those in FIG. 1 are designated by the same reference numerals as those in FIG. The first conversion timing signal generator 2 is 1 /
It has an 8 frequency divider 21 and a 1/16 frequency divider 22, and also has a selector 23 that switches between these outputs. Similarly, the second conversion timing signal generator 4 also has a 1/8 frequency divider 41 and a 1/16 frequency divider 42, and a selector 43 that switches between these outputs. The buffer 5 has two 8-bit serial /
Parallel converters 6a and 6b and two 8-bit parallel / serial converters 7a and 7b are provided. The selector 8 is for selecting whether to use only one of the two 8-bit serial / parallel converters 6a and 6b, that is, 6b, or to connect these in series to expand to a 16-bit serial / parallel converter. It is provided in. A comparator 9, a determiner 10 and a timer 11 are provided to control the selectors 23, 43 and 8 of these respective units.

In a normal state, the selector 23 selects the output of the 1/8 frequency divider 21, and the selector 43 selects the 1/8 frequency divider 41.
, And the selector 8 directly receives the received serial data into the 8-bit serial / parallel converter 6b. This state is the same as in the previous embodiment. When the 8-bit serial / parallel converter overflows, the comparator 9 detects this by the overlap of the first and second timing signals, as shown in FIG. Each selector 23, 43, 8 is switched by 10. That is, the outputs of the 1/16 frequency dividers 22 and 42 are selected in the first and second conversion timing signal generators 2 and 4, respectively, and the serial / parallel converters 6a and 6b are connected in series in the buffer 5. As a result, it is possible to switch between serial / parallel conversion and parallel / serial conversion in 16-bit units.

If the phase difference between the cycle of the first conversion timing signal and the second conversion timing signal is smaller than half the tolerance measured by the timer 11 for a certain period of time, the selectors 8, 23 and 43 cause Reduce the size of serial / parallel conversion and parallel / serial conversion. Considering the data transfer time, it is preferable that the sizes of the serial / parallel conversion and the parallel / serial conversion are small. Therefore, in this embodiment, for example, the frame length is long and the transmission clock is received while maintaining the high speed performance in the normal state. When the deviation from the clock causes a problem, size conversion is performed to enable reliable data initialization.

[0017]

As described above, according to the present invention, by using the station-specific clock as the transmission clock,
It is possible to provide a data relay device that enables the configuration of a data transfer system even when the accuracy of a receiver or a transmitter is somewhat poor when performing multi-stage relay.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a data relay device according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the apparatus according to the embodiment.

FIG. 3 is a view for explaining the operation of the apparatus according to the embodiment.

FIG. 4 is a diagram showing a configuration of a day relay device according to another embodiment.

FIG. 5 is a diagram showing a configuration of a ring network.

[Explanation of symbols]

1 ... Separator code detector, 2 ... First timing signal generator, 3 ... Transmitter, 4 ... Second timing signal generator, 5
... buffer, 6 ... serial / parallel converter, 7 ... parallel / serial converter, 8, 23, 42 ... selector, 9
... comparator, 10 ... determiner, 11 ... timer.

Claims (2)

[Claims] 1. A data relay apparatus for receiving, relaying, and transferring serial data surrounded by a delimiter code for identifying valid data via a transmission medium, from the received serial data synchronized with a receiving clock. A delimiter code detecting means for extracting a code and generating a delimiter timing signal, a means for generating a first conversion timing signal synchronized with the received clock from the delimiter timing signal obtained by this means, and expected in a normal state Transmission clock generation means for generating a transmission clock with accuracy; means for generating a second conversion timing signal synchronized with the transmission clock from the delimiter timing signal obtained from the delimiter code detection means; A serial / power converter that converts parallel data using the first conversion timing signal. Barrel transducer, and the resulting data relay apparatus characterized by comprising: a buffer having a parallel / serial converter, a for converting parallel data again into serial data by the second conversion timing signal. 2. A data relay device for receiving, relaying, and transferring serial data enclosed by a delimiter code for identifying valid data via a transmission medium, from the received serial data synchronized with a reception clock. A delimiter code detecting means for extracting a code and generating a delimiter timing signal, a means for generating a first conversion timing signal synchronized with the received clock from the delimiter timing signal obtained by this means, and expected in a normal state Transmission clock generation means for generating a transmission clock with accuracy; means for generating a second conversion timing signal synchronized with the transmission clock from the delimiter timing signal obtained from the delimiter code detection means; A serial / power converter that converts parallel data using the first conversion timing signal. Parallel converter, and a buffer having a parallel / serial converter for converting the obtained parallel data into serial data again by the second conversion timing signal, and a serial / parallel converter and a parallel / serial converter in the buffer And a means for variably controlling the size of the data relay device.