JPH05299824A - Mounting method of electronic component - Google Patents

Mounting method of electronic component

Info

Publication number
JPH05299824A
JPH05299824A JP9839792A JP9839792A JPH05299824A JP H05299824 A JPH05299824 A JP H05299824A JP 9839792 A JP9839792 A JP 9839792A JP 9839792 A JP9839792 A JP 9839792A JP H05299824 A JPH05299824 A JP H05299824A
Authority
JP
Japan
Prior art keywords
electronic component
circuit board
electrode
electronic
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9839792A
Other languages
Japanese (ja)
Inventor
Hachirou Nakamichi
八郎 中逵
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP9839792A priority Critical patent/JPH05299824A/en
Publication of JPH05299824A publication Critical patent/JPH05299824A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518—Translational movements
    • H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/328—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding

Abstract

PURPOSE:To provide a mounting method of electronic component in which insufficient soldering can be suppressed by reducing the number of soldering steps of electronic component. CONSTITUTION:The electronic component mounting method comprises a step for applying an electronic component adhesive 23 onto a circuit board 21, a step for mounting an electronic component 24 onto the adhesive 23 applied on the circuit board 21, and a step for electrically connecting an electrode 28 on the electronic component 24 side with an electrode 22 on the circuit board 21 side through a metal wire 26, wherein the number of steps for soldering the electronic component is reduced thus realizing a high density electronic circuit in which insufficient soldering is suppressed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は電子機器の回路基板形成
を行なうための電子部品の実装方法に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting method of electronic parts for forming a circuit board of an electronic device.

【０００２】[0002]

【従来の技術】近年、電気製品の小型軽量化にともな
い、プリント基板上に電子部品を実装する方法としては
表面実装方法が主流になっている。2. Description of the Related Art In recent years, the surface mounting method has become the main method for mounting electronic components on a printed circuit board with the reduction in size and weight of electric products.

【０００３】以下、図３を参照しながら従来の電子部品
の表面実装方法について説明する。１は回路基板で、２
はこの回路基板１上に設けた電極である。３はクリーム
半田で、このクリーム半田３はスキージ４が回路基板１
と平行に移動するときメタルマスク５に形成された孔を
通過し、電極２上に印刷される（図３（ａ）参照）。次
に電子部品６は印刷された前記クリーム半田３上に電子
部品装着機によって装着される（図３（ｂ）参照）。装
着された電子部品６は回路基板１ごとリフロー装置に投
入され、所定の温度の中を通過するときにクリーム半田
３中の金属成分が再溶融され、電極２と電子部品６の電
極７との間は溶融したクリーム半田３で電気接続が行な
われ、このクリーム半田３は最終的に冷却固化する（図
３（ｃ）参照）。クリーム半田３の周辺にはクリーム半
田３中に含まれているフラックス成分が残り、そのまま
では腐食や電気絶縁性の低下など信頼性の面で不安があ
るため、洗浄槽８内でトリフロルエタンやフレオンなど
の洗浄剤によって洗浄が行なわれる（図３（ｄ）参
照）。A conventional surface mounting method for electronic components will be described below with reference to FIG. 1 is a circuit board, 2
Is an electrode provided on the circuit board 1. 3 is cream solder, and in this cream solder 3, the squeegee 4 is the circuit board 1
When it moves in parallel with, it passes through the hole formed in the metal mask 5 and is printed on the electrode 2 (see FIG. 3A). Next, the electronic component 6 is mounted on the printed cream solder 3 by the electronic component mounting machine (see FIG. 3B). The mounted electronic component 6 is put into the reflow device together with the circuit board 1, and when passing through a predetermined temperature, the metal component in the cream solder 3 is remelted, and the electrode 2 and the electrode 7 of the electronic component 6 are separated from each other. Electrical connection is made with the melted cream solder 3 during this period, and this cream solder 3 is finally cooled and solidified (see FIG. 3C). The flux component contained in the cream solder 3 remains around the cream solder 3, and if left as it is, there is concern about reliability such as corrosion and deterioration of electrical insulation. Cleaning is performed with a cleaning agent such as Freon (see FIG. 3D).

【０００４】近年、オゾン層破壊などの環境問題からフ
レオン洗浄剤の使用が困難であるため、低残渣のクリー
ム半田の開発が急がれている。電子部品を表面実装する
ためのもう１つの方法としてディップ方法がある。以
下、図４に基づいて説明すると、11は回路基板、12はこ
の回路基板11上に設けた電極であり、前記回路基板11上
に電子部品用接着剤13をディスペンサー14により塗布す
る（図４（ａ）参照）。次に電子部品15を前記電極12に
またがるように電子部品用装着機にて装着する（図４
（ｂ）参照）。その後専用の硬化装置あるいはリフロー
装置などで前記接着剤13を硬化させ、電子部品15を回路
基板11に仮固定する（図４（ｃ）参照）。仮固定した電
子部品15と回路基板11にはフラックスを塗布し、ディッ
プ装置16で溶融したクリーム半田17にさらし、電極12と
電子部品15の電極15ａを電気的に接続する（図４（ｄ）
参照）。その後、最終的にクリーム半田17と前記フラッ
クスを洗浄槽18内でトリフロリエタンやフレオンなどの
洗浄剤19によって洗浄する（図４（ｅ）参照）。In recent years, it has been urgent to develop a low-residue cream solder because it is difficult to use a Freon cleaning agent due to environmental problems such as ozone layer depletion. There is a dipping method as another method for surface-mounting electronic components. Hereinafter, referring to FIG. 4, 11 is a circuit board, 12 is an electrode provided on the circuit board 11, and the electronic component adhesive 13 is applied to the circuit board 11 by a dispenser 14 (FIG. 4). (See (a)). Next, the electronic component 15 is mounted by an electronic component mounting machine so as to straddle the electrode 12 (see FIG. 4).
(See (b)). After that, the adhesive 13 is cured by a dedicated curing device or a reflow device, and the electronic component 15 is temporarily fixed to the circuit board 11 (see FIG. 4C). Flux is applied to the temporarily fixed electronic component 15 and the circuit board 11 and exposed to the cream solder 17 melted by the dip device 16 to electrically connect the electrode 12 and the electrode 15a of the electronic component 15 (FIG. 4 (d)).
reference). After that, the cream solder 17 and the flux are finally cleaned in a cleaning tank 18 with a cleaning agent 19 such as trifloretane or freon (see FIG. 4 (e)).

【０００５】[0005]

【発明が解決しようとする課題】しかしながら前記図３
に示す方法では、印刷工程、リフロー工程、洗浄工程が
必要であり、また図４に示す方法においてもリフロー工
程、フラックス塗布工程、半田付工程、洗浄工程が必要
である。各工程において課題があり、印刷工程ではパタ
ーンの微細化に伴ない、印刷かすれ、にじみ、加熱によ
るダレやクリーム半田そのものの劣化に伴なう半田ボー
ルの発生などの課題がある。リフロー工程では電極間の
温度差やクリーム半田量のばらつきによる部品立ちや半
田ブリッジの発生、その他加熱による部品自体の劣化と
いう課題がある。洗浄工程においては洗浄剤の使用によ
るコストアップやオゾン層破壊などの環境問題からフレ
オン系溶剤の使用が困難となるため、低残渣のクリーム
半田やディップ半田付用フラックスの開発が望まれてい
る。However, the above-mentioned FIG.
The method shown in (1) requires a printing step, a reflow step, and a washing step, and the method shown in FIG. 4 also requires a reflow step, a flux applying step, a soldering step, and a washing step. There are problems in each process, and in the printing process, there are problems such as print faintness, bleeding, sagging due to heating, and generation of solder balls due to deterioration of cream solder itself. In the reflow process, there are problems of component standing and solder bridge due to temperature difference between electrodes and variation of cream solder amount, and deterioration of the component itself due to heating. In the cleaning process, it is difficult to use the Freon solvent due to the cost increase due to the use of the cleaning agent and the environmental problems such as ozone layer destruction. Therefore, it is desired to develop a flux for low-residue cream solder or dip soldering.

【０００６】本発明はこのような課題を解決するもの
で、電子部品の半田付工程を削減して、半田付不良を少
なくできるようにした電子部品の実装方法を提供するこ
とを目的とするものである。The present invention solves such a problem, and an object of the present invention is to provide a mounting method of an electronic component that can reduce the soldering process of the electronic component and reduce the soldering failure. Is.

【０００７】[0007]

【課題を解決するための手段】この課題を解決するため
に本発明は、回路基板上に電子部品用接着剤を塗布する
工程と、電子部品を回路基板上の前記電子部品用接着剤
上に装着する工程と、電子部品側の電極と回路基板側の
電極を金属ワイヤで電気的に接続する工程とからなるも
のである。また本発明は、電子部品を回路基板上に縦型
に装着して回路基板に対向する電子部品の一方の電極を
回路基板上に半田付けし、電子部品の他方の電極と回路
基板側の電極を金属ワイヤで電気的に接続する工程とか
らなるものである。In order to solve this problem, the present invention provides a step of applying an adhesive for electronic parts on a circuit board, and an electronic part on the adhesive for electronic parts on the circuit board. It comprises a mounting step and a step of electrically connecting the electrode on the electronic component side and the electrode on the circuit board side with a metal wire. Further, according to the present invention, an electronic component is vertically mounted on a circuit board, one electrode of the electronic component facing the circuit board is soldered on the circuit board, and the other electrode of the electronic component and the electrode on the circuit board side are mounted. Is electrically connected with a metal wire.

【０００８】[0008]

【作用】この構成によれば、電子部品は塗布された電子
部品用接着剤の上に装着され、加熱硬化して回路基板に
固定され、電子部品側の電極と回路基板側の電極を金属
ワイヤで接続することにより電子部品と回路基板との電
気的接続がなされる。According to this structure, the electronic component is mounted on the applied electronic component adhesive, is cured by heating and is fixed to the circuit board, and the electrode on the electronic component side and the electrode on the circuit board side are metal wires. The electrical connection between the electronic component and the circuit board is made by connecting with.

【０００９】[0009]

【実施例】以下、本発明の実施例について、図面に基づ
いて説明する。まず、図１に示す第１実施例について説
明すると、21は回路基板、22はこの回路基板21上に設け
た電極であり、前記電極22間における前記回路基板21の
表面にはエポキシ樹脂かアクリレート樹脂を主成分とす
る電子部品用接着剤23が塗布されている（図１（ａ）参
照）。電子部品24は電子部品装着機のヘッド25にかかえ
られ前記電極22間にまたがるように位置されて前記電子
部品用接着剤23上に載置される（図１（ｂ）参照）。こ
の後、接着剤23は専用の硬化装置で紫外線あるいは熱に
より硬化され、電子部品24を回路基板21に固定する。Embodiments of the present invention will be described below with reference to the drawings. First, referring to the first embodiment shown in FIG. 1, 21 is a circuit board, 22 is an electrode provided on the circuit board 21, and an epoxy resin or an acrylate is provided on the surface of the circuit board 21 between the electrodes 22. An electronic component adhesive 23 containing resin as a main component is applied (see FIG. 1A). The electronic component 24 is held by the head 25 of the electronic component mounting machine, is positioned so as to straddle the electrodes 22, and is mounted on the electronic component adhesive 23 (see FIG. 1B). After that, the adhesive 23 is cured by ultraviolet rays or heat by a dedicated curing device, and the electronic component 24 is fixed to the circuit board 21.

【００１０】次に、電子部品24を電極22に電気的接続を
行なう方法を説明する。先端があらかじめ高電圧のスパ
ークで丸形状となっている金ワイヤー26が挿通されたキ
ャピラリー27が下降して（図１（ｃ）参照）、電子部品
24の電極28に衝突する。このとき同時に超音波と熱を印
加することにより、金ワイワー26の先端部と電子部品24
の電極28間に金属結合が生じる（図１（ｄ）参照）。続
いてキャピラリー27は上昇し、前記回路基板21の電極22
側に移動して衝突し、このときにも前記と同様に超音波
と熱を印加する。金ワイヤー26はキャピラリー27の移動
量と同等量を供給され、電子部品24の電極28と回路基板
21の電極22間の電気的接続を得る（図１（ｅ）参照）。
次にキャピラリー27と金ワイヤー26は同時に上昇し、電
極22との接合部で金ワイヤー26を破断する（図１（ｆ）
参照）。このときの条件として超音波振動数は60Ｈｚ、
加熱は 120℃〜 150℃で行ない、金ワイヤー26を電極2
2、28に押し付ける圧力は 100ｇ程度が適切である。な
お、図面では電子部品24の一方の電極28を回路基板21の
一方の電極22に金ワイヤー26で接続しているが、同様に
電子部品24の他方の電極28を回路基板21の他方の電極22
に接続するものである。 次に図２に示す第２実施例に
ついて説明すると、この実施例は電子部品を回路基板上
に縦型に装着する場合であって、回路基板21上の２つの
電極22の内、一方の電極22上にクリーム半田29を印刷塗
布しておく（図２（ａ）参照）。次に電子部品24をこの
電子部品24の一方の電極28が回路基板21のクリーム半田
29が印刷塗布された一方の電極22に接触するように立て
て回路基板21に載せ、直ちにリフロー装置で加熱して回
路基板21に対する電子部品24の固定を行なう（図２
（ｂ）参照）。その後は電子部品24の上端に位置する他
方の電極28と回路基板21の他方の電極22を前記第１実施
例と同様の方法で、キャピラリー27により金ワイヤー26
を用いて接続するものである（図２（ｃ）〜（ｆ）参
照）。Next, a method of electrically connecting the electronic component 24 to the electrode 22 will be described. The capillary 27 into which the gold wire 26, which has a round shape with a high-voltage spark in advance, is inserted, descends (see FIG. 1 (c)), and the electronic component
Collide with 24 electrodes 28. At this time, by applying ultrasonic waves and heat at the same time, the tip of the gold wire 26 and the electronic component 24
A metallic bond is generated between the electrodes 28 of the electrodes (see FIG. 1D). Subsequently, the capillary 27 rises and the electrode 22 of the circuit board 21 is
It moves to the side and collides, and at this time, ultrasonic waves and heat are applied in the same manner as described above. The gold wire 26 is supplied with an amount equivalent to the movement amount of the capillary 27, and the electrode 28 of the electronic component 24 and the circuit board.
An electrical connection between the 21 electrodes 22 is obtained (see FIG. 1 (e)).
Next, the capillary 27 and the gold wire 26 rise at the same time, and the gold wire 26 is broken at the joint with the electrode 22 (Fig. 1 (f)).
reference). As the condition at this time, the ultrasonic frequency is 60 Hz,
Heating is performed at 120 ℃ ~ 150 ℃, gold wire 26 electrode 2
It is appropriate that the pressure applied to 2, 28 is about 100g. In the drawing, one electrode 28 of the electronic component 24 is connected to one electrode 22 of the circuit board 21 by a gold wire 26, but similarly, the other electrode 28 of the electronic component 24 is connected to the other electrode of the circuit board 21. twenty two
To connect to. Next, the second embodiment shown in FIG. 2 will be described. In this embodiment, an electronic component is vertically mounted on a circuit board, and one of two electrodes 22 on the circuit board 21 is mounted. Cream solder 29 is applied by printing onto 22 (see FIG. 2A). Next, the electronic component 24 is connected to the electrode 28 of the electronic component 24 with cream solder on the circuit board 21.
29 is erected so as to be in contact with one electrode 22 printed and applied, and placed on the circuit board 21, and immediately heated by a reflow device to fix the electronic component 24 to the circuit board 21 (see FIG. 2).
(See (b)). After that, the other electrode 28 located on the upper end of the electronic component 24 and the other electrode 22 of the circuit board 21 are connected to the gold wire 26 by the capillary 27 in the same manner as in the first embodiment.
For connection (see FIGS. 2 (c) to 2 (f)).

【００１１】[0011]

【発明の効果】以上の説明からも本発明によれば、前記
従来の方法に比べて電子部品の半田付工程を削減でき、
半田付不良の少ない電子回路の高密度化が実現できるも
のである。As described above, according to the present invention, the number of steps for soldering electronic components can be reduced as compared with the conventional method.
It is possible to realize high-density electronic circuits with few soldering defects.

【図面の簡単な説明】[Brief description of drawings]

【図１】（ａ）〜（ｆ）は本発明の第１実施例における
電子部品の実装方法の工程図である。1A to 1F are process diagrams of a method for mounting an electronic component according to a first embodiment of the present invention.

【図２】（ａ）〜（ｆ）は本発明の第２実施例における
電子部品の実装方法の工程図である。FIGS. 2A to 2F are process diagrams of a method for mounting electronic components according to a second embodiment of the present invention.

【図３】（ａ）〜（ｄ）は第１の従来例における電子部
品の実装方法の工程図である。3A to 3D are process diagrams of a mounting method of an electronic component in a first conventional example.

【図４】（ａ）〜（ｅ）は第２の従来例における電子部
品の実装方法の工程図である。FIG. 4A to FIG. 4E are process diagrams of a mounting method for electronic components in a second conventional example.

【符号の説明】[Explanation of symbols]

21 回路基板 22 電極 23 電子部品用接着剤 24 電子部品 25 ヘッド 26 金ワイヤー 27 キャピラリー 28 電極 29 クリーム半田 21 Circuit board 22 Electrode 23 Adhesive for electronic parts 24 Electronic part 25 Head 26 Gold wire 27 Capillary 28 Electrode 29 Cream solder

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 回路基板上に電子部品用接着剤を塗布す
る工程と、電子部品を回路基板上の前記電子部品用接着
剤上に装着する工程と、電子部品側の電極と回路基板側
の電極を金属ワイヤで電気的に接続する工程とからなる
電子部品の実装方法。1. A step of applying an electronic component adhesive on a circuit board, a step of mounting an electronic component on the electronic component adhesive on a circuit board, an electrode on the electronic component side and a circuit board side electrode. A method for mounting an electronic component, which comprises a step of electrically connecting electrodes with a metal wire. 【請求項２】 電子部品を回路基板上に縦型に装着して
回路基板に対向する電子部品の一方の電極を回路基板上
に半田付けし、電子部品の他方の電極と回路基板側の電
極を金属ワイヤで電気的に接続する工程とからなる電子
部品の実装方法。2. An electronic component is vertically mounted on a circuit board, one electrode of the electronic component facing the circuit board is soldered on the circuit board, and the other electrode of the electronic component and the electrode on the circuit board side. A method for mounting an electronic component, which comprises the step of electrically connecting the components with a metal wire.
JP9839792A 1992-04-20 1992-04-20 Mounting method of electronic component Pending JPH05299824A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9839792A JPH05299824A (en) 1992-04-20 1992-04-20 Mounting method of electronic component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9839792A JPH05299824A (en) 1992-04-20 1992-04-20 Mounting method of electronic component

Publications (1)

Publication Number Publication Date
JPH05299824A true JPH05299824A (en) 1993-11-12

Family

ID=14218707

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9839792A Pending JPH05299824A (en) 1992-04-20 1992-04-20 Mounting method of electronic component

Country Status (1)

Country Link
JP (1) JPH05299824A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19714544B4 (en) * 1996-04-09 2004-04-01 Rohm Co. Ltd. Method of mounting a solid electrolytic capacitor on a printed circuit board and arrangement of the capacitor and the board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19714544B4 (en) * 1996-04-09 2004-04-01 Rohm Co. Ltd. Method of mounting a solid electrolytic capacitor on a printed circuit board and arrangement of the capacitor and the board

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