JPH05299631A - Solid-state image sensing device - Google Patents

Abstract

PURPOSE:To provide a solid-state image sensing device, in which the generation of a potential barrier between the charge storage section of a light-receiving section and an overflow control gate section is inhibited and excessively generated charges from the charge storage section are discharged effectively by the overflow control gate. CONSTITUTION:In a light-receiving section 2 adoption HAD sensor structure, the hole storage layer 12 of the light-receiving section 2 is formed in a shape that the layer 12 is separated from an overflow control gate 4 by a specified distance (d), and no potential barrier is generated between the overflow control gate 4 and a charge storage section 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device,
In particular, HAD (Holl Accumulation Diode) in which a hole accumulation layer is laminated on the region where charges generated by photoelectric conversion are accumulated.
The present invention relates to a solid-state imaging device having a sensor array in which a plurality of light receiving parts having a sensor structure are arranged.

[0002]

2. Description of the Related Art As a specific example of this type of solid-state image pickup device,
Consider the case of a CCD (Charge Coupled Device) linear sensor. Multiple light-receiving units (specifically, photo sensors)
FIG. 2 shows a specific example of a CCD linear sensor having an overflow control gate (OFCG) and an overflow drain (OFD) adjacent to a sensor array consisting of the above array. This CCD linear sensor is generally called a linear sensor with a horizontal overflow drain.

In FIG. 2, the signal charge generated in the light receiving portion 2 of the sensor array 1 is surrounded by a shift gate 3, an overflow control gate 4 and a channel stop portion (not shown) formed between the light receiving portion 2. Accumulated in the area. FIG. 6 is a potential diagram taken along the line AA ′ of FIG. 2 during charge accumulation. FIG. 6A shows a state in which no voltage is applied to the overflow control gate, and FIG.
Indicates the state where voltage is applied. At the time of charge accumulation, a voltage is applied to the gate electrode of the shift gate 3 and the gate electrode of the overflow control gate 4 so that the potential of the semiconductor substrate portion therebelow becomes shallower than the potential of the light receiving portion 2. .. The signal charges generated in the light receiving section 2 are accumulated in the region surrounded by these potential barriers.

By the way, when a sensor having an HAD structure (hereinafter referred to as HAD sensor) is used for the light receiving section 2,
In order to suppress the dark current generated from the Si / SiO ₂ interface, it is necessary to form a hole accumulation layer which is a P-type semiconductor layer (P ⁺ layer) having a high impurity concentration on the surface of the semiconductor substrate. The N-type semiconductor layer and the P-type semiconductor layer are provided under the hole accumulation layer (P ⁺ layer) and serve as a photodiode.

[0005]

In FIG. 7, conventionally, when forming the hole accumulation layer 12, ions were implanted so that the overflow control gate 4 was self-aligned to form a P ⁺ layer. .. In this case, P ⁺
Impurities (generally, boron) that form the layer diffuse by the heat treatment after the ion implantation step, and as shown in FIG. 7, enter under the gate electrode 16 of the overflow control gate 4.

Here, a potential is applied to the overflow control gate 4 to increase the potential under the gate electrode 16, but as shown in the potential diagram of FIG. 8, the P ⁺ layer is diffused. In the region, a barrier having a potential lower than that of the channel portion of the overflow control gate 4 (hereinafter referred to as a potential barrier) is formed around the isolation portion of the overflow control gate 4 to which no voltage is applied. This potential barrier becomes an obstacle when a voltage is externally applied to the overflow control gate 4 to discharge charges. Further, since a certain potential barrier is not formed due to the influence of diffusion variation, there is a problem that variation between elements becomes large when controlling from the outside.

Therefore, according to the present invention, generation of a potential barrier between the charge storage portion of the light receiving portion and the overflow control gate portion can be suppressed, and excess charge generated by the overflow control gate can be effectively discharged. An object is to provide a solid-state imaging device.

[0008]

In the solid-state image pickup device according to the present invention, a plurality of light receiving portions having a hole accumulation layer laminated on a region for accumulating charges generated corresponding to incident optical information are arranged. Sensor array, a charge transfer path that is arranged on one side of the sensor array to transfer charges, a shift gate that reads out the charge accumulated in each light receiving portion of the sensor array to the charge transfer path, and the sensor array Between the hole accumulation layer and the overflow control gate. Is provided with a predetermined distance.

[0009]

In the light receiving portion having the HAD sensor structure, the hole accumulation layer is formed so as to be separated from the overflow control gate by a predetermined distance, so that a potential barrier is formed between the overflow control gate portion and the charge accumulation portion. It will not occur. As a result, it is possible to effectively discharge the excess generated charge from the charge storage portion by the overflow control gate.

[0010]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 2 is a configuration diagram of a linear sensor having a lateral overflow drain to which the present invention is applied. In this linear sensor, the signal charge generated in each light receiving section 2 of the sensor array 1 is surrounded by the shift gate 3, the overflow control gate 4, and the channel stop section 14 (see FIG. 3) separating the respective light receiving sections 2. The structure is such that it is accumulated in the area. In this case, as is clear from FIG. 1, the charge storage section 13 has the same impurity profile as the light receiving section 2.

The signal charge accumulated in each light receiving portion 2 of the sensor array 1 is read out to the charge transfer path 5 via the shift gate 3 by the charge read pulse φrog input from the charge read pulse input terminal 11. The charge transfer path 5 sequentially transfers signal charges by two-phase driving by two-phase clock pulses φ1 and φ2. An output section 6 is provided at the output end of the charge transfer path 5, and the signal charge transferred by the charge transfer path 5 is converted into an electric signal by the output section 6 and derived from the output terminal 7.

An overflow drain 8 is arranged on the opposite side of the charge transfer path 5 with respect to the sensor array 1. The overflow drain 8 is electrically low in resistance and is fixed to the potential V1 applied to the drain terminal 9. The potential is made deeper than that of the light receiving section 2, and the gate pulse φcg is applied to the gate terminal 10.
6 is applied, the charges accumulated in the charge accumulating portion 13 flow out toward the overflow drain 8 by an amount higher than the potential of the overflow control gate 4 as shown in FIG. 6B. The charges that have flowed out are discharged through the overflow drain 8.

FIG. 1 is a sectional view taken along the line AA 'in FIG. In the figure, the light receiving portion 2 has a HAD sensor structure, and on the N-type semiconductor layer forming the charge storage portion 13, a P ⁺ semiconductor layer (normal P Type semiconductor with higher impurity concentration than type semiconductor)
The hole accumulation layer 12 made of is laminated. The hole storage layer 12 is formed with a predetermined distance d from the overflow control gate 4.

When the P ⁺ semiconductor layer is ion-implanted in the formation of the hole accumulation layer 12, an ion implantation mask 15 is formed at a distance from the overflow control gate 4 as shown in FIG. To do. Regarding the distance D between the opening end of the ion implantation mask 13 and the overflow control gate 4, the impurities forming the P ⁺ semiconductor layer are diffused by the thermal process and do not enter below the gate electrode 16 of the overflow control gate 4. Try to take about.

In this way, when impurities (usually boron) are ion-implanted, the hole storage layer 12 is formed into the state shown in FIG.
As is apparent from (b), the overflow control gate 4 does not get under the gate electrode 16 even after the diffusion process. FIG. 4 shows the potential distribution of the light receiving section 2 and the overflow control gate 4 in this configuration.

According to the above structure, the diffusion of the P ⁺ semiconductor is N
Since it is inside the type semiconductor layer, no potential barrier is generated between the overflow control gate 4 and the charge storage portion 13. Accordingly, when it is desired to discharge the excess charge from the light receiving portion 2 from the overflow control gate 4 to use the device, it is uniquely determined by the potential of the channel portion formed under the gate electrode 16 of the overflow control gate 4. It

Further, considering the dispersion of impurity diffusion, P
By determining the offset amount D of the ion implantation mask 15 of the ⁺ layer from the overflow control gate 4, it is possible to eliminate the influence of variations in impurity diffusion and to prevent the overflow characteristics from changing depending on the device.

In the above embodiment, as apparent from FIG. 3A, one side 15a of the opening end of the ion implantation mask 15 is formed parallel to the overflow control gate 4 with an offset amount D. As shown in FIG. 5, only a part 15b on one side of the opening end of the ion implantation mask 15 'is covered with the overflow control gate 4a.
Alternatively, they may be formed in parallel with an offset amount D. According to this structure, the hole storage layer 12 has an offset shape in which only the region corresponding to a part 15b on one side of the opening end of the ion implantation mask 15 'is isolated from the overflow control gate 4. .. In other words, if there is one region in which no potential barrier is generated for each pixel, a path for discharging excess generated charges can be secured, so that the intended purpose can be achieved.

[0019]

As described above, according to the present invention,
In the light receiving portion having the HAD sensor structure, the hole storage layer is formed so as to be separated from the overflow control gate, so that no potential barrier is generated between the overflow control gate portion and the charge storage portion. Further, there is an effect that it is possible to effectively discharge the excess generated charge from the charge storage portion by the overflow control gate, and to suppress the variation due to the manufacturing process.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing an embodiment of the present invention, showing a cross section taken along the line AA ′ of FIG.

FIG. 2 is a configuration diagram of a linear sensor with an overflow drain.

3A and 3B are configuration diagrams of an ion implantation step at the time of forming a hole accumulation layer in the present invention, FIG. 3A is a plan view thereof, and FIG. 3B is a sectional view thereof.

FIG. 4 is a potential diagram of a light receiving portion and an overflow control gate portion according to the present invention.

FIG. 5 is a plan view showing another embodiment of the present invention.

6A and 6B are potential diagrams of a linear sensor with an overflow drain, in which FIG. 6A shows a state in which no voltage is applied to the overflow control gate, and FIG. 6B shows a state in which a voltage is applied.

FIG. 7 is a cross-sectional view of an ion implantation process when forming a hole storage layer in a conventional example.

FIG. 8 is a potential diagram of a light receiving portion and an overflow control gate portion according to a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Sensor array 2 Light receiving part (photo sensor) 3 Shift gate 4 Overflow control gate 5 Charge transfer path 6 Output part 8 Overflow drain 12 Hole storage layer 13 Charge storage part 15, 15 'Ion implantation mask

Claims (2)

[Claims] 1. A sensor array in which a plurality of light receiving portions having a hole storage layer stacked on a region for storing charges generated corresponding to incident light information are arranged, and one side of the sensor array. A charge transfer path for transferring charge, a shift gate for reading the charge accumulated in each light receiving portion of the sensor array to the charge transfer path, and a shift gate for the sensor array on the opposite side of the charge transfer path. An overflow drain arranged and an overflow control gate for sweeping charges accumulated in each light receiving portion of the sensor array to the overflow drain, and a predetermined distance between the hole accumulation layer and the overflow control gate. A solid-state imaging device comprising: 2. The solid-state imaging device according to claim 1, wherein a predetermined distance is provided between the overflow control gate and a part of the hole accumulation layer adjacent to the overflow control gate. ..