JPH05299618A - Cmos type gate array lsi - Google Patents

Cmos type gate array lsi

Info

Publication number
JPH05299618A
JPH05299618A JP4084342A JP8434292A JPH05299618A JP H05299618 A JPH05299618 A JP H05299618A JP 4084342 A JP4084342 A JP 4084342A JP 8434292 A JP8434292 A JP 8434292A JP H05299618 A JPH05299618 A JP H05299618A
Authority
JP
Japan
Prior art keywords
output
input
gate
lsi
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4084342A
Other languages
Japanese (ja)
Inventor
Hiroetsu Yamazaki
裕悦 山崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4084342A priority Critical patent/JPH05299618A/en
Publication of JPH05299618A publication Critical patent/JPH05299618A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent the generation of the difference of the transmission time while effectively utilizing input-output blocks by using a gate for an output having large driving capacity when a signal from the outside of an LSI is transmitted over a logic circuit. CONSTITUTION:Output from the gates 14 for inputs of input-output blocks 13 are connected to inputs to gates 15 for outputs, and outputs from the gates 15 for the outputs are connected to a plurality of logic circuits in an LSI.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明はＣＭＯＳ型ゲートアレー
ＬＳＩ、特に、多ピン，大規模高密度高集積のＣＭＯＳ
型ゲートアレーＬＳＩに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS type gate array LSI, and more particularly to a multi-pin, large-scale, high-density, highly integrated CMOS.
Type gate array LSI.

【０００２】[0002]

【従来の技術】従来、この種のＣＭＯＳ型ゲートアレー
ＬＳＩは、図５に示す様に、ＬＳＩ５１の周辺部にパッ
ド５２とそのパッド５２に対応して入出力ブロック５３
が配置されている。この入出力ブロック５３は、パッド
５２と、入力側を接続した入力用ゲート５４と、パッド
５２に信号を出力する時のために用意された出力用ゲー
ト５５とで構成されている。パッド５２と入力用ゲート
５４が信号入力用とて使用される時は出力用ゲート５５
は使用されない。2. Description of the Related Art Conventionally, in this type of CMOS gate array LSI, as shown in FIG. 5, a pad 52 is provided in the peripheral portion of the LSI 51 and an input / output block 53 corresponding to the pad 52.
Are arranged. The input / output block 53 is composed of a pad 52, an input gate 54 having an input side connected, and an output gate 55 prepared for outputting a signal to the pad 52. When the pad 52 and the input gate 54 are used for signal input, the output gate 55
Is not used.

【０００３】図６は、図５で示す用な信号入力の構成を
取る場合のＬＳＩ内部の一般的な回路図である。パッド
６２と入力用ゲート６４の入力が接続され、また入力用
ゲート６４の出力は２段で構成された分配用、ゲート６
７の入力に接続されている。分配用ゲート６７の後段の
各々の出力は各々複数の論理回路６６に接続されてい
る。ここで負荷駆動能力の低い入力用ゲート６４の出力
から、複数の論理回路６６までの信号伝達時間を短くす
るために複数段の分配用ゲート６７が配置されている。FIG. 6 is a general circuit diagram inside the LSI in the case of adopting the signal input configuration shown in FIG. The pad 62 and the input of the input gate 64 are connected to each other, and the output of the input gate 64 is a two-stage distribution gate 6
7 inputs. Each output of the latter stage of the distribution gate 67 is connected to each of the plurality of logic circuits 66. Here, a plurality of stages of distribution gates 67 are arranged in order to shorten the signal transmission time from the output of the input gate 64 having a low load driving capability to the plurality of logic circuits 66.

【０００４】[0004]

【発明が解決しようとする課題】上述した従来のＣＭＯ
Ｓ型ゲートアレーＬＳＩで、ＬＳＩ外部の信号をパッド
から入出力ブロックの入力用ゲートを通してＬＳＩ内部
の論理回路に伝達される時、入出力ブロックで大きな面
積を占める出力用ゲートが使用されず、面積効率が悪
い。また複数段の分配用ゲートを必要とするためこれら
分配用ゲートの遅延時間の差による、論理回路への信号
伝達時間の差が生じるという欠点がある。DISCLOSURE OF THE INVENTION The conventional CMO described above
In the S-type gate array LSI, when a signal external to the LSI is transmitted from the pad through the input gate of the input / output block to the logic circuit inside the LSI, the output gate occupying a large area in the input / output block is not used, ineffective. Further, since a plurality of distribution gates are required, there is a disadvantage that a difference in signal transmission time to the logic circuit occurs due to a difference in delay time between these distribution gates.

【０００５】[0005]

【課題を解決するための手段】第１の発明のＣＭＯＳ型
ゲートアレーＬＳＩは、入力用ゲートの出力側を同一入
出力ブロックの出力用ゲートの入力側に接続すると共に
出力用ゲートの出力側を複数の論理回路に接続する。In a CMOS type gate array LSI of the first invention, the output side of the input gate is connected to the input side of the output gate of the same input / output block and the output side of the output gate is connected. Connect to multiple logic circuits.

【０００６】第２の発明のＣＭＯＳ型ゲートアレーＬＳ
Ｉは、前記入力用ゲートの出力側を他の複数の入出力ブ
ロックの出力ゲートの入力側に接続し、さらに各々の出
力ゲートの出力側は各々複数の論理回路に接続してい
る。A CMOS type gate array LS of the second invention.
I connects the output side of the input gate to the input side of the output gates of the other plurality of input / output blocks, and the output side of each output gate is connected to the plurality of logic circuits.

【０００７】第３の発明のＣＭＯＳ型ゲートアレーＬＳ
Ｉは、前記各々の出力ゲートの最終段のＣＭＯＳトラン
ジスタの個数の可変する構造を有している。CMOS type gate array LS of the third invention
I has a structure in which the number of CMOS transistors at the final stage of each output gate is variable.

【０００８】[0008]

【実施例】次に本発明について図面を参照して説明す
る。The present invention will be described below with reference to the drawings.

【０００９】図１は本発明の第１の実施例を示すブロッ
ク図である。パッド１２と、入力用ゲート１４と、出力
用ゲート１５とを有する入出力ブロック１３とが１対１
でＬＳＩ１１の周辺部に複数配置されている。ここで入
力側がパッド１２に接続された入力用ゲート１４の出力
側が入出力ブロック１３の出力用ゲート１５の入力に接
続され、さらに出力用ゲート１５の出力側からＬＳＩ内
部に配線が出ている。FIG. 1 is a block diagram showing a first embodiment of the present invention. The pad 12, the input gate 14, and the input / output block 13 having the output gate 15 have a one-to-one correspondence.
A plurality of LSIs are arranged in the peripheral portion of the LSI 11. Here, the output side of the input gate 14 whose input side is connected to the pad 12 is connected to the input of the output gate 15 of the input / output block 13, and wiring is extended from the output side of the output gate 15 to the inside of the LSI.

【００１０】図２は、図１に示す実施例の論理図であ
る。パッド２２と入力用ゲート２４の入力との接続並び
に入力用ゲート２４の出力と出力用ゲート２５の入力と
の接続は図１と同様である。図２はさらに出力用ゲート
２５の出力が複数の論理回路へ接続されている。図１と
図２から判る用に、ＬＳＩ外部より入力される信号はパ
ッドと入力用ゲート及び出力用ゲートを通り、論理回路
に入力される。ここで出力用ゲートは負荷駆動能力が大
きいため、分配回路なしで直接、複数の論理回路を駆動
出来る。FIG. 2 is a logical diagram of the embodiment shown in FIG. The connection between the pad 22 and the input of the input gate 24 and the connection between the output of the input gate 24 and the input of the output gate 25 are the same as in FIG. In FIG. 2, the output of the output gate 25 is further connected to a plurality of logic circuits. As can be seen from FIGS. 1 and 2, a signal input from the outside of the LSI passes through the pad, the input gate and the output gate and is input to the logic circuit. Since the output gate has a large load driving capability, it is possible to directly drive a plurality of logic circuits without a distribution circuit.

【００１１】図３は本発明の第２の実施例を示すブロッ
ク図である。第１の実施例で説明した用にパッドと入出
力ブロックは１対１でＬＳＩ３１の周辺部に複数配置さ
れている。ここで入出力ブロック３３の入力用ゲート３
４の入力はパッド３２に接続され、入力用ゲート３４の
出力は自己の入出力ブロック３３の出力用ゲート３５の
入力及び二つの他の入出力ブロック３６と３８の出力用
ゲート３７と３９の入力に接続されている。図３の構成
を取ることにより、図１と図２で説明した構成よりも、
さらにより多くの論理回路を駆動することが可能とな
る。FIG. 3 is a block diagram showing a second embodiment of the present invention. As described in the first embodiment, a plurality of pads and input / output blocks are arranged in a one-to-one relationship in the peripheral portion of the LSI 31. Here, the input gate 3 of the input / output block 33
The input of 4 is connected to the pad 32, and the output of the input gate 34 is the input of the output gate 35 of its own input / output block 33 and the input of the output gates 37 and 39 of the two other input / output blocks 36 and 38. It is connected to the. By adopting the configuration shown in FIG. 3, the configuration shown in FIGS.
Further, it becomes possible to drive more logic circuits.

【００１２】図４は本発明の第３の実施例を示す入出力
ブロックの回路図である。一般に出力用ゲート４２の最
終段回路４３は複数のＰ型ＭＯＳトランジスタ同時の並
列接続と複数のｎ型ＭＯＳトランジスタ同士の並列接続
とで構成されるインバーター回路となっている。従っ
て、Ｐ型トランジスタ４４をＰ型トランジスタ４５から
切離し、またｎ型トランジスタ４６をｎ型トランジスタ
４７から切離すことにより出力用ゲート４２の負荷駆動
能力を調整することが出来る。これによって図２で説明
した論理図の出力用ゲート２５に図３で述べた出力用ゲ
ート４２を使用することにより、パッドから論理回路ま
での信号伝達時間を調整することが出来る。FIG. 4 is a circuit diagram of an input / output block showing a third embodiment of the present invention. Generally, the final stage circuit 43 of the output gate 42 is an inverter circuit composed of a plurality of P-type MOS transistors simultaneously connected in parallel and a plurality of n-type MOS transistors connected in parallel. Therefore, the load driving capability of the output gate 42 can be adjusted by disconnecting the P-type transistor 44 from the P-type transistor 45 and disconnecting the n-type transistor 46 from the n-type transistor 47. As a result, by using the output gate 42 described in FIG. 3 as the output gate 25 of the logic diagram described in FIG. 2, the signal transmission time from the pad to the logic circuit can be adjusted.

【００１３】[0013]

【発明の効果】以上説明したように本発明の第１は、入
力用ゲートと出力用ゲートを有する入出力ブロックにお
いて、入力用ゲートの出力と出力用ゲートの入力を接続
し、さらに出力用ゲートの出力を複数の論理回路に接続
することにより、分配用ゲートを使用する時の信号伝達
時間の差を無くすことが出来る。As described above, according to the first aspect of the present invention, in the input / output block having the input gate and the output gate, the output of the input gate is connected to the input of the output gate, and the output gate is further connected. By connecting the output of the above to a plurality of logic circuits, it is possible to eliminate the difference in signal transmission time when the distribution gate is used.

【００１４】また本発明の第２は、前記第１で述べた入
力用ゲートの出力を他の入出力ブロックの出力用ゲート
の入力にも接続し、またこれら出力用ゲートを出力を各
々複数の論理回路に接続することにより、分配用ゲート
を不要にすることが出来、ＬＳＩの面積を効率的に使用
することが出来る。According to a second aspect of the present invention, the output of the input gate described in the first section is also connected to the input of the output gate of another input / output block, and these output gates each have a plurality of outputs. By connecting to the logic circuit, the distribution gate can be eliminated and the area of the LSI can be used efficiently.

【００１５】また本発明の第３は、出力用ゲートの最終
段回路のトランジスタ数を負荷の論理回路数に合わせて
調整することにより、他の入出力ブロックとの信号伝達
時間を一致させることが出来るという効果がある。In a third aspect of the present invention, by adjusting the number of transistors in the final stage circuit of the output gate according to the number of logic circuits in the load, the signal transmission time with other input / output blocks can be matched. There is an effect that you can.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の第１の実施例を示すブロック図であ
る。FIG. 1 is a block diagram showing a first embodiment of the present invention.

【図２】図１に示す実施例の論理図である。FIG. 2 is a logical diagram of the embodiment shown in FIG.

【図３】本発明の第２の実施例を示すブロック図であ
る。FIG. 3 is a block diagram showing a second embodiment of the present invention.

【図４】本発明の第３の実施例を示す回路図である。FIG. 4 is a circuit diagram showing a third embodiment of the present invention.

【図５】従来の一例を示すブロック図である。FIG. 5 is a block diagram showing a conventional example.

【図６】図５のブロック配線を使用した時の論理図であ
る。FIG. 6 is a logic diagram when the block wiring of FIG. 5 is used.

【符号の説明】[Explanation of symbols]

１１，３１，５１ ＬＳＩ １２，２２，３２，５２，６２ パッド １３，２３，３３，３６，３８，５３，６３ 入出力
ブロック １４，２４，３４，４１，５４，６４ 入力用ゲート １５，２５，３５，３７，３９，４２，５５ 出力用
ゲート ２６，６６ 論理回路 ４３ 出力用ゲート最終段回路 ６７ 分配用ゲート ４４，４５ Ｐ型ＭＯＳトランジスタ ４６，４７ ｎ型ＭＯＳトランジスタ11, 31, 51 LSI 12, 22, 32, 52, 62 Pads 13, 23, 33, 36, 38, 53, 63 Input / output block 14, 24, 34, 41, 54, 64 Input gates 15, 25, 35, 37, 39, 42, 55 output gate 26, 66 logic circuit 43 output gate final stage circuit 67 distribution gate 44, 45 P-type MOS transistor 46, 47 n-type MOS transistor

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 複数のパッドとそのパッドからの信号を
入力とする入力用ゲートとまたパッドへ信号を出力する
ための出力用ゲートとで構成された複数の入出力ブロッ
クと、前記パッドと入出力ブロックとが各々１対１で配
置された構造を有するＣＭＯＳ型ゲートアレーＬＳＩに
おいて、入力側のパッドに接続した入力用ゲートの出力
側を同一入出力ブロック内の出力用ゲートの入力側に接
続し、さらに出力用ゲートの出力側がＬＳＩ内部の複数
の論理回路に接続していることを特徴とするＣＭＯＳ型
ゲートアレーＬＳＩ。1. A plurality of input / output blocks composed of a plurality of pads, an input gate for receiving a signal from the pad and an output gate for outputting a signal to the pad, and the pad and the input / output block. In a CMOS type gate array LSI having a structure in which output blocks are arranged in a one-to-one correspondence, the output side of an input gate connected to an input side pad is connected to the input side of an output gate in the same input / output block. Further, a CMOS type gate array LSI characterized in that the output side of the output gate is connected to a plurality of logic circuits inside the LSI. 【請求項２】 入力用ゲートの出力側を他の複数の入出
力ブロックの出力用ゲートの入力側に接続し、それぞれ
の出力用ゲートの出力側がそれぞれ複数の論理回路に接
続した請求項１記載のＣＭＯＳ型ゲートアレーＬＳＩ。2. The output side of the input gate is connected to the input side of the output gates of the other plurality of input / output blocks, and the output side of each output gate is connected to each of the plurality of logic circuits. CMOS type gate array LSI. 【請求項３】 前記出力用ゲートにおいて、最終段のＣ
ＭＯＳトランジスタの個数を可変する請求項１および２
記載のＣＭＯＳ型ゲートアレーＬＳＩ。3. The C for the final stage in the output gate
3. The number of MOS transistors is variable, according to claim 1 and 2.
The described CMOS type gate array LSI.
JP4084342A 1992-04-07 1992-04-07 Cmos type gate array lsi Withdrawn JPH05299618A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4084342A JPH05299618A (en) 1992-04-07 1992-04-07 Cmos type gate array lsi

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4084342A JPH05299618A (en) 1992-04-07 1992-04-07 Cmos type gate array lsi

Publications (1)

Publication Number Publication Date
JPH05299618A true JPH05299618A (en) 1993-11-12

Family

ID=13827839

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4084342A Withdrawn JPH05299618A (en) 1992-04-07 1992-04-07 Cmos type gate array lsi

Country Status (1)

Country Link
JP (1) JPH05299618A (en)

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Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19990608