JPH05299446A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05299446A JPH05299446A JP9511292A JP9511292A JPH05299446A JP H05299446 A JPH05299446 A JP H05299446A JP 9511292 A JP9511292 A JP 9511292A JP 9511292 A JP9511292 A JP 9511292A JP H05299446 A JPH05299446 A JP H05299446A
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor device
- silicon substrate
- lead frame
- back surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
半導体装置を金属フレーム上にダイボンディングするた
めの半導体基板の裏面構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a back surface structure of a semiconductor substrate for die bonding the semiconductor device onto a metal frame.
【０００２】[0002]
【従来の技術】一般にシリコン基板上に形成された半導
体装置をリードフレーム等の金属フレーム上にダイボン
ディングするための技術として、リードフレームのダイ
ボンディングされる表面に部分Ａｕメッキを施してお
き、シリコン基板の裏面をこのＡｕメッキ上にペースト
や共晶合金等の固着材を利用して固着するものが提案さ
れている。例えば、半導体装置の裏面を機械的或いは化
学的に加工した後、数千オングストロームの薄膜メタル
を形成し、一方、リードフレームの表面にＡｕメッキを
施しておく。そして、半導体装置の裏面とリードフレー
ムの表面との間に固着材として金系合金を介在させ、こ
れを３６０℃前後の温度で加熱処理することで半導体装
置のシリコンとＡｕメッキとでＡｕ−Ｓｉ共晶を形成
し、半導体装置をリードフレームに固着させる。2. Description of the Related Art Generally, as a technique for die-bonding a semiconductor device formed on a silicon substrate to a metal frame such as a lead frame, a surface of the lead frame to be die-bonded is partially Au-plated, and silicon is used. It has been proposed to fix the back surface of the substrate on the Au plating by using a fixing material such as paste or eutectic alloy. For example, after the back surface of the semiconductor device is mechanically or chemically processed, a thin film metal of several thousand angstroms is formed, while the surface of the lead frame is plated with Au. Then, a gold alloy is interposed as a fixing material between the back surface of the semiconductor device and the front surface of the lead frame, and this is heat-treated at a temperature of about 360 ° C., so that the Au of the semiconductor device and the Au plating are Au—Si. A eutectic is formed and the semiconductor device is fixed to the lead frame.
【０００３】又、リードフレームのコストダウンをはか
る為に、リードフレームに銀メッキをほどこしておくや
りかたや、銅フレームに直接ダイボンディング及びワイ
ヤーボンディングをほどこしモールド終了後にリード部
分にのみ銀メッキをほどこす方法等が提唱されている。In order to reduce the cost of the lead frame, the lead frame is plated with silver, or the copper frame is directly die-bonded and wire-bonded, and only the lead portion is plated with silver after the molding is completed. Methods etc. have been proposed.
【０００４】又、最近の全自動ダイボンダの導入に伴っ
てダイボンディングの高速化が図られており、このため
上記したような固着材を用いたダイボンディング技術の
適用が困難になってきている。このため、近年では固着
材を使用しない搭載技術が提案されており、例えばその
一例として、シリコン基板の裏面に１μｍ程度のＡｕ膜
を直接形成し、このＡｕ膜と半導体装置のシリコンとで
Ａｕ−Ｓｉ共晶を形成し、かつＡｕ膜をリードフレーム
上に直接固着させる技術がある。Further, with the recent introduction of a fully automatic die bonder, the speed of die bonding has been increased, which makes it difficult to apply the die bonding technique using the fixing material as described above. Therefore, in recent years, a mounting technique that does not use a fixing material has been proposed. For example, as an example thereof, an Au film of about 1 μm is directly formed on the back surface of a silicon substrate, and the Au film and the silicon of the semiconductor device are Au— There is a technique of forming a Si eutectic and fixing the Au film directly on the lead frame.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、このよ
うに半導体装置の裏面に直接Ａｕ膜を形成する技術で
は、ダイボンディングの高速化は達成できるものの、シ
リコン基板にドープする不純物の濃度によってはどのよ
うなリードフレームに対しても固着強度の信頼性が低い
という問題点が生じている。即ち、シリコン基板にＳｂ
をハイドープした半導体装置では、長時間にわたる電気
的試験において半導体装置とリードフレームとの間が遊
離するという問題がある。又、シリコン基板の基板抵抗
が特性に影響をあたえるダイオード等の半導体装置にお
いては、シリコン基板にＳｂ以上にハイドープ可能なＡ
ｓをドープしたシリコン基板を使うと裏面にＡｕ膜を形
成した後、短期間の内にＡｕ膜表面の変色やＡｕ膜の剥
がれが生じ、変色が生じない場合でも固着強度が低下さ
れるという問題がある。However, although the technique of directly forming the Au film on the back surface of the semiconductor device as described above can speed up the die bonding, it may be difficult depending on the concentration of impurities to be doped into the silicon substrate. However, there is a problem that the reliability of the fixing strength is low even for a large lead frame. That is, Sb on the silicon substrate
The highly-doped semiconductor device has a problem that the semiconductor device and the lead frame are separated from each other in an electrical test for a long time. In a semiconductor device such as a diode in which the substrate resistance of the silicon substrate affects the characteristics, the silicon substrate can be highly doped with Sb or higher.
When a s-doped silicon substrate is used, after the Au film is formed on the back surface, discoloration of the Au film surface or peeling of the Au film occurs within a short period of time, and even if discoloration does not occur, the fixing strength is reduced. There is.
【０００６】これら不具合の原因としては、シリコン基
板にドープされているＳｂ，Ａｓ等の不純物がＡｕ膜に
拡散し、ＳｉとＡｕとの密着強度を低下させ、かつＡｕ
−Ｓｉ共晶化を妨げていることが考えられている。The cause of these problems is that impurities such as Sb and As doped in the silicon substrate diffuse into the Au film, and the adhesion strength between Si and Au is lowered, and Au is
It is believed that it hinders -Si eutecticization.
【０００７】本発明の目的は、シリコン基板に含まれる
不純物の影響による固着強度の低下を防止して、信頼性
を改善した半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device having improved reliability by preventing a decrease in fixing strength due to the influence of impurities contained in a silicon substrate.
【０００８】[0008]
【課題を解決するための手段】本発明の半導体装置は、
シリコン基板の裏面に形成されたＴｉ膜と、このＴｉ膜
上に形成されたＡｕ膜と、このＡｕ膜に固着される、金
属フレームに形成したＡｕ膜とを備えることを特徴とす
る。The semiconductor device of the present invention comprises:
It is characterized by comprising a Ti film formed on the back surface of the silicon substrate, an Au film formed on the Ti film, and an Au film formed on a metal frame and fixed to the Au film.
【０００９】この場合、上記Ｔｉ膜の厚さを５０〜１０
０オングストロームとし、上記Ａｕ膜の厚さを０．５μ
ｍ以上とすることが好ましい。In this case, the thickness of the Ti film is 50 to 10
The thickness of the Au film is set to 0 .ANG.
It is preferably m or more.
【００１０】[0010]
【作用】Ｔｉ膜によってシリコン基板中の不純物がＡｕ
膜にまで拡散することが防止でき、Ａｕ膜の変色やシリ
コン基板とＡｕ膜との共晶の阻害が防止される。[Function] The Ti film prevents the impurities in the silicon substrate from becoming Au.
The diffusion to the film can be prevented, and the discoloration of the Au film and the inhibition of the eutectic between the silicon substrate and the Au film can be prevented.
【００１１】[0011]
【実施例】次に、本発明について図面を参照して説明す
る。図１は本発明の一実施例の半導体装置の断面図であ
る。シリコン基板１の表面には図示を省略した種々の素
子を形成し、その表面は保護膜等で被覆される。又、シ
リコン基板１の裏面は研磨等によりシリコン面を露呈さ
せた上で、この裏面に５０オングストローム程度のＴｉ
膜２を蒸着法により形成し、更にこの上に１μｍ程度の
Ａｕ膜３を蒸着法により形成している。これらＴｉ膜２
及びＡｕ膜３の形成はウェハ状態で行い、その後ダイシ
ング工程でチップ状の半導体装置を得る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention. Various elements (not shown) are formed on the surface of the silicon substrate 1, and the surface is covered with a protective film or the like. The back surface of the silicon substrate 1 is exposed to the silicon surface by polishing or the like, and the back surface of the silicon substrate 1 is made of Ti of about 50 angstroms.
The film 2 is formed by the vapor deposition method, and the Au film 3 having a thickness of about 1 μm is further formed thereon by the vapor deposition method. These Ti films 2
The Au film 3 and the Au film 3 are formed in a wafer state, and then a chip-shaped semiconductor device is obtained by a dicing process.
【００１２】そして、このチップ状の半導体装置を、図
示を省略するＡｕメッキを施したリードフレーム上に載
置し、４４０〜４６０℃の温度でＡｕ膜３をＡｕメッキ
に一体化させることでリードフレームへ半導体装置を固
着する。Then, the chip-shaped semiconductor device is mounted on a lead frame (not shown) plated with Au, and the Au film 3 is integrated with the Au plating at a temperature of 440 to 460 ° C. Fix the semiconductor device to the frame.
【００１３】このように、半導体装置のシリコン基板１
の裏面にＴｉ膜２を形成した上でＡｕ膜３を形成するこ
とにより、シリコン基板１にドープされているＳｂ，Ａ
ｓ等の不純物がＴｉ膜２によって遮蔽され、Ａｕ膜３に
迄拡散されることが防止される。このため、Ａｕ膜３が
不純物によって変色されたり、或いはＳｉとＡｕとの共
晶が阻害されたりすることがなく、Ａｕ膜３とリードフ
レームのＡｕメッキとの一体化を促進し、リードフレー
ム上への半導体装置の固着強度を高めることが可能とな
る。As described above, the silicon substrate 1 of the semiconductor device
By forming a Ti film 2 on the back surface of the Au film 3 and then forming an Au film 3, Sb, A doped in the silicon substrate 1 is formed.
Impurities such as s are blocked by the Ti film 2 and prevented from diffusing to the Au film 3. Therefore, the Au film 3 is not discolored by impurities or the eutectic of Si and Au is not hindered, promoting the integration of the Au film 3 and the Au plating of the lead frame, and It is possible to increase the fixing strength of the semiconductor device to the semiconductor device.
【００１４】ここで、本発明者の実験によれば、図２に
示すように、Ｔｉ膜２を５０オングストローム以下の厚
さに形成すると、不純物がＡｕ膜３に拡散することを有
効に防止できず、逆に１００オングストローム以上の厚
さに形成すると、その上に形成したＡｕ膜３の変色は防
止できるが、ＳｉとＡｕとの共晶に影響が生じるように
なり、Ａｕ−Ｓｉ共晶ができなくなり、Ａｕ膜３が剥が
れ易くなる。又、メッキがほどこされていないリードフ
レームを用いる場合、図３に示すようにＡｕ膜３の厚さ
が５０００オングストローム以下では、Ｓｉとの共晶、
及びＡｕメッキへの固着に際しての金の絶対量が不足す
るようになり、固着強度が低下する。したがって、Ｔｉ
膜２の厚さを５０〜１００オングストローム，Ａｕ膜３
の厚さを０．５μｍ以上とすることが好ましい。According to an experiment conducted by the present inventor, it is possible to effectively prevent impurities from diffusing into the Au film 3 when the Ti film 2 is formed to a thickness of 50 angstroms or less as shown in FIG. On the contrary, if it is formed to have a thickness of 100 angstroms or more, discoloration of the Au film 3 formed thereon can be prevented, but the eutectic of Si and Au is affected, and the Au-Si eutectic crystal is formed. It becomes impossible, and the Au film 3 is easily peeled off. Further, when a lead frame which is not plated is used, as shown in FIG. 3, when the thickness of the Au film 3 is 5000 angstroms or less, a eutectic with Si,
Also, the absolute amount of gold becomes insufficient at the time of fixing to Au plating, and the fixing strength is reduced. Therefore, Ti
The film 2 has a thickness of 50 to 100 angstroms, and the Au film 3
The thickness is preferably 0.5 μm or more.
【００１５】[0015]
【発明の効果】以上説明したように本発明は、シリコン
基板の裏面にＴｉ膜を形成し、この上にＡｕ膜を形成し
て金属フレーム上のＡｕ膜に固着するように構成してい
るので、Ｔｉ膜によってシリコン基板中の不純物がＡｕ
膜にまで拡散することが防止され、ＳｉとＡｕとの共晶
が促進されてＡｕ膜の変色や剥がれが防止され、固着強
度の高いボンディングが実現できる効果がある。As described above, according to the present invention, the Ti film is formed on the back surface of the silicon substrate, the Au film is formed on the Ti film, and the Ti film is fixed to the Au film on the metal frame. , Ti film causes impurities in the silicon substrate to become Au.
It is possible to prevent the diffusion to the film, promote the eutectic of Si and Au, prevent discoloration and peeling of the Au film, and have an effect that bonding with high fixing strength can be realized.
【図１】本発明の半導体装置の一実施例の断面図であ
る。FIG. 1 is a sectional view of an embodiment of a semiconductor device of the present invention.
【図２】マウント強度不良率とＴｉ膜の厚さとの関係を
示すグラフである。FIG. 2 is a graph showing the relationship between the mount strength defect rate and the thickness of the Ti film.
【図３】マウント強度不良率とＡｕ膜３の厚さとの関係
を示すグラフである。FIG. 3 is a graph showing the relationship between the mount strength defective rate and the thickness of the Au film 3.
１ シリコン基板 ２ Ｔｉ膜 ３ Ａｕ膜 1 Silicon substrate 2 Ti film 3 Au film
Claims (1)
し、その裏面を金属フレーム等にダイボンディングする
半導体装置において、Ａｓを３×１０18ｃｍ3以上を含
むシリコン基板の裏面に形成した５０〜１００オングス
トロームのＴｉ膜と、このＴｉ膜上に形成した０．５μ
ｍ以上のＡｕ膜とを有し、このＡｕ膜を金属フレームに
直接固着するように構成したことを特徴とする半導体装
置。1. In a semiconductor device in which various elements are formed on the front surface of a silicon substrate and the back surface thereof is die-bonded to a metal frame or the like, As formed on the back surface of the silicon substrate containing 3 × 10 18 cm 3 or more of 50 to 50 100 Å Ti film and 0.5μ formed on this Ti film
A semiconductor device comprising an Au film of m or more, and the Au film being directly fixed to a metal frame.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10814991 | 1991-04-15 | ||
| JP3-108149 | 1991-04-15 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05299446A true JPH05299446A (en) | 1993-11-12 |
| JP2833335B2 JP2833335B2 (en) | 1998-12-09 |
Family
ID=14477190
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9511292A Expired - Fee Related JP2833335B2 (en) | 1991-04-15 | 1992-04-15 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2833335B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001065614A1 (en) * | 2000-03-01 | 2001-09-07 | Hamamatsu Photonics K.K. | Semiconductor laser device |
-
1992
- 1992-04-15 JP JP9511292A patent/JP2833335B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001065614A1 (en) * | 2000-03-01 | 2001-09-07 | Hamamatsu Photonics K.K. | Semiconductor laser device |
| JP2001244548A (en) * | 2000-03-01 | 2001-09-07 | Hamamatsu Photonics Kk | Semiconductor laser device |
| US6920164B2 (en) | 2000-03-01 | 2005-07-19 | Hamamatsu Photonics K.K. | Semiconductor laser device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2833335B2 (en) | 1998-12-09 |
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